Drop patch that got merged upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+++ /dev/null
-From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:24 +0100
-Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for
- gcc_pxo_pll8_pll0
-
-Parent gcc_pxo_pll8_pll0 had the parent definition and parent map
-swapped. Fix this naming error.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[]
- "pll3",
- };
-
--static const struct parent_map gcc_pxo_pll8_pll0[] = {
-+static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
- { P_PXO, 0 },
- { P_PLL8, 3 },
- { P_PLL0, 2 }
- };
-
--static const char * const gcc_pxo_pll8_pll0_map[] = {
-+static const char * const gcc_pxo_pll8_pll0[] = {
- "pxo",
- "pll8_vote",
- "pll0_vote",
-@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s
- },
- .s = {
- .src_sel_shift = 0,
-- .parent_map = gcc_pxo_pll8_pll0,
-+ .parent_map = gcc_pxo_pll8_pll0_map,
- },
- .freq_tbl = clk_tbl_usb30_master,
- .clkr = {
-@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_master_ref_src",
-- .parent_names = gcc_pxo_pll8_pll0_map,
-+ .parent_names = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = {
- },
- .s = {
- .src_sel_shift = 0,
-- .parent_map = gcc_pxo_pll8_pll0,
-+ .parent_map = gcc_pxo_pll8_pll0_map,
- },
- .freq_tbl = clk_tbl_usb30_utmi,
- .clkr = {
-@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_utmi_clk",
-- .parent_names = gcc_pxo_pll8_pll0_map,
-+ .parent_names = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
- },
- .s = {
- .src_sel_shift = 0,
-- .parent_map = gcc_pxo_pll8_pll0,
-+ .parent_map = gcc_pxo_pll8_pll0_map,
- },
- .freq_tbl = clk_tbl_usb,
- .clkr = {
-@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb_hs1_xcvr_src",
-- .parent_names = gcc_pxo_pll8_pll0_map,
-+ .parent_names = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
- },
- .s = {
- .src_sel_shift = 0,
-- .parent_map = gcc_pxo_pll8_pll0,
-+ .parent_map = gcc_pxo_pll8_pll0_map,
- },
- .freq_tbl = clk_tbl_usb,
- .clkr = {
-@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb_fs1_xcvr_src",
-- .parent_names = gcc_pxo_pll8_pll0_map,
-+ .parent_names = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
+++ /dev/null
-From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:25 +0100
-Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to
- parent_data
-
-Convert parent_names to parent_data to modernize the driver.
-Where possible use parent_hws directly.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++-------------
- 1 file changed, 173 insertions(+), 113 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -25,6 +25,10 @@
- #include "clk-hfpll.h"
- #include "reset.h"
-
-+static const struct clk_parent_data gcc_pxo[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+};
-+
- static struct clk_pll pll0 = {
- .l_reg = 0x30c4,
- .m_reg = 0x30c8,
-@@ -35,7 +39,7 @@ static struct clk_pll pll0 = {
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll0",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "pll0_vote",
-- .parent_names = (const char *[]){ "pll0" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pll0.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-@@ -62,7 +68,7 @@ static struct clk_pll pll3 = {
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll3",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -89,7 +95,7 @@ static struct clk_pll pll8 = {
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll8",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = {
- .enable_mask = BIT(8),
- .hw.init = &(struct clk_init_data){
- .name = "pll8_vote",
-- .parent_names = (const char *[]){ "pll8" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pll8.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = {
- static struct clk_hfpll hfpll0 = {
- .d = &hfpll0_data,
- .clkr.hw.init = &(struct clk_init_data){
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .name = "hfpll0",
- .ops = &clk_ops_hfpll,
-@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = {
- static struct clk_hfpll hfpll1 = {
- .d = &hfpll1_data,
- .clkr.hw.init = &(struct clk_init_data){
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .name = "hfpll1",
- .ops = &clk_ops_hfpll,
-@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data =
- static struct clk_hfpll hfpll_l2 = {
- .d = &hfpll_l2_data,
- .clkr.hw.init = &(struct clk_init_data){
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .name = "hfpll_l2",
- .ops = &clk_ops_hfpll,
-@@ -194,7 +202,7 @@ static struct clk_pll pll14 = {
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll14",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = {
- .enable_mask = BIT(14),
- .hw.init = &(struct clk_init_data){
- .name = "pll14_vote",
-- .parent_names = (const char *[]){ "pll14" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pll14.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-@@ -238,7 +248,7 @@ static struct clk_pll pll18 = {
- .freq_tbl = pll18_freq_tbl,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll18",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p
- { P_PLL8, 3 }
- };
-
--static const char * const gcc_pxo_pll8[] = {
-- "pxo",
-- "pll8_vote",
-+static const struct clk_parent_data gcc_pxo_pll8[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .hw = &pll8_vote.hw },
- };
-
- static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
-@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p
- { P_CXO, 5 }
- };
-
--static const char * const gcc_pxo_pll8_cxo[] = {
-- "pxo",
-- "pll8_vote",
-- "cxo",
-+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .hw = &pll8_vote.hw },
-+ { .fw_name = "cxo", .name = "cxo" },
- };
-
- static const struct parent_map gcc_pxo_pll3_map[] = {
-@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p
- { P_PLL3, 6 }
- };
-
--static const char * const gcc_pxo_pll3[] = {
-- "pxo",
-- "pll3",
-+static const struct clk_parent_data gcc_pxo_pll3[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .hw = &pll3.clkr.hw },
- };
-
- static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
-@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p
- { P_PLL0, 2 }
- };
-
--static const char * const gcc_pxo_pll8_pll0[] = {
-- "pxo",
-- "pll8_vote",
-- "pll0_vote",
-+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .hw = &pll8_vote.hw },
-+ { .hw = &pll0_vote.hw },
- };
-
- static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
-@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p
- { P_PLL18, 1 }
- };
-
--static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
-- "pxo",
-- "pll8_vote",
-- "pll0_vote",
-- "pll14",
-- "pll18",
-+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .hw = &pll8_vote.hw },
-+ { .hw = &pll0_vote.hw },
-+ { .hw = &pll14.clkr.hw },
-+ { .hw = &pll18.clkr.hw },
- };
-
- static struct freq_tbl clk_tbl_gsbi_uart[] = {
-@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi1_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi1_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi2_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi2_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi4_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi4_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi5_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi5_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi6_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi6_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_uart_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_uart_clk",
-- .parent_names = (const char *[]){
-- "gsbi7_uart_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi7_uart_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_qup_clk",
-- .parent_names = (const char *[]){ "gsbi1_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi1_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_qup_clk",
-- .parent_names = (const char *[]){ "gsbi2_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi2_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_qup_clk",
-- .parent_names = (const char *[]){ "gsbi4_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi4_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_qup_clk",
-- .parent_names = (const char *[]){ "gsbi5_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi5_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_qup_clk",
-- .parent_names = (const char *[]){ "gsbi6_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi6_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_qup_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_qup_clk",
-- .parent_names = (const char *[]){ "gsbi7_qup_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gsbi7_qup_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gp0_src",
-- .parent_names = gcc_pxo_pll8_cxo,
-+ .parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
-@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gp0_clk",
-- .parent_names = (const char *[]){ "gp0_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp0_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gp1_src",
-- .parent_names = gcc_pxo_pll8_cxo,
-+ .parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gp1_clk",
-- .parent_names = (const char *[]){ "gp1_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp1_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "gp2_src",
-- .parent_names = gcc_pxo_pll8_cxo,
-+ .parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "gp2_clk",
-- .parent_names = (const char *[]){ "gp2_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gp2_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "prng_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- },
-@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = {
- .enable_mask = BIT(10),
- .hw.init = &(struct clk_init_data){
- .name = "prng_clk",
-- .parent_names = (const char *[]){ "prng_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &prng_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- },
-@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "sdc1_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- },
-@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "sdc1_clk",
-- .parent_names = (const char *[]){ "sdc1_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdc1_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "sdc3_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- },
-@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "sdc3_clk",
-- .parent_names = (const char *[]){ "sdc3_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sdc3_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "tsif_ref_src",
-- .parent_names = gcc_pxo_pll8,
-+ .parent_data = gcc_pxo_pll8,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- },
-@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk =
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "tsif_ref_clk",
-- .parent_names = (const char *[]){ "tsif_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &tsif_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "pcie_ref_src",
-- .parent_names = gcc_pxo_pll3,
-+ .parent_data = gcc_pxo_pll3,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "pcie_ref_src_clk",
-- .parent_names = (const char *[]){ "pcie_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_ref_src",
-- .parent_names = gcc_pxo_pll3,
-+ .parent_data = gcc_pxo_pll3,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_ref_src_clk",
-- .parent_names = (const char *[]){ "pcie1_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie1_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "pcie2_ref_src",
-- .parent_names = gcc_pxo_pll3,
-+ .parent_data = gcc_pxo_pll3,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "pcie2_ref_src_clk",
-- .parent_names = (const char *[]){ "pcie2_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcie2_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = {
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "sata_ref_src",
-- .parent_names = gcc_pxo_pll3,
-+ .parent_data = gcc_pxo_pll3,
- .num_parents = 2,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "sata_rxoob_clk",
-- .parent_names = (const char *[]){ "sata_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sata_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "sata_pmalive_clk",
-- .parent_names = (const char *[]){ "sata_ref_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &sata_ref_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "sata_phy_ref_clk",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = gcc_pxo,
- .num_parents = 1,
- .ops = &clk_branch_ops,
- },
-@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_master_ref_src",
-- .parent_names = gcc_pxo_pll8_pll0,
-+ .parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_0_branch_clk",
-- .parent_names = (const char *[]){ "usb30_master_ref_src", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_1_branch_clk",
-- .parent_names = (const char *[]){ "usb30_master_ref_src", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_master_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_utmi_clk",
-- .parent_names = gcc_pxo_pll8_pll0,
-+ .parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_0_utmi_clk_ctl",
-- .parent_names = (const char *[]){ "usb30_utmi_clk", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_utmi_clk.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "usb30_1_utmi_clk_ctl",
-- .parent_names = (const char *[]){ "usb30_utmi_clk", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb30_utmi_clk.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb_hs1_xcvr_src",
-- .parent_names = gcc_pxo_pll8_pll0,
-+ .parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "usb_hs1_xcvr_clk",
-- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb_hs1_xcvr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "usb_fs1_xcvr_src",
-- .parent_names = gcc_pxo_pll8_pll0,
-+ .parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
-@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "usb_fs1_xcvr_clk",
-- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb_fs1_xcvr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "usb_fs1_sys_clk",
-- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &usb_fs1_xcvr_clk_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core1_src",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- },
-@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core1_clk",
-- .parent_names = (const char *[]){
-- "gmac_core1_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gmac_core1_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core2_src",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- },
-@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core2_clk",
-- .parent_names = (const char *[]){
-- "gmac_core2_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gmac_core2_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core3_src",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- },
-@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core3_clk",
-- .parent_names = (const char *[]){
-- "gmac_core3_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gmac_core3_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core4_src",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- },
-@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core4_clk",
-- .parent_names = (const char *[]){
-- "gmac_core4_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &gmac_core4_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src =
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "nss_tcm_src",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- },
-@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = {
- .enable_mask = BIT(6) | BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "nss_tcm_clk",
-- .parent_names = (const char *[]){
-- "nss_tcm_src",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &nss_tcm_src.clkr.hw,
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_core1_src_clk",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
-@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_core2_src_clk",
-- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
-+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
- .ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+++ /dev/null
-From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:26 +0100
-Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
-
-Use ARRAY_SIZE for num_parents instead of hardcoding the value.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
- 1 file changed, 34 insertions(+), 34 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_uart_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi1_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi2_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi5_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi6_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi7_qup_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gp0_src",
- .parent_data = gcc_pxo_pll8_cxo,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
- },
-@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gp1_src",
- .parent_data = gcc_pxo_pll8_cxo,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = {
- .hw.init = &(struct clk_init_data){
- .name = "gp2_src",
- .parent_data = gcc_pxo_pll8_cxo,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = {
- .hw.init = &(struct clk_init_data){
- .name = "prng_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- },
- },
-@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = {
- .hw.init = &(struct clk_init_data){
- .name = "sdc1_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- },
- }
-@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = {
- .hw.init = &(struct clk_init_data){
- .name = "sdc3_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- },
- }
-@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = {
- .hw.init = &(struct clk_init_data){
- .name = "tsif_ref_src",
- .parent_data = gcc_pxo_pll8,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
- },
- }
-@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie_ref_src",
- .parent_data = gcc_pxo_pll3,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_ref_src",
- .parent_data = gcc_pxo_pll3,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie2_ref_src",
- .parent_data = gcc_pxo_pll3,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = {
- .hw.init = &(struct clk_init_data){
- .name = "sata_ref_src",
- .parent_data = gcc_pxo_pll3,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s
- .hw.init = &(struct clk_init_data){
- .name = "usb30_master_ref_src",
- .parent_data = gcc_pxo_pll8_pll0,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = {
- .hw.init = &(struct clk_init_data){
- .name = "usb30_utmi_clk",
- .parent_data = gcc_pxo_pll8_pll0,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s
- .hw.init = &(struct clk_init_data){
- .name = "usb_hs1_xcvr_src",
- .parent_data = gcc_pxo_pll8_pll0,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s
- .hw.init = &(struct clk_init_data){
- .name = "usb_fs1_xcvr_src",
- .parent_data = gcc_pxo_pll8_pll0,
-- .num_parents = 3,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core1_src",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- },
- },
-@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core2_src",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- },
- },
-@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core3_src",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- },
- },
-@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src
- .hw.init = &(struct clk_init_data){
- .name = "gmac_core4_src",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- },
- },
-@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src =
- .hw.init = &(struct clk_init_data){
- .name = "nss_tcm_src",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- },
- },
-@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_core1_src_clk",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
- },
-@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_core2_src_clk",
- .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
-- .num_parents = 5,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
- .ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
- },
+++ /dev/null
-From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:27 +0100
-Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores
-
-Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
-clocked to 800MHz. Add these missing freq to the gcc driver.
-Set the freq_tbl for the ubi32_cores to the correct values based on the
-machine compatible.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
- 1 file changed, 21 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
-
- static struct pll_freq_tbl pll18_freq_tbl[] = {
- NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
-+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
- NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
-+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
- };
-
- static struct clk_pll pll18 = {
-@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = {
- },
- };
-
--static const struct freq_tbl clk_tbl_nss[] = {
-+static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
- { 110000000, P_PLL18, 1, 1, 5 },
- { 275000000, P_PLL18, 2, 0, 0 },
- { 550000000, P_PLL18, 1, 0, 0 },
-@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss
- { }
- };
-
-+static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
-+ { 110000000, P_PLL18, 1, 1, 5 },
-+ { 275000000, P_PLL18, 2, 0, 0 },
-+ { 600000000, P_PLL18, 1, 0, 0 },
-+ { 800000000, P_PLL18, 1, 0, 0 },
-+ { }
-+};
-+
- static struct clk_dyn_rcg ubi32_core1_src_clk = {
- .ns_reg[0] = 0x3d2c,
- .ns_reg[1] = 0x3d30,
-@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
- .pre_div_width = 2,
- },
- .mux_sel_bit = 0,
-- .freq_tbl = clk_tbl_nss,
-+ /* nss freq table is selected based on the SoC compatible */
- .clkr = {
- .enable_reg = 0x3d20,
- .enable_mask = BIT(1),
-@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
- .pre_div_width = 2,
- },
- .mux_sel_bit = 0,
-- .freq_tbl = clk_tbl_nss,
-+ /* nss freq table is selected based on the SoC compatible */
- .clkr = {
- .enable_reg = 0x3d40,
- .enable_mask = BIT(1),
-@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat
- if (ret)
- return ret;
-
-+ if (of_machine_is_compatible("qcom,ipq8065")) {
-+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
-+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
-+ } else {
-+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
-+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
-+ }
-+
- ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
- if (ret)
- return ret;
+++ /dev/null
-From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:28 +0100
-Subject: [PATCH 08/14] clk: qcom: gcc-ipq806x: add unusued flag for critical
- clock
-
-Some clocks are used by other devices present on the SoC. For example
-the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to
-reject any regulator change command. These clock should never be
-disabled.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++----
- 1 file changed, 5 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = {
- .parent_data = gcc_pxo_pll8,
- .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
-- .flags = CLK_SET_PARENT_GATE,
-+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
- },
- },
- };
-@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk =
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-- .flags = CLK_SET_RATE_PARENT,
-+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- },
- },
- };
-@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = {
- .parent_data = gcc_pxo_pll8,
- .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
-- .flags = CLK_SET_PARENT_GATE,
-+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
- },
- },
- };
-@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk =
- },
- .num_parents = 1,
- .ops = &clk_branch_ops,
-- .flags = CLK_SET_RATE_PARENT,
-+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
- },
- },
- };
-@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = {
- .hw.init = &(struct clk_init_data){
- .name = "gsbi4_h_clk",
- .ops = &clk_branch_ops,
-+ .flags = CLK_IGNORE_UNUSED,
- },
- },
- };
+++ /dev/null
-From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:29 +0100
-Subject: [PATCH 09/14] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
-
-Add clk_rcg_floor_ops for clock that can't provide a stable freq and
-require to use a floor freq to provide the requested frequency.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com
----
- drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++
- drivers/clk/qcom/clk-rcg.h | 1 +
- 2 files changed, 25 insertions(+)
-
---- a/drivers/clk/qcom/clk-rcg.c
-+++ b/drivers/clk/qcom/clk-rcg.c
-@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_h
- return __clk_rcg_set_rate(rcg, f);
- }
-
-+static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long parent_rate)
-+{
-+ struct clk_rcg *rcg = to_clk_rcg(hw);
-+ const struct freq_tbl *f;
-+
-+ f = qcom_find_freq_floor(rcg->freq_tbl, rate);
-+ if (!f)
-+ return -EINVAL;
-+
-+ return __clk_rcg_set_rate(rcg, f);
-+}
-+
- static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = {
- };
- EXPORT_SYMBOL_GPL(clk_rcg_ops);
-
-+const struct clk_ops clk_rcg_floor_ops = {
-+ .enable = clk_enable_regmap,
-+ .disable = clk_disable_regmap,
-+ .get_parent = clk_rcg_get_parent,
-+ .set_parent = clk_rcg_set_parent,
-+ .recalc_rate = clk_rcg_recalc_rate,
-+ .determine_rate = clk_rcg_determine_rate,
-+ .set_rate = clk_rcg_set_floor_rate,
-+};
-+EXPORT_SYMBOL_GPL(clk_rcg_floor_ops);
-+
- const struct clk_ops clk_rcg_bypass_ops = {
- .enable = clk_enable_regmap,
- .disable = clk_disable_regmap,
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -86,6 +86,7 @@ struct clk_rcg {
- };
-
- extern const struct clk_ops clk_rcg_ops;
-+extern const struct clk_ops clk_rcg_floor_ops;
- extern const struct clk_ops clk_rcg_bypass_ops;
- extern const struct clk_ops clk_rcg_bypass2_ops;
- extern const struct clk_ops clk_rcg_pixel_ops;
+++ /dev/null
-From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:30 +0100
-Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc
- table
-
-Add additional freq supported for the sdc table. The ops are changed to
-the floor_ops to handle a freq request of 52kHz where we need to provide
-a freq of 51.2kHz instead for stability reason.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc
- { 20210000, P_PLL8, 1, 1, 19 },
- { 24000000, P_PLL8, 4, 1, 4 },
- { 48000000, P_PLL8, 4, 1, 2 },
-+ { 51200000, P_PLL8, 1, 2, 15 },
- { 64000000, P_PLL8, 3, 1, 2 },
- { 96000000, P_PLL8, 4, 0, 0 },
- { 192000000, P_PLL8, 2, 0, 0 },
-@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = {
- .name = "sdc1_src",
- .parent_data = gcc_pxo_pll8,
- .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
-- .ops = &clk_rcg_ops,
-+ .ops = &clk_rcg_floor_ops,
- },
- }
- };
+++ /dev/null
-From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:31 +0100
-Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define
-
-Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver.
-Define CE5_SRC is not used so it's OK to change and we align it to
-the QSDK naming.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
-@@ -240,7 +240,7 @@
- #define PLL14 232
- #define PLL14_VOTE 233
- #define PLL18 234
--#define CE5_SRC 235
-+#define CE5_A_CLK 235
- #define CE5_H_CLK 236
- #define CE5_CORE_CLK 237
- #define CE3_SLEEP_CLK 238
-@@ -283,5 +283,8 @@
- #define EBI2_AON_CLK 281
- #define NSSTCM_CLK_SRC 282
- #define NSSTCM_CLK 283
-+#define CE5_A_CLK_SRC 285
-+#define CE5_H_CLK_SRC 286
-+#define CE5_CORE_CLK_SRC 287
-
- #endif
+++ /dev/null
-From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:32 +0100
-Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks
-
-Add missing CryptoEngine clocks and pll11 required clock.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++
- 1 file changed, 244 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -256,6 +256,24 @@ static struct clk_pll pll18 = {
- },
- };
-
-+static struct clk_pll pll11 = {
-+ .l_reg = 0x3184,
-+ .m_reg = 0x3188,
-+ .n_reg = 0x318c,
-+ .config_reg = 0x3194,
-+ .mode_reg = 0x3180,
-+ .status_reg = 0x3198,
-+ .status_bit = 16,
-+ .clkr.hw.init = &(struct clk_init_data){
-+ .name = "pll11",
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "pxo",
-+ },
-+ .num_parents = 1,
-+ .ops = &clk_pll_ops,
-+ },
-+};
-+
- enum {
- P_PXO,
- P_PLL8,
-@@ -264,6 +282,7 @@ enum {
- P_CXO,
- P_PLL14,
- P_PLL18,
-+ P_PLL11,
- };
-
- static const struct parent_map gcc_pxo_pll8_map[] = {
-@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_
- { .hw = &pll18.clkr.hw },
- };
-
-+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
-+ { P_PXO, 0 },
-+ { P_PLL8, 4 },
-+ { P_PLL0, 2 },
-+ { P_PLL14, 5 },
-+ { P_PLL18, 1 },
-+ { P_PLL11, 3 },
-+};
-+
-+static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
-+ { .fw_name = "pxo" },
-+ { .hw = &pll8_vote.hw },
-+ { .hw = &pll0_vote.hw },
-+ { .hw = &pll14.clkr.hw },
-+ { .hw = &pll18.clkr.hw },
-+ { .hw = &pll11.clkr.hw },
-+
-+};
-+
-+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
-+ { P_PXO, 0 },
-+ { P_PLL3, 6 },
-+ { P_PLL0, 2 },
-+ { P_PLL14, 5 },
-+ { P_PLL18, 1 },
-+ { P_PLL11, 3 },
-+};
-+
-+static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
-+ { .fw_name = "pxo" },
-+ { .hw = &pll3.clkr.hw },
-+ { .hw = &pll0_vote.hw },
-+ { .hw = &pll14.clkr.hw },
-+ { .hw = &pll18.clkr.hw },
-+ { .hw = &pll11.clkr.hw },
-+
-+};
-+
- static struct freq_tbl clk_tbl_gsbi_uart[] = {
- { 1843200, P_PLL8, 2, 6, 625 },
- { 3686400, P_PLL8, 2, 12, 625 },
-@@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
- },
- };
-
-+static const struct freq_tbl clk_tbl_ce5_core[] = {
-+ { 150000000, P_PLL3, 8, 1, 1 },
-+ { 213200000, P_PLL11, 5, 1, 1 },
-+ { }
-+};
-+
-+static struct clk_dyn_rcg ce5_core_src = {
-+ .ns_reg[0] = 0x36C4,
-+ .ns_reg[1] = 0x36C8,
-+ .bank_reg = 0x36C0,
-+ .s[0] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
-+ },
-+ .s[1] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
-+ },
-+ .p[0] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .p[1] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .mux_sel_bit = 0,
-+ .freq_tbl = clk_tbl_ce5_core,
-+ .clkr = {
-+ .enable_reg = 0x36C0,
-+ .enable_mask = BIT(1),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_core_src",
-+ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
-+ .ops = &clk_dyn_rcg_ops,
-+ },
-+ },
-+};
-+
-+static struct clk_branch ce5_core_clk = {
-+ .halt_reg = 0x2FDC,
-+ .halt_bit = 5,
-+ .hwcg_reg = 0x36CC,
-+ .hwcg_bit = 6,
-+ .clkr = {
-+ .enable_reg = 0x36CC,
-+ .enable_mask = BIT(4),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_core_clk",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ce5_core_src.clkr.hw,
-+ },
-+ .num_parents = 1,
-+ .ops = &clk_branch_ops,
-+ .flags = CLK_SET_RATE_PARENT,
-+ },
-+ },
-+};
-+
-+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
-+ { 160000000, P_PLL0, 5, 1, 1 },
-+ { 213200000, P_PLL11, 5, 1, 1 },
-+ { }
-+};
-+
-+static struct clk_dyn_rcg ce5_a_clk_src = {
-+ .ns_reg[0] = 0x3d84,
-+ .ns_reg[1] = 0x3d88,
-+ .bank_reg = 0x3d80,
-+ .s[0] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
-+ },
-+ .s[1] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
-+ },
-+ .p[0] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .p[1] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .mux_sel_bit = 0,
-+ .freq_tbl = clk_tbl_ce5_a_clk,
-+ .clkr = {
-+ .enable_reg = 0x3d80,
-+ .enable_mask = BIT(1),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_a_clk_src",
-+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
-+ .ops = &clk_dyn_rcg_ops,
-+ },
-+ },
-+};
-+
-+static struct clk_branch ce5_a_clk = {
-+ .halt_reg = 0x3c20,
-+ .halt_bit = 12,
-+ .hwcg_reg = 0x3d8c,
-+ .hwcg_bit = 6,
-+ .clkr = {
-+ .enable_reg = 0x3d8c,
-+ .enable_mask = BIT(4),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_a_clk",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ce5_a_clk_src.clkr.hw,
-+ },
-+ .num_parents = 1,
-+ .ops = &clk_branch_ops,
-+ .flags = CLK_SET_RATE_PARENT,
-+ },
-+ },
-+};
-+
-+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
-+ { 160000000, P_PLL0, 5, 1, 1 },
-+ { 213200000, P_PLL11, 5, 1, 1 },
-+ { }
-+};
-+
-+static struct clk_dyn_rcg ce5_h_clk_src = {
-+ .ns_reg[0] = 0x3c64,
-+ .ns_reg[1] = 0x3c68,
-+ .bank_reg = 0x3c60,
-+ .s[0] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
-+ },
-+ .s[1] = {
-+ .src_sel_shift = 0,
-+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
-+ },
-+ .p[0] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .p[1] = {
-+ .pre_div_shift = 3,
-+ .pre_div_width = 4,
-+ },
-+ .mux_sel_bit = 0,
-+ .freq_tbl = clk_tbl_ce5_h_clk,
-+ .clkr = {
-+ .enable_reg = 0x3c60,
-+ .enable_mask = BIT(1),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_h_clk_src",
-+ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
-+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
-+ .ops = &clk_dyn_rcg_ops,
-+ },
-+ },
-+};
-+
-+static struct clk_branch ce5_h_clk = {
-+ .halt_reg = 0x3c20,
-+ .halt_bit = 11,
-+ .hwcg_reg = 0x3c6c,
-+ .hwcg_bit = 6,
-+ .clkr = {
-+ .enable_reg = 0x3c6c,
-+ .enable_mask = BIT(4),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "ce5_h_clk",
-+ .parent_hws = (const struct clk_hw*[]){
-+ &ce5_h_clk_src.clkr.hw,
-+ },
-+ .num_parents = 1,
-+ .ops = &clk_branch_ops,
-+ .flags = CLK_SET_RATE_PARENT,
-+ },
-+ },
-+};
-+
- static struct clk_regmap *gcc_ipq806x_clks[] = {
- [PLL0] = &pll0.clkr,
- [PLL0_VOTE] = &pll0_vote,
-@@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl
- [PLL4_VOTE] = &pll4_vote,
- [PLL8] = &pll8.clkr,
- [PLL8_VOTE] = &pll8_vote,
-+ [PLL11] = &pll11.clkr,
- [PLL14] = &pll14.clkr,
- [PLL14_VOTE] = &pll14_vote,
- [PLL18] = &pll18.clkr,
-@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl
- [PLL9] = &hfpll0.clkr,
- [PLL10] = &hfpll1.clkr,
- [PLL12] = &hfpll_l2.clkr,
-+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
-+ [CE5_A_CLK] = &ce5_a_clk.clkr,
-+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
-+ [CE5_H_CLK] = &ce5_h_clk.clkr,
-+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
-+ [CE5_CORE_CLK] = &ce5_core_clk.clkr,
- };
-
- static const struct qcom_reset_map gcc_ipq806x_resets[] = {
+++ /dev/null
-From f4a7e56f4956f0450b9f671ed93d45ffcc15aa62 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 01:22:05 +0100
-Subject: [PATCH v6 13/15] dt-bindings: reset: add ipq8064 ce5 resets
-
-Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
-+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
-@@ -163,5 +163,10 @@
- #define NSS_CAL_PRBS_RST_N_RESET 154
- #define NSS_LCKDT_RST_N_RESET 155
- #define NSS_SRDS_N_RESET 156
-+#define CRYPTO_ENG1_RESET 157
-+#define CRYPTO_ENG2_RESET 158
-+#define CRYPTO_ENG3_RESET 159
-+#define CRYPTO_ENG4_RESET 160
-+#define CRYPTO_AHB_RESET 161
-
- #endif
+++ /dev/null
-From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:34 +0100
-Subject: [PATCH 14/14] clk: qcom: gcc-ipq806x: add CryptoEngine resets
-
-Add missing CryptoEngine resets.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_i
- [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
- [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
- [GMAC_AHB_RESET] = { 0x3e24, 0 },
-+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
-+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
-+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
-+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
-+ [CRYPTO_AHB_RESET] = { 0x3e10, 0},
- [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
- [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
- [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
+++ /dev/null
-From 9ec092d2feb69045dd289845024301fb91c064ee Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jun 2022 13:22:27 +0200
-Subject: [PATCH 1/2] net: ethernet: stmmac: add missing sgmii configure for
- ipq806x
-
-The different gmacid require different configuration based on the soc
-and on the gmac id. Add these missing configuration taken from the
-original driver.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20220614112228.1998-1-ansuelsmth@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
- .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 93 +++++++++++++++----
- 2 files changed, 78 insertions(+), 16 deletions(-)
-
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -83,6 +83,7 @@ config DWMAC_IPQ806X
- default ARCH_QCOM
- depends on OF && (ARCH_QCOM || COMPILE_TEST)
- select MFD_SYSCON
-+ select QCOM_SOCINFO
- help
- Support for QCA IPQ806X DWMAC Ethernet.
-
---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
-@@ -27,6 +27,8 @@
- #include <linux/stmmac.h>
- #include <linux/of_mdio.h>
- #include <linux/module.h>
-+#include <linux/sys_soc.h>
-+#include <linux/bitfield.h>
-
- #include "stmmac_platform.h"
-
-@@ -75,11 +77,20 @@
- #define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
- #define QSGMII_PHY_TX_DRIVER_EN BIT(3)
- #define QSGMII_PHY_QSGMII_EN BIT(7)
--#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12
--#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18
--#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20
--#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22
--#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28
-+#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10)
-+#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x))
-+#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12)
-+#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x))
-+#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18)
-+#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x))
-+#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20)
-+#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x))
-+#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22)
-+#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x))
-+#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26)
-+#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x))
-+#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28)
-+#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x))
-
- struct ipq806x_gmac {
- struct platform_device *pdev;
-@@ -242,6 +253,64 @@ static void ipq806x_gmac_fix_mac_speed(v
- ipq806x_gmac_set_speed(gmac, speed);
- }
-
-+static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
-+ {
-+ .revision = "1.*",
-+ },
-+ {
-+ /* sentinel */
-+ }
-+};
-+
-+static int
-+ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac)
-+{
-+ struct platform_device *pdev = gmac->pdev;
-+ const struct soc_device_attribute *soc;
-+ struct device *dev = &pdev->dev;
-+ u32 qsgmii_param;
-+
-+ switch (gmac->id) {
-+ case 1:
-+ soc = soc_device_match(ipq806x_gmac_soc_v1);
-+
-+ if (soc)
-+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) |
-+ QSGMII_PHY_TX_SLEW(0x2) |
-+ QSGMII_PHY_DEEMPHASIS_LVL(0x2);
-+ else
-+ qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) |
-+ QSGMII_PHY_TX_SLEW(0x0) |
-+ QSGMII_PHY_DEEMPHASIS_LVL(0x0);
-+
-+ qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2);
-+ break;
-+ case 2:
-+ case 3:
-+ qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) |
-+ QSGMII_PHY_TX_DRV_AMP(0xc);
-+ break;
-+ default: /* gmac 0 can't be set in SGMII mode */
-+ dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id);
-+ return -EINVAL;
-+ }
-+
-+ /* Common params across all gmac id */
-+ qsgmii_param |= QSGMII_PHY_CDR_EN |
-+ QSGMII_PHY_RX_FRONT_EN |
-+ QSGMII_PHY_RX_SIGNAL_DETECT_EN |
-+ QSGMII_PHY_TX_DRIVER_EN |
-+ QSGMII_PHY_QSGMII_EN |
-+ QSGMII_PHY_PHASE_LOOP_GAIN(0x4) |
-+ QSGMII_PHY_RX_INPUT_EQU(0x1) |
-+ QSGMII_PHY_CDR_PI_SLEW(0x2);
-+
-+ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
-+ qsgmii_param);
-+
-+ return 0;
-+}
-+
- static int ipq806x_gmac_probe(struct platform_device *pdev)
- {
- struct plat_stmmacenet_data *plat_dat;
-@@ -328,17 +397,9 @@ static int ipq806x_gmac_probe(struct pla
- regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
-
- if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
-- regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
-- QSGMII_PHY_CDR_EN |
-- QSGMII_PHY_RX_FRONT_EN |
-- QSGMII_PHY_RX_SIGNAL_DETECT_EN |
-- QSGMII_PHY_TX_DRIVER_EN |
-- QSGMII_PHY_QSGMII_EN |
-- 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
-- 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
-- 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
-- 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
-- 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
-+ err = ipq806x_gmac_configure_qsgmii_params(gmac);
-+ if (err)
-+ goto err_remove_config_dt;
- }
-
- plat_dat->has_gmac = true;
+++ /dev/null
-From 8bca458990dd8c6d001b2fb52063aa18e8ca7444 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jun 2022 13:22:28 +0200
-Subject: [PATCH 2/2] net: ethernet: stmmac: reset force speed bit for ipq806x
-
-Some bootloader may set the force speed regs even if the actual
-interface should use autonegotiation between PCS and PHY.
-This cause the complete malfuction of the interface.
-
-To fix this correctly reset the force speed regs if a fixed-link is not
-defined in the DTS. With a fixed-link node correctly configure the
-forced speed regs to handle any misconfiguration by the bootloader.
-
-Reported-by: Mark Mentovai <mark@moxienet.com>
-Co-developed-by: Mark Mentovai <mark@moxienet.com>
-Signed-off-by: Mark Mentovai <mark@moxienet.com>
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20220614112228.1998-2-ansuelsmth@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- .../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 64 +++++++++++++++++++
- 1 file changed, 64 insertions(+)
-
---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
-@@ -66,6 +66,17 @@
- #define NSS_COMMON_CLK_DIV_SGMII_100 4
- #define NSS_COMMON_CLK_DIV_SGMII_10 49
-
-+#define QSGMII_PCS_ALL_CH_CTL 0x80
-+#define QSGMII_PCS_CH_SPEED_FORCE BIT(1)
-+#define QSGMII_PCS_CH_SPEED_10 0x0
-+#define QSGMII_PCS_CH_SPEED_100 BIT(2)
-+#define QSGMII_PCS_CH_SPEED_1000 BIT(3)
-+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \
-+ QSGMII_PCS_CH_SPEED_10 | \
-+ QSGMII_PCS_CH_SPEED_100 | \
-+ QSGMII_PCS_CH_SPEED_1000)
-+#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4)
-+
- #define QSGMII_PCS_CAL_LCKDT_CTL 0x120
- #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
-
-@@ -253,6 +264,55 @@ static void ipq806x_gmac_fix_mac_speed(v
- ipq806x_gmac_set_speed(gmac, speed);
- }
-
-+static int
-+ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac)
-+{
-+ struct platform_device *pdev = gmac->pdev;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *dn;
-+ int link_speed;
-+ int val = 0;
-+ int ret;
-+
-+ /* Some bootloader may apply wrong configuration and cause
-+ * not functioning port. If fixed link is not set,
-+ * reset the force speed bit.
-+ */
-+ if (!of_phy_is_fixed_link(pdev->dev.of_node))
-+ goto write;
-+
-+ dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link");
-+ ret = of_property_read_u32(dn, "speed", &link_speed);
-+ of_node_put(dn);
-+ if (ret) {
-+ dev_err(dev, "found fixed-link node with no speed");
-+ return ret;
-+ }
-+
-+ val = QSGMII_PCS_CH_SPEED_FORCE;
-+
-+ switch (link_speed) {
-+ case SPEED_1000:
-+ val |= QSGMII_PCS_CH_SPEED_1000;
-+ break;
-+ case SPEED_100:
-+ val |= QSGMII_PCS_CH_SPEED_100;
-+ break;
-+ case SPEED_10:
-+ val |= QSGMII_PCS_CH_SPEED_10;
-+ break;
-+ }
-+
-+write:
-+ regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL,
-+ QSGMII_PCS_CH_SPEED_MASK <<
-+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
-+ val <<
-+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id));
-+
-+ return 0;
-+}
-+
- static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
- {
- .revision = "1.*",
-@@ -400,6 +460,10 @@ static int ipq806x_gmac_probe(struct pla
- err = ipq806x_gmac_configure_qsgmii_params(gmac);
- if (err)
- goto err_remove_config_dt;
-+
-+ err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac);
-+ if (err)
-+ goto err_remove_config_dt;
- }
-
- plat_dat->has_gmac = true;
+++ /dev/null
-From a5ba119455c77a07e05f2fe0af446c8bf43d1a00 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 26 Feb 2022 14:52:35 +0100
-Subject: [PATCH] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for
- ipq8064
-
-Add syscon compatible required for tsens driver to correctly probe driver
-and access the reg. Also add cxo and pxo tag and declare them as gcc clock
-now requires them for the ipq8064 gcc driver that has now been modernized.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220226135235.10051-16-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -298,13 +298,13 @@
- };
-
- clocks {
-- cxo_board {
-+ cxo_board: cxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
-- pxo_board {
-+ pxo_board: pxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
-@@ -736,7 +736,9 @@
- };
-
- gcc: clock-controller@900000 {
-- compatible = "qcom,gcc-ipq8064";
-+ compatible = "qcom,gcc-ipq8064", "syscon";
-+ clocks = <&pxo_board>, <&cxo_board>;
-+ clock-names = "pxo", "cxo";
- reg = <0x00900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
+++ /dev/null
-From eb9e93937756a05787977875830c0dc482cb57e0 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 30 Apr 2022 07:51:17 +0200
-Subject: [PATCH] ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock
-
-Replace gcc PXO phandle to pxo_board fixed clock declared in the dts.
-gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a
-kernel panic if any driver actually try to use it.
-
-Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064")
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220430055118.1947-2-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -784,7 +784,7 @@
- l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc", "syscon";
- reg = <0x2011000 0x1000>;
-- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
-+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
- };
+++ /dev/null
-From 4af1defb305798d1a064a5ea0d0c9b30e5eee185 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:35 +0200
-Subject: [PATCH 1/8] ARM: dts: qcom: ipq8064: add multiple missing pin
- definition
-
-Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
-pins and rgmii2 pins for ipq8064.
-
-Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064
-dtsi.
-
-Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to
-ipq8064 dtsi.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-2-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -----
- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 -------
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++
- 3 files changed, 32 insertions(+), 15 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-@@ -305,15 +305,6 @@
- };
- };
-
-- mdio0_pins: mdio0_pins {
-- mux {
-- pins = "gpio0", "gpio1";
-- function = "gpio";
-- drive-strength = <8>;
-- bias-disable;
-- };
-- };
--
- mdio1_pins: mdio1_pins {
- mux {
- pins = "gpio10", "gpio11";
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -382,6 +382,13 @@
- };
- };
-
-+ i2c4_pins: i2c4-default {
-+ pins = "gpio12", "gpio13";
-+ function = "gsbi4";
-+ drive-strength = <12>;
-+ bias-disable;
-+ };
-+
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
-@@ -424,6 +431,8 @@
-
- pullups {
- pins = "gpio39";
-+ function = "nand";
-+ drive-strength = <10>;
- bias-pull-up;
- };
-
-@@ -431,9 +440,32 @@
- pins = "gpio40", "gpio41", "gpio42",
- "gpio43", "gpio44", "gpio45",
- "gpio46", "gpio47";
-+ function = "nand";
-+ drive-strength = <10>;
- bias-bus-hold;
- };
- };
-+
-+ mdio0_pins: mdio0-pins {
-+ mux {
-+ pins = "gpio0", "gpio1";
-+ function = "mdio";
-+ drive-strength = <8>;
-+ bias-disable;
-+ };
-+ };
-+
-+ rgmii2_pins: rgmii2-pins {
-+ mux {
-+ pins = "gpio27", "gpio28", "gpio29",
-+ "gpio30", "gpio31", "gpio32",
-+ "gpio51", "gpio52", "gpio59",
-+ "gpio60", "gpio61", "gpio62";
-+ function = "rgmii2";
-+ drive-strength = <8>;
-+ bias-disable;
-+ };
-+ };
- };
-
- intc: interrupt-controller@2000000 {
+++ /dev/null
-From d883a12a547b6d42e795ff3b5ac87cfd013b5423 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:36 +0200
-Subject: [PATCH 2/8] ARM: dts: qcom: ipq8064: add gsbi6 missing definition
-
-Add gsbi6 missing definition for ipq8064.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-3-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -663,6 +663,49 @@
- };
- };
-
-+ gsbi6: gsbi@16500000 {
-+ compatible = "qcom,gsbi-v1.0.0";
-+ reg = <0x16500000 0x100>;
-+ cell-index = <6>;
-+ clocks = <&gcc GSBI6_H_CLK>;
-+ clock-names = "iface";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ syscon-tcsr = <&tcsr>;
-+
-+ status = "disabled";
-+
-+ gsbi6_i2c: i2c@16580000 {
-+ compatible = "qcom,i2c-qup-v1.1.1";
-+ reg = <0x16580000 0x1000>;
-+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
-+ clock-names = "core", "iface";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
-+ };
-+
-+ gsbi6_spi: spi@16580000 {
-+ compatible = "qcom,spi-qup-v1.1.1";
-+ reg = <0x16580000 0x1000>;
-+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
-+ clock-names = "core", "iface";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
-+ };
-+ };
-+
- gsbi7: gsbi@16600000 {
- status = "disabled";
- compatible = "qcom,gsbi-v1.0.0";
+++ /dev/null
-From 5c47a46d5e942ea6b041c8b7727b201817c1ff76 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:37 +0200
-Subject: [PATCH 3/8] ARM: dts: qcom: ipq8064: add specific dtsi with smb208
- rpm regulators
-
-Add specific ipq8064 dtsi with smb208 rpm regulators.
-
-Qcom advise to use this configuration but it's not mandatory and OEM
-can decide to implement their own regulators.
-smb208 regulators are used to scale CPU voltage, L2 cache voltage and
-Ubi32 cores.
-
-There regulators are controlled by rpm and to correctly works gsbi4-i2c
-require to be NEVER disabled or rpm will reject any regulator change
-request.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
- create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include "qcom-ipq8064.dtsi"
-+
-+&rpm {
-+ smb208_regulators: regulators {
-+ compatible = "qcom,rpm-smb208-regulators";
-+
-+ smb208_s1a: s1a {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s1b: s1b {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2a: s2a {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2b: s2b {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+ };
-+};
+++ /dev/null
-From 0ce34e0c13e99c239cce6099f64b0e95697f36b1 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:38 +0200
-Subject: [PATCH 4/8] ARM: dts: qcom: ipq8064: add missing snps,dwmac
- compatible for gmac
-
-Add missing snps,dwmac compatible for gmac ipq8064 dtsi.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-5-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1042,7 +1042,7 @@
-
- gmac0: ethernet@37000000 {
- device_type = "network";
-- compatible = "qcom,ipq806x-gmac";
-+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
- reg = <0x37000000 0x200000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
-@@ -1066,7 +1066,7 @@
-
- gmac1: ethernet@37200000 {
- device_type = "network";
-- compatible = "qcom,ipq806x-gmac";
-+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
- reg = <0x37200000 0x200000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
-@@ -1090,7 +1090,7 @@
-
- gmac2: ethernet@37400000 {
- device_type = "network";
-- compatible = "qcom,ipq806x-gmac";
-+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
- reg = <0x37400000 0x200000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
-@@ -1114,7 +1114,7 @@
-
- gmac3: ethernet@37600000 {
- device_type = "network";
-- compatible = "qcom,ipq806x-gmac";
-+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
- reg = <0x37600000 0x200000>;
- interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+++ /dev/null
-From d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:39 +0200
-Subject: [PATCH 5/8] ARM: dts: qcom: ipq8064: disable usb phy by default
-
-Disable usb phy by default. When the usb phy were pushed, half of them
-were flagged as disabled by mistake.
-Correctly disable all usb phy and enable them only if a device actually
-use them.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-6-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1188,6 +1188,8 @@
- clocks = <&gcc USB30_1_UTMI_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-+
-+ status = "disabled";
- };
-
- ss_phy_1: phy@110f8830 {
-@@ -1196,6 +1198,8 @@
- clocks = <&gcc USB30_1_MASTER_CLK>;
- clock-names = "ref";
- #phy-cells = <0>;
-+
-+ status = "disabled";
- };
-
- usb3_1: usb3@110f8800 {
+++ /dev/null
-From 6c421a9c08286389bb331fe783e2625c9efcc187 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:41 +0200
-Subject: [PATCH 7/8] ARM: dts: qcom: ipq8064: fix and add some missing gsbi
- node
-
-Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
-gsbi7 i2c node and gsbi1 node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-8-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++-
- 1 file changed, 53 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -539,6 +539,44 @@
- regulator;
- };
-
-+ gsbi1: gsbi@12440000 {
-+ compatible = "qcom,gsbi-v1.0.0";
-+ reg = <0x12440000 0x100>;
-+ cell-index = <1>;
-+ clocks = <&gcc GSBI1_H_CLK>;
-+ clock-names = "iface";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ syscon-tcsr = <&tcsr>;
-+
-+ status = "disabled";
-+
-+ gsbi1_serial: serial@12450000 {
-+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-+ reg = <0x12450000 0x100>,
-+ <0x12400000 0x03>;
-+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+
-+ status = "disabled";
-+ };
-+
-+ gsbi1_i2c: i2c@12460000 {
-+ compatible = "qcom,i2c-qup-v1.1.1";
-+ reg = <0x12460000 0x1000>;
-+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
-+ };
-+ };
-+
- gsbi2: gsbi@12480000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <2>;
-@@ -562,7 +600,7 @@
- status = "disabled";
- };
-
-- i2c@124a0000 {
-+ gsbi2_i2c: i2c@124a0000 {
- compatible = "qcom,i2c-qup-v1.1.1";
- reg = <0x124a0000 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
-@@ -727,6 +765,20 @@
- clock-names = "core", "iface";
- status = "disabled";
- };
-+
-+ gsbi7_i2c: i2c@16680000 {
-+ compatible = "qcom,i2c-qup-v1.1.1";
-+ reg = <0x16680000 0x1000>;
-+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
-+
-+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
-+ clock-names = "core", "iface";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "disabled";
-+ };
- };
-
- rng@1a500000 {
+++ /dev/null
-From 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 03:09:43 +0200
-Subject: [PATCH 8/8] ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node
-
-Add speedbin efuse nvmem cell needed for the opp table for the CPU
-freqs.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707010943.20857-10-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -854,6 +854,9 @@
- reg = <0x00700000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+ speedbin_efuse: speedbin@c0 {
-+ reg = <0xc0 0x4>;
-+ };
- tsens_calib: calib@400 {
- reg = <0x400 0xb>;
- };
+++ /dev/null
-From cdab30b44518513003607ecfc8a22de3dbbb78ed Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 12:20:38 +0200
-Subject: [PATCH 1/1] hwspinlock: qcom: Add support for mmio usage to
- sfpb-mutex
-
-Allow sfpb-mutex to use mmio in addition to syscon.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707102040.1859-1-ansuelsmth@gmail.com
----
- drivers/hwspinlock/qcom_hwspinlock.c | 28 +++++++++++++++++++++++-----
- 1 file changed, 23 insertions(+), 5 deletions(-)
-
---- a/drivers/hwspinlock/qcom_hwspinlock.c
-+++ b/drivers/hwspinlock/qcom_hwspinlock.c
-@@ -19,6 +19,11 @@
- #define QCOM_MUTEX_APPS_PROC_ID 1
- #define QCOM_MUTEX_NUM_LOCKS 32
-
-+struct qcom_hwspinlock_of_data {
-+ u32 offset;
-+ u32 stride;
-+};
-+
- static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
- {
- struct regmap_field *field = lock->priv;
-@@ -63,9 +68,20 @@ static const struct hwspinlock_ops qcom_
- .unlock = qcom_hwspinlock_unlock,
- };
-
-+static const struct qcom_hwspinlock_of_data of_sfpb_mutex = {
-+ .offset = 0x4,
-+ .stride = 0x4,
-+};
-+
-+/* All modern platform has offset 0 and stride of 4k */
-+static const struct qcom_hwspinlock_of_data of_tcsr_mutex = {
-+ .offset = 0,
-+ .stride = 0x1000,
-+};
-+
- static const struct of_device_id qcom_hwspinlock_of_match[] = {
-- { .compatible = "qcom,sfpb-mutex" },
-- { .compatible = "qcom,tcsr-mutex" },
-+ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
-+ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
- { }
- };
- MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
-@@ -112,12 +128,14 @@ static const struct regmap_config tcsr_m
- static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
- u32 *offset, u32 *stride)
- {
-+ const struct qcom_hwspinlock_of_data *data;
- struct device *dev = &pdev->dev;
- void __iomem *base;
-
-- /* All modern platform has offset 0 and stride of 4k */
-- *offset = 0;
-- *stride = 0x1000;
-+ data = of_device_get_match_data(dev);
-+
-+ *offset = data->offset;
-+ *stride = data->stride;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base))
+++ /dev/null
-From fbe4be367b2169602f6a5949a20d2917b25714d4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 12:20:39 +0200
-Subject: [PATCH 1/2] ARM: dts: qcom: ipq8064: add missing hwlock
-
-Add missing hwlock for ipq8064 dtsi provided by qcom,sfpb-mutex.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-[bjorn: Moved the node inside /soc]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707102040.1859-2-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1357,5 +1357,12 @@
- dma-names = "tx", "rx";
- };
- };
-+
-+ sfpb_mutex: hwlock@1200600 {
-+ compatible = "qcom,sfpb-mutex";
-+ reg = <0x01200600 0x100>;
-+
-+ #hwlock-cells = <1>;
-+ };
- };
- };
+++ /dev/null
-From 4fefb5434c4b735daf913abaef12431405368031 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 12:20:40 +0200
-Subject: [PATCH 2/2] ARM: dts: qcom: ipq8064: add missing smem compatible
-
-Add missing smem compatible and hwlocks phandle for ipq8064 dtsi
-smem node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707102040.1859-3-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -292,8 +292,11 @@
- };
-
- smem: smem@41000000 {
-+ compatible = "qcom,smem";
- reg = <0x41000000 0x200000>;
- no-map;
-+
-+ hwlocks = <&sfpb_mutex 3>;
- };
- };
-
+++ /dev/null
-From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 18 Jul 2022 18:05:16 +0200
-Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant
-
-Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for
-some additional pcie, sata and usb configuration values, additional
-reserved memory and serial output.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++
- arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++
- 2 files changed, 106 insertions(+)
- create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
- create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
-
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include "qcom-ipq8064-v2.0.dtsi"
-+
-+&rpm {
-+ smb208_regulators: regulators {
-+ compatible = "qcom,rpm-smb208-regulators";
-+
-+ smb208_s1a: s1a {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s1b: s1b {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2a: s2a {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2b: s2b {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1250000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
-@@ -0,0 +1,69 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include "qcom-ipq8064.dtsi"
-+
-+/ {
-+ model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
-+
-+ aliases {
-+ serial0 = &gsbi4_serial;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ reserved-memory {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ rsvd@41200000 {
-+ reg = <0x41200000 0x300000>;
-+ no-map;
-+ };
-+ };
-+};
-+
-+&gsbi4 {
-+ qcom,mode = <GSBI_PROT_I2C_UART>;
-+ status = "okay";
-+
-+ serial@16340000 {
-+ status = "okay";
-+ };
-+ /*
-+ * The i2c device on gsbi4 should not be enabled.
-+ * On ipq806x designs gsbi4 i2c is meant for exclusive
-+ * RPM usage. Turning this on in kernel manifests as
-+ * i2c failure for the RPM.
-+ */
-+};
-+
-+&pcie0 {
-+ compatible = "qcom,pcie-ipq8064-v2";
-+};
-+
-+&pcie1 {
-+ compatible = "qcom,pcie-ipq8064-v2";
-+};
-+
-+&pcie2 {
-+ compatible = "qcom,pcie-ipq8064-v2";
-+};
-+
-+&sata {
-+ ports-implemented = <0x1>;
-+};
-+
-+&ss_phy_0 {
-+ qcom,rx-eq = <2>;
-+ qcom,tx-deamp_3_5db = <32>;
-+ qcom,mpll = <5>;
-+};
-+
-+&ss_phy_1 {
-+ qcom,rx-eq = <2>;
-+ qcom,tx-deamp_3_5db = <32>;
-+ qcom,mpll = <5>;
-+};
+++ /dev/null
-From 41d9fa8de7845bd92d9c963196fdfd7ea9232bb2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 18 Jul 2022 18:07:26 +0200
-Subject: [PATCH 2/3] ARM: dts: qcom: ipq8064: add ipq8062 variant
-
-ipq8062 SoC is based on ipq8064-v2.0 with lower supported freq, lack of
-usb port and a reduced voltage output with the smb208 regulators.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi | 37 ++++++++++++++++++++++
- arch/arm/boot/dts/qcom-ipq8062.dtsi | 8 +++++
- 2 files changed, 45 insertions(+)
- create mode 100644 arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
- create mode 100644 arch/arm/boot/dts/qcom-ipq8062.dtsi
-
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include "qcom-ipq8062.dtsi"
-+
-+&rpm {
-+ smb208_regulators: regulators {
-+ compatible = "qcom,rpm-smb208-regulators";
-+
-+ smb208_s1a: s1a {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s1b: s1b {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2a: s2a {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2b: s2b {
-+ regulator-min-microvolt = < 800000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
-@@ -0,0 +1,8 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include "qcom-ipq8064-v2.0.dtsi"
-+
-+/ {
-+ model = "Qualcomm Technologies, Inc. IPQ8062";
-+ compatible = "qcom,ipq8062", "qcom,ipq8064";
-+};
+++ /dev/null
-From 01e7aa3fe6f76f7960f2382038136235eee9c6cd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 18 Jul 2022 18:09:35 +0200
-Subject: [PATCH 3/3] ARM: dts: qcom: ipq8064: add ipq8065 variant
-
-ipq8065 SoC is based on ipq8064-v2.0 with a more clocked CPU and
-an increased voltage output with the smb208 regulators.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi | 37 ++++++++++++++++++++++
- arch/arm/boot/dts/qcom-ipq8065.dtsi | 8 +++++
- 2 files changed, 45 insertions(+)
- create mode 100644 arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
- create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
-
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include "qcom-ipq8065.dtsi"
-+
-+&rpm {
-+ smb208_regulators: regulators {
-+ compatible = "qcom,rpm-smb208-regulators";
-+
-+ smb208_s1a: s1a {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s1b: s1b {
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1150000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2a: s2a {
-+ regulator-min-microvolt = <775000>;
-+ regulator-max-microvolt = <1275000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+
-+ smb208_s2b: s2b {
-+ regulator-min-microvolt = <775000>;
-+ regulator-max-microvolt = <1275000>;
-+
-+ qcom,switch-mode-frequency = <1200000>;
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
-@@ -0,0 +1,8 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include "qcom-ipq8064-v2.0.dtsi"
-+
-+/ {
-+ model = "Qualcomm Technologies, Inc. IPQ8065";
-+ compatible = "qcom,ipq8065", "qcom,ipq8064";
-+};
+++ /dev/null
-From fc7dc1d0c10e8e3d72b68ddae8a61c8aa02a62c1 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 17:13:32 +0200
-Subject: [PATCH v4 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc
-
-Add pcm reset define for ipq806x lcc.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Acked-by: Rob Herring <robh@kernel.org>
----
-v3:
- - Added review tag
- - Added ack tag
-v2:
- - Fix Sob tag
-
- include/dt-bindings/clock/qcom,lcc-ipq806x.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h
-+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
-@@ -19,4 +19,6 @@
- #define SPDIF_CLK 10
- #define AHBIX_CLK 11
-
-+#define LCC_PCM_RESET 0
-+
- #endif
+++ /dev/null
-From 3587d768bdf4683a53244be1acca5d095044671f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 17:19:55 +0200
-Subject: [PATCH v4 2/3] clk: qcom: lcc-ipq806x: add reset definition
-
-Add reset definition for lcc-ipq806x.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
----
-v3:
- - Added review tag
-v2:
- - Fix Sob tag
-
- drivers/clk/qcom/lcc-ipq806x.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/clk/qcom/lcc-ipq806x.c
-+++ b/drivers/clk/qcom/lcc-ipq806x.c
-@@ -22,6 +22,7 @@
- #include "clk-branch.h"
- #include "clk-regmap-divider.h"
- #include "clk-regmap-mux.h"
-+#include "reset.h"
-
- static struct clk_pll pll4 = {
- .l_reg = 0x4,
-@@ -405,6 +406,10 @@ static struct clk_regmap *lcc_ipq806x_cl
- [AHBIX_CLK] = &ahbix_clk.clkr,
- };
-
-+static const struct qcom_reset_map lcc_ipq806x_resets[] = {
-+ [LCC_PCM_RESET] = { 0x54, 13 },
-+};
-+
- static const struct regmap_config lcc_ipq806x_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
-@@ -417,6 +422,8 @@ static const struct qcom_cc_desc lcc_ipq
- .config = &lcc_ipq806x_regmap_config,
- .clks = lcc_ipq806x_clks,
- .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
-+ .resets = lcc_ipq806x_resets,
-+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
- };
-
- static const struct of_device_id lcc_ipq806x_match_table[] = {
+++ /dev/null
-From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 17:35:13 +0200
-Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data
-
-Convert lcc-ipq806x driver to parent_data API.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
-v5:
-- Fix the same compilation error (don't know what the hell happen
- to my buildroot)
-v4:
-- Fix compilation error
-v3:
- - Inline pxo pll4 parent
- - Change .name from pxo to pxo_board
-
- drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++----------------
- 1 file changed, 42 insertions(+), 35 deletions(-)
-
---- a/drivers/clk/qcom/lcc-ipq806x.c
-+++ b/drivers/clk/qcom/lcc-ipq806x.c
-@@ -34,7 +34,9 @@ static struct clk_pll pll4 = {
- .status_bit = 16,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pll4",
-- .parent_names = (const char *[]){ "pxo" },
-+ .parent_data = &(const struct clk_parent_data) {
-+ .fw_name = "pxo", .name = "pxo_board",
-+ },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p
- { P_PLL4, 2 }
- };
-
--static const char * const lcc_pxo_pll4[] = {
-- "pxo",
-- "pll4_vote",
-+static const struct clk_parent_data lcc_pxo_pll4[] = {
-+ { .fw_name = "pxo", .name = "pxo" },
-+ { .fw_name = "pll4_vote", .name = "pll4_vote" },
- };
-
- static struct freq_tbl clk_tbl_aif_mi2s[] = {
-@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_src",
-- .parent_names = lcc_pxo_pll4,
-- .num_parents = 2,
-+ .parent_data = lcc_pxo_pll4,
-+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
- };
-
--static const char * const lcc_mi2s_parents[] = {
-- "mi2s_osr_src",
--};
--
- static struct clk_branch mi2s_osr_clk = {
- .halt_reg = 0x50,
- .halt_bit = 1,
-@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk =
- .enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_osr_clk",
-- .parent_names = lcc_mi2s_parents,
-+ .parent_hws = (const struct clk_hw*[]){
-+ &mi2s_osr_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_div_clk",
-- .parent_names = lcc_mi2s_parents,
-+ .parent_hws = (const struct clk_hw*[]){
-+ &mi2s_osr_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- },
-@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl
- .enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_div_clk",
-- .parent_names = (const char *[]){ "mi2s_div_clk" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &mi2s_div_clk.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl
- },
- };
-
-+static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
-+ { .hw = &mi2s_bit_div_clk.clkr.hw, },
-+ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" },
-+};
-
- static struct clk_regmap_mux mi2s_bit_clk = {
- .reg = 0x48,
-@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "mi2s_bit_clk",
-- .parent_names = (const char *[]){
-- "mi2s_bit_div_clk",
-- "mi2s_codec_clk",
-- },
-- .num_parents = 2,
-+ .parent_data = lcc_mi2s_bit_div_codec_clk,
-+ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "pcm_src",
-- .parent_names = lcc_pxo_pll4,
-- .num_parents = 2,
-+ .parent_data = lcc_pxo_pll4,
-+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
-@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "pcm_clk_out",
-- .parent_names = (const char *[]){ "pcm_src" },
-+ .parent_hws = (const struct clk_hw*[]){
-+ &pcm_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = {
- },
- };
-
-+static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
-+ { .hw = &pcm_clk_out.clkr.hw, },
-+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
-+};
-+
- static struct clk_regmap_mux pcm_clk = {
- .reg = 0x54,
- .shift = 10,
-@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = {
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcm_clk",
-- .parent_names = (const char *[]){
-- "pcm_clk_out",
-- "pcm_codec_clk",
-- },
-- .num_parents = 2,
-+ .parent_data = lcc_pcm_clk_out_codec_clk,
-+ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = {
- .enable_mask = BIT(9),
- .hw.init = &(struct clk_init_data){
- .name = "spdif_src",
-- .parent_names = lcc_pxo_pll4,
-- .num_parents = 2,
-+ .parent_data = lcc_pxo_pll4,
-+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
- .ops = &clk_rcg_ops,
- .flags = CLK_SET_RATE_GATE,
- },
- },
- };
-
--static const char * const lcc_spdif_parents[] = {
-- "spdif_src",
--};
--
- static struct clk_branch spdif_clk = {
- .halt_reg = 0xd4,
- .halt_bit = 1,
-@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = {
- .enable_mask = BIT(12),
- .hw.init = &(struct clk_init_data){
- .name = "spdif_clk",
-- .parent_names = lcc_spdif_parents,
-+ .parent_hws = (const struct clk_hw*[]){
-+ &spdif_src.clkr.hw,
-+ },
- .num_parents = 1,
- .ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = {
- .enable_mask = BIT(11),
- .hw.init = &(struct clk_init_data){
- .name = "ahbix",
-- .parent_names = lcc_pxo_pll4,
-- .num_parents = 2,
-+ .parent_data = lcc_pxo_pll4,
-+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
- .ops = &clk_rcg_lcc_ops,
- },
- },
+++ /dev/null
-From 713472e53e6e53c985e283782b0fd76b8ecfd47e Mon Sep 17 00:00:00 2001
-From: Chanwoo Choi <cw00.choi@samsung.com>
-Date: Mon, 1 Mar 2021 02:07:29 +0900
-Subject: [PATCH 1/5] PM / devfreq: Export devfreq_get_freq_range symbol within
- devfreq
-
-In order to get frequency range within devfreq governors,
-export devfreq_get_freq_range symbol within devfreq.
-
-Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Johnson Wang <johnson.wang@mediatek.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/devfreq.c | 20 ++++++++++++--------
- drivers/devfreq/governor.h | 2 ++
- 2 files changed, 14 insertions(+), 8 deletions(-)
-
---- a/drivers/devfreq/devfreq.c
-+++ b/drivers/devfreq/devfreq.c
-@@ -112,16 +112,16 @@ static unsigned long find_available_max_
- }
-
- /**
-- * get_freq_range() - Get the current freq range
-+ * devfreq_get_freq_range() - Get the current freq range
- * @devfreq: the devfreq instance
- * @min_freq: the min frequency
- * @max_freq: the max frequency
- *
- * This takes into consideration all constraints.
- */
--static void get_freq_range(struct devfreq *devfreq,
-- unsigned long *min_freq,
-- unsigned long *max_freq)
-+void devfreq_get_freq_range(struct devfreq *devfreq,
-+ unsigned long *min_freq,
-+ unsigned long *max_freq)
- {
- unsigned long *freq_table = devfreq->profile->freq_table;
- s32 qos_min_freq, qos_max_freq;
-@@ -158,6 +158,7 @@ static void get_freq_range(struct devfre
- if (*min_freq > *max_freq)
- *min_freq = *max_freq;
- }
-+EXPORT_SYMBOL(devfreq_get_freq_range);
-
- /**
- * devfreq_get_freq_level() - Lookup freq_table for the frequency
-@@ -418,7 +419,7 @@ int devfreq_update_target(struct devfreq
- err = devfreq->governor->get_target_freq(devfreq, &freq);
- if (err)
- return err;
-- get_freq_range(devfreq, &min_freq, &max_freq);
-+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq);
-
- if (freq < min_freq) {
- freq = min_freq;
-@@ -784,6 +785,7 @@ struct devfreq *devfreq_add_device(struc
- {
- struct devfreq *devfreq;
- struct devfreq_governor *governor;
-+ unsigned long min_freq, max_freq;
- int err = 0;
-
- if (!dev || !profile || !governor_name) {
-@@ -848,6 +850,8 @@ struct devfreq *devfreq_add_device(struc
- goto err_dev;
- }
-
-+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq);
-+
- devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev);
- devfreq->opp_table = dev_pm_opp_get_opp_table(dev);
- if (IS_ERR(devfreq->opp_table))
-@@ -1559,7 +1563,7 @@ static ssize_t min_freq_show(struct devi
- unsigned long min_freq, max_freq;
-
- mutex_lock(&df->lock);
-- get_freq_range(df, &min_freq, &max_freq);
-+ devfreq_get_freq_range(df, &min_freq, &max_freq);
- mutex_unlock(&df->lock);
-
- return sprintf(buf, "%lu\n", min_freq);
-@@ -1613,7 +1617,7 @@ static ssize_t max_freq_show(struct devi
- unsigned long min_freq, max_freq;
-
- mutex_lock(&df->lock);
-- get_freq_range(df, &min_freq, &max_freq);
-+ devfreq_get_freq_range(df, &min_freq, &max_freq);
- mutex_unlock(&df->lock);
-
- return sprintf(buf, "%lu\n", max_freq);
-@@ -1927,7 +1931,7 @@ static int devfreq_summary_show(struct s
-
- mutex_lock(&devfreq->lock);
- cur_freq = devfreq->previous_freq;
-- get_freq_range(devfreq, &min_freq, &max_freq);
-+ devfreq_get_freq_range(devfreq, &min_freq, &max_freq);
- timer = devfreq->profile->timer;
-
- if (IS_SUPPORTED_ATTR(devfreq->governor->attrs, POLLING_INTERVAL))
---- a/drivers/devfreq/governor.h
-+++ b/drivers/devfreq/governor.h
-@@ -86,6 +86,8 @@ int devfreq_remove_governor(struct devfr
-
- int devfreq_update_status(struct devfreq *devfreq, unsigned long freq);
- int devfreq_update_target(struct devfreq *devfreq, unsigned long freq);
-+void devfreq_get_freq_range(struct devfreq *devfreq, unsigned long *min_freq,
-+ unsigned long *max_freq);
-
- static inline int devfreq_update_stats(struct devfreq *df)
- {
+++ /dev/null
-From a03dacb0316f74400846aaf144d6c73f4217ca08 Mon Sep 17 00:00:00 2001
-From: Saravana Kannan <skannan@codeaurora.org>
-Date: Tue, 2 Mar 2021 15:58:21 +0900
-Subject: [PATCH 2/5] PM / devfreq: Add cpu based scaling support to passive
- governor
-
-Many CPU architectures have caches that can scale independent of the
-CPUs. Frequency scaling of the caches is necessary to make sure that the
-cache is not a performance bottleneck that leads to poor performance and
-power. The same idea applies for RAM/DDR.
-
-To achieve this, this patch adds support for cpu based scaling to the
-passive governor. This is accomplished by taking the current frequency
-of each CPU frequency domain and then adjust the frequency of the cache
-(or any devfreq device) based on the frequency of the CPUs. It listens
-to CPU frequency transition notifiers to keep itself up to date on the
-current CPU frequency.
-
-To decide the frequency of the device, the governor does one of the
-following:
-* Derives the optimal devfreq device opp from required-opps property of
- the parent cpu opp_table.
-
-* Scales the device frequency in proportion to the CPU frequency. So, if
- the CPUs are running at their max frequency, the device runs at its
- max frequency. If the CPUs are running at their min frequency, the
- device runs at its min frequency. It is interpolated for frequencies
- in between.
-
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Johnson Wang <johnson.wang@mediatek.com>
-Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
-[Sibi: Integrated cpu-freqmap governor into passive_governor]
-Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
-[Chanwoo: Fix conflict with latest code and cleanup code]
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/governor.h | 22 +++
- drivers/devfreq/governor_passive.c | 298 +++++++++++++++++++++++++++--
- include/linux/devfreq.h | 17 +-
- 3 files changed, 323 insertions(+), 14 deletions(-)
-
---- a/drivers/devfreq/governor.h
-+++ b/drivers/devfreq/governor.h
-@@ -48,6 +48,28 @@
- #define DEVFREQ_GOV_ATTR_TIMER BIT(1)
-
- /**
-+ * struct devfreq_cpu_data - Hold the per-cpu data
-+ * @dev: reference to cpu device.
-+ * @first_cpu: the cpumask of the first cpu of a policy.
-+ * @opp_table: reference to cpu opp table.
-+ * @cur_freq: the current frequency of the cpu.
-+ * @min_freq: the min frequency of the cpu.
-+ * @max_freq: the max frequency of the cpu.
-+ *
-+ * This structure stores the required cpu_data of a cpu.
-+ * This is auto-populated by the governor.
-+ */
-+struct devfreq_cpu_data {
-+ struct device *dev;
-+ unsigned int first_cpu;
-+
-+ struct opp_table *opp_table;
-+ unsigned int cur_freq;
-+ unsigned int min_freq;
-+ unsigned int max_freq;
-+};
-+
-+/**
- * struct devfreq_governor - Devfreq policy governor
- * @node: list node - contains registered devfreq governors
- * @name: Governor's name
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -8,11 +8,85 @@
- */
-
- #include <linux/module.h>
-+#include <linux/cpu.h>
-+#include <linux/cpufreq.h>
-+#include <linux/cpumask.h>
-+#include <linux/slab.h>
- #include <linux/device.h>
- #include <linux/devfreq.h>
- #include "governor.h"
-
--static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
-+#define HZ_PER_KHZ 1000
-+
-+static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
-+ struct opp_table *p_opp_table,
-+ struct opp_table *opp_table,
-+ unsigned long *freq)
-+{
-+ struct dev_pm_opp *opp = NULL, *p_opp = NULL;
-+ unsigned long target_freq;
-+
-+ if (!p_dev || !p_opp_table || !opp_table || !freq)
-+ return 0;
-+
-+ p_opp = devfreq_recommended_opp(p_dev, freq, 0);
-+ if (IS_ERR(p_opp))
-+ return 0;
-+
-+ opp = dev_pm_opp_xlate_required_opp(p_opp_table, opp_table, p_opp);
-+ dev_pm_opp_put(p_opp);
-+
-+ if (IS_ERR(opp))
-+ return 0;
-+
-+ target_freq = dev_pm_opp_get_freq(opp);
-+ dev_pm_opp_put(opp);
-+
-+ return target_freq;
-+}
-+
-+static int get_target_freq_with_cpufreq(struct devfreq *devfreq,
-+ unsigned long *target_freq)
-+{
-+ struct devfreq_passive_data *p_data =
-+ (struct devfreq_passive_data *)devfreq->data;
-+ struct devfreq_cpu_data *parent_cpu_data;
-+ unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
-+ unsigned long dev_min, dev_max;
-+ unsigned long freq = 0;
-+
-+ for_each_online_cpu(cpu) {
-+ parent_cpu_data = p_data->parent_cpu_data[cpu];
-+ if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
-+ continue;
-+
-+ /* Get target freq via required opps */
-+ cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
-+ freq = get_target_freq_by_required_opp(parent_cpu_data->dev,
-+ parent_cpu_data->opp_table,
-+ devfreq->opp_table, &cpu_cur);
-+ if (freq) {
-+ *target_freq = max(freq, *target_freq);
-+ continue;
-+ }
-+
-+ /* Use interpolation if required opps is not available */
-+ devfreq_get_freq_range(devfreq, &dev_min, &dev_max);
-+
-+ cpu_min = parent_cpu_data->min_freq;
-+ cpu_max = parent_cpu_data->max_freq;
-+ cpu_cur = parent_cpu_data->cur_freq;
-+
-+ cpu_percent = ((cpu_cur - cpu_min) * 100) / (cpu_max - cpu_min);
-+ freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
-+
-+ *target_freq = max(freq, *target_freq);
-+ }
-+
-+ return 0;
-+}
-+
-+static int get_target_freq_with_devfreq(struct devfreq *devfreq,
- unsigned long *freq)
- {
- struct devfreq_passive_data *p_data
-@@ -99,6 +173,181 @@ no_required_opp:
- return 0;
- }
-
-+static int devfreq_passive_get_target_freq(struct devfreq *devfreq,
-+ unsigned long *freq)
-+{
-+ struct devfreq_passive_data *p_data =
-+ (struct devfreq_passive_data *)devfreq->data;
-+ int ret;
-+
-+ if (!p_data)
-+ return -EINVAL;
-+
-+ /*
-+ * If the devfreq device with passive governor has the specific method
-+ * to determine the next frequency, should use the get_target_freq()
-+ * of struct devfreq_passive_data.
-+ */
-+ if (p_data->get_target_freq)
-+ return p_data->get_target_freq(devfreq, freq);
-+
-+ switch (p_data->parent_type) {
-+ case DEVFREQ_PARENT_DEV:
-+ ret = get_target_freq_with_devfreq(devfreq, freq);
-+ break;
-+ case CPUFREQ_PARENT_DEV:
-+ ret = get_target_freq_with_cpufreq(devfreq, freq);
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ dev_err(&devfreq->dev, "Invalid parent type\n");
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+static int cpufreq_passive_notifier_call(struct notifier_block *nb,
-+ unsigned long event, void *ptr)
-+{
-+ struct devfreq_passive_data *p_data =
-+ container_of(nb, struct devfreq_passive_data, nb);
-+ struct devfreq *devfreq = (struct devfreq *)p_data->this;
-+ struct devfreq_cpu_data *parent_cpu_data;
-+ struct cpufreq_freqs *freqs = ptr;
-+ unsigned int cur_freq;
-+ int ret;
-+
-+ if (event != CPUFREQ_POSTCHANGE || !freqs ||
-+ !p_data->parent_cpu_data[freqs->policy->cpu])
-+ return 0;
-+
-+ parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
-+ if (parent_cpu_data->cur_freq == freqs->new)
-+ return 0;
-+
-+ cur_freq = parent_cpu_data->cur_freq;
-+ parent_cpu_data->cur_freq = freqs->new;
-+
-+ mutex_lock(&devfreq->lock);
-+ ret = devfreq_update_target(devfreq, freqs->new);
-+ mutex_unlock(&devfreq->lock);
-+ if (ret) {
-+ parent_cpu_data->cur_freq = cur_freq;
-+ dev_err(&devfreq->dev, "failed to update the frequency.\n");
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int cpufreq_passive_unregister_notifier(struct devfreq *devfreq)
-+{
-+ struct devfreq_passive_data *p_data
-+ = (struct devfreq_passive_data *)devfreq->data;
-+ struct devfreq_cpu_data *parent_cpu_data;
-+ int cpu, ret;
-+
-+ if (p_data->nb.notifier_call) {
-+ ret = cpufreq_unregister_notifier(&p_data->nb,
-+ CPUFREQ_TRANSITION_NOTIFIER);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ for_each_possible_cpu(cpu) {
-+ parent_cpu_data = p_data->parent_cpu_data[cpu];
-+ if (!parent_cpu_data)
-+ continue;
-+
-+ if (parent_cpu_data->opp_table)
-+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
-+ kfree(parent_cpu_data);
-+ }
-+
-+ return 0;
-+}
-+
-+static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
-+{
-+ struct devfreq_passive_data *p_data
-+ = (struct devfreq_passive_data *)devfreq->data;
-+ struct device *dev = devfreq->dev.parent;
-+ struct opp_table *opp_table = NULL;
-+ struct devfreq_cpu_data *parent_cpu_data;
-+ struct cpufreq_policy *policy;
-+ struct device *cpu_dev;
-+ unsigned int cpu;
-+ int ret;
-+
-+ p_data->nb.notifier_call = cpufreq_passive_notifier_call;
-+ ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
-+ if (ret) {
-+ dev_err(dev, "failed to register cpufreq notifier\n");
-+ p_data->nb.notifier_call = NULL;
-+ goto err;
-+ }
-+
-+ for_each_possible_cpu(cpu) {
-+ if (p_data->parent_cpu_data[cpu])
-+ continue;
-+
-+ policy = cpufreq_cpu_get(cpu);
-+ if (!policy) {
-+ ret = -EPROBE_DEFER;
-+ goto err;
-+ }
-+
-+ parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
-+ GFP_KERNEL);
-+ if (!parent_cpu_data) {
-+ ret = -ENOMEM;
-+ goto err_put_policy;
-+ }
-+
-+ cpu_dev = get_cpu_device(cpu);
-+ if (!cpu_dev) {
-+ dev_err(dev, "failed to get cpu device\n");
-+ ret = -ENODEV;
-+ goto err_free_cpu_data;
-+ }
-+
-+ opp_table = dev_pm_opp_get_opp_table(cpu_dev);
-+ if (IS_ERR(opp_table)) {
-+ dev_err(dev, "failed to get opp_table of cpu%d\n", cpu);
-+ ret = PTR_ERR(opp_table);
-+ goto err_free_cpu_data;
-+ }
-+
-+ parent_cpu_data->dev = cpu_dev;
-+ parent_cpu_data->opp_table = opp_table;
-+ parent_cpu_data->first_cpu = cpumask_first(policy->related_cpus);
-+ parent_cpu_data->cur_freq = policy->cur;
-+ parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
-+ parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
-+
-+ p_data->parent_cpu_data[cpu] = parent_cpu_data;
-+ cpufreq_cpu_put(policy);
-+ }
-+
-+ mutex_lock(&devfreq->lock);
-+ ret = devfreq_update_target(devfreq, 0L);
-+ mutex_unlock(&devfreq->lock);
-+ if (ret)
-+ dev_err(dev, "failed to update the frequency\n");
-+
-+ return ret;
-+
-+err_free_cpu_data:
-+ kfree(parent_cpu_data);
-+err_put_policy:
-+ cpufreq_cpu_put(policy);
-+err:
-+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
-+
-+ return ret;
-+}
-+
- static int devfreq_passive_notifier_call(struct notifier_block *nb,
- unsigned long event, void *ptr)
- {
-@@ -131,30 +380,55 @@ static int devfreq_passive_notifier_call
- return NOTIFY_DONE;
- }
-
--static int devfreq_passive_event_handler(struct devfreq *devfreq,
-- unsigned int event, void *data)
-+static int devfreq_passive_unregister_notifier(struct devfreq *devfreq)
-+{
-+ struct devfreq_passive_data *p_data
-+ = (struct devfreq_passive_data *)devfreq->data;
-+ struct devfreq *parent = (struct devfreq *)p_data->parent;
-+ struct notifier_block *nb = &p_data->nb;
-+
-+ return devfreq_unregister_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
-+}
-+
-+static int devfreq_passive_register_notifier(struct devfreq *devfreq)
- {
- struct devfreq_passive_data *p_data
- = (struct devfreq_passive_data *)devfreq->data;
- struct devfreq *parent = (struct devfreq *)p_data->parent;
- struct notifier_block *nb = &p_data->nb;
-- int ret = 0;
-
- if (!parent)
- return -EPROBE_DEFER;
-
-+ nb->notifier_call = devfreq_passive_notifier_call;
-+ return devfreq_register_notifier(parent, nb, DEVFREQ_TRANSITION_NOTIFIER);
-+}
-+
-+static int devfreq_passive_event_handler(struct devfreq *devfreq,
-+ unsigned int event, void *data)
-+{
-+ struct devfreq_passive_data *p_data
-+ = (struct devfreq_passive_data *)devfreq->data;
-+ int ret = -EINVAL;
-+
-+ if (!p_data)
-+ return -EINVAL;
-+
-+ if (!p_data->this)
-+ p_data->this = devfreq;
-+
- switch (event) {
- case DEVFREQ_GOV_START:
-- if (!p_data->this)
-- p_data->this = devfreq;
--
-- nb->notifier_call = devfreq_passive_notifier_call;
-- ret = devfreq_register_notifier(parent, nb,
-- DEVFREQ_TRANSITION_NOTIFIER);
-+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
-+ ret = devfreq_passive_register_notifier(devfreq);
-+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
-+ ret = cpufreq_passive_register_notifier(devfreq);
- break;
- case DEVFREQ_GOV_STOP:
-- WARN_ON(devfreq_unregister_notifier(parent, nb,
-- DEVFREQ_TRANSITION_NOTIFIER));
-+ if (p_data->parent_type == DEVFREQ_PARENT_DEV)
-+ WARN_ON(devfreq_passive_unregister_notifier(devfreq));
-+ else if (p_data->parent_type == CPUFREQ_PARENT_DEV)
-+ WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
- break;
- default:
- break;
---- a/include/linux/devfreq.h
-+++ b/include/linux/devfreq.h
-@@ -38,6 +38,7 @@ enum devfreq_timer {
-
- struct devfreq;
- struct devfreq_governor;
-+struct devfreq_cpu_data;
- struct thermal_cooling_device;
-
- /**
-@@ -289,6 +290,11 @@ struct devfreq_simple_ondemand_data {
- #endif
-
- #if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE)
-+enum devfreq_parent_dev_type {
-+ DEVFREQ_PARENT_DEV,
-+ CPUFREQ_PARENT_DEV,
-+};
-+
- /**
- * struct devfreq_passive_data - ``void *data`` fed to struct devfreq
- * and devfreq_add_device
-@@ -300,8 +306,11 @@ struct devfreq_simple_ondemand_data {
- * using governors except for passive governor.
- * If the devfreq device has the specific method to decide
- * the next frequency, should use this callback.
-- * @this: the devfreq instance of own device.
-- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list
-+ * @parent_type: the parent type of the device.
-+ * @this: the devfreq instance of own device.
-+ * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
-+ * CPUFREQ_TRANSITION_NOTIFIER list.
-+ * @parent_cpu_data: the state min/max/current frequency of all online cpu's.
- *
- * The devfreq_passive_data have to set the devfreq instance of parent
- * device with governors except for the passive governor. But, don't need to
-@@ -315,9 +324,13 @@ struct devfreq_passive_data {
- /* Optional callback to decide the next frequency of passvice device */
- int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
-
-+ /* Should set the type of parent device */
-+ enum devfreq_parent_dev_type parent_type;
-+
- /* For passive governor's internal use. Don't need to set them */
- struct devfreq *this;
- struct notifier_block nb;
-+ struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
- };
- #endif
-
+++ /dev/null
-From 05723e71234b60a1a47313ea1a889797ec648f1c Mon Sep 17 00:00:00 2001
-From: Chanwoo Choi <cw00.choi@samsung.com>
-Date: Tue, 2 Mar 2021 17:22:50 +0900
-Subject: [PATCH 3/5] PM / devfreq: passive: Reduce duplicate code when
- passive_devfreq case
-
-In order to keep the consistent coding style between passive_devfreq
-and passive_cpufreq, use common code for handling required opp property.
-Also remove the unneed conditional statement and unify the comment
-of both passive_devfreq and passive_cpufreq when getting the target frequency.
-
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Johnson Wang <johnson.wang@mediatek.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/governor_passive.c | 66 ++++--------------------------
- 1 file changed, 8 insertions(+), 58 deletions(-)
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -93,65 +93,16 @@ static int get_target_freq_with_devfreq(
- = (struct devfreq_passive_data *)devfreq->data;
- struct devfreq *parent_devfreq = (struct devfreq *)p_data->parent;
- unsigned long child_freq = ULONG_MAX;
-- struct dev_pm_opp *opp, *p_opp;
- int i, count;
-
-- /*
-- * If the devfreq device with passive governor has the specific method
-- * to determine the next frequency, should use the get_target_freq()
-- * of struct devfreq_passive_data.
-- */
-- if (p_data->get_target_freq)
-- return p_data->get_target_freq(devfreq, freq);
--
-- /*
-- * If the parent and passive devfreq device uses the OPP table,
-- * get the next frequency by using the OPP table.
-- */
--
-- /*
-- * - parent devfreq device uses the governors except for passive.
-- * - passive devfreq device uses the passive governor.
-- *
-- * Each devfreq has the OPP table. After deciding the new frequency
-- * from the governor of parent devfreq device, the passive governor
-- * need to get the index of new frequency on OPP table of parent
-- * device. And then the index is used for getting the suitable
-- * new frequency for passive devfreq device.
-- */
-- if (!devfreq->profile || !devfreq->profile->freq_table
-- || devfreq->profile->max_state <= 0)
-- return -EINVAL;
--
-- /*
-- * The passive governor have to get the correct frequency from OPP
-- * list of parent device. Because in this case, *freq is temporary
-- * value which is decided by ondemand governor.
-- */
-- if (devfreq->opp_table && parent_devfreq->opp_table) {
-- p_opp = devfreq_recommended_opp(parent_devfreq->dev.parent,
-- freq, 0);
-- if (IS_ERR(p_opp))
-- return PTR_ERR(p_opp);
--
-- opp = dev_pm_opp_xlate_required_opp(parent_devfreq->opp_table,
-- devfreq->opp_table, p_opp);
-- dev_pm_opp_put(p_opp);
--
-- if (IS_ERR(opp))
-- goto no_required_opp;
--
-- *freq = dev_pm_opp_get_freq(opp);
-- dev_pm_opp_put(opp);
--
-- return 0;
-- }
-+ /* Get target freq via required opps */
-+ child_freq = get_target_freq_by_required_opp(parent_devfreq->dev.parent,
-+ parent_devfreq->opp_table,
-+ devfreq->opp_table, freq);
-+ if (child_freq)
-+ goto out;
-
--no_required_opp:
-- /*
-- * Get the OPP table's index of decided frequency by governor
-- * of parent device.
-- */
-+ /* Use interpolation if required opps is not available */
- for (i = 0; i < parent_devfreq->profile->max_state; i++)
- if (parent_devfreq->profile->freq_table[i] == *freq)
- break;
-@@ -159,7 +110,6 @@ no_required_opp:
- if (i == parent_devfreq->profile->max_state)
- return -EINVAL;
-
-- /* Get the suitable frequency by using index of parent device. */
- if (i < devfreq->profile->max_state) {
- child_freq = devfreq->profile->freq_table[i];
- } else {
-@@ -167,7 +117,7 @@ no_required_opp:
- child_freq = devfreq->profile->freq_table[count - 1];
- }
-
-- /* Return the suitable frequency for passive device. */
-+out:
- *freq = child_freq;
-
- return 0;
+++ /dev/null
-From 26984d9d581e5049bd75091d2e789b9cc3ea12e0 Mon Sep 17 00:00:00 2001
-From: Chanwoo Choi <cw00.choi@samsung.com>
-Date: Wed, 27 Apr 2022 03:49:19 +0900
-Subject: [PATCH 4/5] PM / devfreq: passive: Keep cpufreq_policy for possible
- cpus
-
-The passive governor requires the cpu data to get the next target frequency
-of devfreq device if depending on cpu. In order to reduce the unnecessary
-memory data, keep cpufreq_policy data for possible cpus instead of NR_CPU.
-
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Johnson Wang <johnson.wang@mediatek.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/governor.h | 3 ++
- drivers/devfreq/governor_passive.c | 75 +++++++++++++++++++++++-------
- include/linux/devfreq.h | 4 +-
- 3 files changed, 64 insertions(+), 18 deletions(-)
-
---- a/drivers/devfreq/governor.h
-+++ b/drivers/devfreq/governor.h
-@@ -49,6 +49,7 @@
-
- /**
- * struct devfreq_cpu_data - Hold the per-cpu data
-+ * @node: list node
- * @dev: reference to cpu device.
- * @first_cpu: the cpumask of the first cpu of a policy.
- * @opp_table: reference to cpu opp table.
-@@ -60,6 +61,8 @@
- * This is auto-populated by the governor.
- */
- struct devfreq_cpu_data {
-+ struct list_head node;
-+
- struct device *dev;
- unsigned int first_cpu;
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -1,4 +1,4 @@
--// SPDX-License-Identifier: GPL-2.0-only
-+ // SPDX-License-Identifier: GPL-2.0-only
- /*
- * linux/drivers/devfreq/governor_passive.c
- *
-@@ -18,6 +18,22 @@
-
- #define HZ_PER_KHZ 1000
-
-+static struct devfreq_cpu_data *
-+get_parent_cpu_data(struct devfreq_passive_data *p_data,
-+ struct cpufreq_policy *policy)
-+{
-+ struct devfreq_cpu_data *parent_cpu_data;
-+
-+ if (!p_data || !policy)
-+ return NULL;
-+
-+ list_for_each_entry(parent_cpu_data, &p_data->cpu_data_list, node)
-+ if (parent_cpu_data->first_cpu == cpumask_first(policy->related_cpus))
-+ return parent_cpu_data;
-+
-+ return NULL;
-+}
-+
- static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
- struct opp_table *p_opp_table,
- struct opp_table *opp_table,
-@@ -51,14 +67,24 @@ static int get_target_freq_with_cpufreq(
- struct devfreq_passive_data *p_data =
- (struct devfreq_passive_data *)devfreq->data;
- struct devfreq_cpu_data *parent_cpu_data;
-+ struct cpufreq_policy *policy;
- unsigned long cpu, cpu_cur, cpu_min, cpu_max, cpu_percent;
- unsigned long dev_min, dev_max;
- unsigned long freq = 0;
-+ int ret = 0;
-
- for_each_online_cpu(cpu) {
-- parent_cpu_data = p_data->parent_cpu_data[cpu];
-- if (!parent_cpu_data || parent_cpu_data->first_cpu != cpu)
-+ policy = cpufreq_cpu_get(cpu);
-+ if (!policy) {
-+ ret = -EINVAL;
-+ continue;
-+ }
-+
-+ parent_cpu_data = get_parent_cpu_data(p_data, policy);
-+ if (!parent_cpu_data) {
-+ cpufreq_cpu_put(policy);
- continue;
-+ }
-
- /* Get target freq via required opps */
- cpu_cur = parent_cpu_data->cur_freq * HZ_PER_KHZ;
-@@ -67,6 +93,7 @@ static int get_target_freq_with_cpufreq(
- devfreq->opp_table, &cpu_cur);
- if (freq) {
- *target_freq = max(freq, *target_freq);
-+ cpufreq_cpu_put(policy);
- continue;
- }
-
-@@ -81,9 +108,10 @@ static int get_target_freq_with_cpufreq(
- freq = dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
-
- *target_freq = max(freq, *target_freq);
-+ cpufreq_cpu_put(policy);
- }
-
-- return 0;
-+ return ret;
- }
-
- static int get_target_freq_with_devfreq(struct devfreq *devfreq,
-@@ -168,12 +196,11 @@ static int cpufreq_passive_notifier_call
- unsigned int cur_freq;
- int ret;
-
-- if (event != CPUFREQ_POSTCHANGE || !freqs ||
-- !p_data->parent_cpu_data[freqs->policy->cpu])
-+ if (event != CPUFREQ_POSTCHANGE || !freqs)
- return 0;
-
-- parent_cpu_data = p_data->parent_cpu_data[freqs->policy->cpu];
-- if (parent_cpu_data->cur_freq == freqs->new)
-+ parent_cpu_data = get_parent_cpu_data(p_data, freqs->policy);
-+ if (!parent_cpu_data || parent_cpu_data->cur_freq == freqs->new)
- return 0;
-
- cur_freq = parent_cpu_data->cur_freq;
-@@ -196,7 +223,7 @@ static int cpufreq_passive_unregister_no
- struct devfreq_passive_data *p_data
- = (struct devfreq_passive_data *)devfreq->data;
- struct devfreq_cpu_data *parent_cpu_data;
-- int cpu, ret;
-+ int cpu, ret = 0;
-
- if (p_data->nb.notifier_call) {
- ret = cpufreq_unregister_notifier(&p_data->nb,
-@@ -206,16 +233,26 @@ static int cpufreq_passive_unregister_no
- }
-
- for_each_possible_cpu(cpu) {
-- parent_cpu_data = p_data->parent_cpu_data[cpu];
-- if (!parent_cpu_data)
-+ struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
-+ if (!policy) {
-+ ret = -EINVAL;
-+ continue;
-+ }
-+
-+ parent_cpu_data = get_parent_cpu_data(p_data, policy);
-+ if (!parent_cpu_data) {
-+ cpufreq_cpu_put(policy);
- continue;
-+ }
-
-+ list_del(&parent_cpu_data->node);
- if (parent_cpu_data->opp_table)
- dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
- kfree(parent_cpu_data);
-+ cpufreq_cpu_put(policy);
- }
-
-- return 0;
-+ return ret;
- }
-
- static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
-@@ -230,6 +267,9 @@ static int cpufreq_passive_register_noti
- unsigned int cpu;
- int ret;
-
-+ p_data->cpu_data_list
-+ = (struct list_head)LIST_HEAD_INIT(p_data->cpu_data_list);
-+
- p_data->nb.notifier_call = cpufreq_passive_notifier_call;
- ret = cpufreq_register_notifier(&p_data->nb, CPUFREQ_TRANSITION_NOTIFIER);
- if (ret) {
-@@ -239,15 +279,18 @@ static int cpufreq_passive_register_noti
- }
-
- for_each_possible_cpu(cpu) {
-- if (p_data->parent_cpu_data[cpu])
-- continue;
--
- policy = cpufreq_cpu_get(cpu);
- if (!policy) {
- ret = -EPROBE_DEFER;
- goto err;
- }
-
-+ parent_cpu_data = get_parent_cpu_data(p_data, policy);
-+ if (parent_cpu_data) {
-+ cpufreq_cpu_put(policy);
-+ continue;
-+ }
-+
- parent_cpu_data = kzalloc(sizeof(*parent_cpu_data),
- GFP_KERNEL);
- if (!parent_cpu_data) {
-@@ -276,7 +319,7 @@ static int cpufreq_passive_register_noti
- parent_cpu_data->min_freq = policy->cpuinfo.min_freq;
- parent_cpu_data->max_freq = policy->cpuinfo.max_freq;
-
-- p_data->parent_cpu_data[cpu] = parent_cpu_data;
-+ list_add_tail(&parent_cpu_data->node, &p_data->cpu_data_list);
- cpufreq_cpu_put(policy);
- }
-
---- a/include/linux/devfreq.h
-+++ b/include/linux/devfreq.h
-@@ -310,7 +310,7 @@ enum devfreq_parent_dev_type {
- * @this: the devfreq instance of own device.
- * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER or
- * CPUFREQ_TRANSITION_NOTIFIER list.
-- * @parent_cpu_data: the state min/max/current frequency of all online cpu's.
-+ * @cpu_data_list: the list of cpu frequency data for all cpufreq_policy.
- *
- * The devfreq_passive_data have to set the devfreq instance of parent
- * device with governors except for the passive governor. But, don't need to
-@@ -330,7 +330,7 @@ struct devfreq_passive_data {
- /* For passive governor's internal use. Don't need to set them */
- struct devfreq *this;
- struct notifier_block nb;
-- struct devfreq_cpu_data *parent_cpu_data[NR_CPUS];
-+ struct list_head cpu_data_list;
- };
- #endif
-
+++ /dev/null
-From 42d2607d91c4ec37ea1970899c2d614824f3014b Mon Sep 17 00:00:00 2001
-From: Chanwoo Choi <cw00.choi@samsung.com>
-Date: Thu, 19 May 2022 10:07:53 +0900
-Subject: [PATCH 5/5] PM / devfreq: passive: Return non-error when
- not-supported event is required
-
-Each devfreq governor specifies the supported governor event
-such as GOV_START and GOV_STOP. When not-supported event is required,
-just return non-error. But, commit ce9a0d88d97a ("PM / devfreq: Add
-cpu based scaling support to passive governor") returned the error
-value. So that return non-error value when not-supported event is required.
-
-Fixes: ce9a0d88d97a ("PM / devfreq: Add cpu based scaling support to passive governor")
-Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/devfreq/governor_passive.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -402,7 +402,7 @@ static int devfreq_passive_event_handler
- {
- struct devfreq_passive_data *p_data
- = (struct devfreq_passive_data *)devfreq->data;
-- int ret = -EINVAL;
-+ int ret = 0;
-
- if (!p_data)
- return -EINVAL;
+++ /dev/null
-From 82c66d2bbbeda9e493487e7413769087a0b46250 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 20 Jun 2022 00:29:39 +0200
-Subject: [PATCH 1/1] PM / devfreq: Fix kernel warning with cpufreq passive
- register fail
-
-Remove cpufreq_passive_unregister_notifier from
-cpufreq_passive_register_notifier in case of error as devfreq core
-already call unregister on GOV_START fail.
-
-This fix the kernel always printing a WARN on governor PROBE_DEFER as
-cpufreq_passive_unregister_notifier is called two times and return
-error on the second call as the cpufreq is already unregistered.
-
-Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/governor_passive.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -336,7 +336,6 @@ err_free_cpu_data:
- err_put_policy:
- cpufreq_cpu_put(policy);
- err:
-- WARN_ON(cpufreq_passive_unregister_notifier(devfreq));
-
- return ret;
- }
+++ /dev/null
-From 8953603eb5447be52f6fc3d8fcae1b3ce9899189 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Mon, 6 Jun 2022 11:58:49 +0200
-Subject: [PATCH v4 1/4] PM / devfreq: Fix cpufreq passive unregister erroring
- on PROBE_DEFER
-
-With the passive governor, the cpu based scaling can PROBE_DEFER due to
-the fact that CPU policy are not ready.
-The cpufreq passive unregister notifier is called both from the
-GOV_START errors and for the GOV_STOP and assume the notifier is
-successfully registred every time. With GOV_START failing it's wrong to
-loop over each possible CPU since the register path has failed for
-some CPU policy not ready. Change the logic and unregister the notifer
-based on the current allocated parent_cpu_data list to correctly handle
-errors and the governor unregister path.
-
-Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/governor_passive.c | 39 +++++++++++++-----------------
- 1 file changed, 17 insertions(+), 22 deletions(-)
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -34,6 +34,20 @@ get_parent_cpu_data(struct devfreq_passi
- return NULL;
- }
-
-+static void delete_parent_cpu_data(struct devfreq_passive_data *p_data)
-+{
-+ struct devfreq_cpu_data *parent_cpu_data, *tmp;
-+
-+ list_for_each_entry_safe(parent_cpu_data, tmp, &p_data->cpu_data_list, node) {
-+ list_del(&parent_cpu_data->node);
-+
-+ if (parent_cpu_data->opp_table)
-+ dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
-+
-+ kfree(parent_cpu_data);
-+ }
-+}
-+
- static unsigned long get_target_freq_by_required_opp(struct device *p_dev,
- struct opp_table *p_opp_table,
- struct opp_table *opp_table,
-@@ -222,8 +236,7 @@ static int cpufreq_passive_unregister_no
- {
- struct devfreq_passive_data *p_data
- = (struct devfreq_passive_data *)devfreq->data;
-- struct devfreq_cpu_data *parent_cpu_data;
-- int cpu, ret = 0;
-+ int ret;
-
- if (p_data->nb.notifier_call) {
- ret = cpufreq_unregister_notifier(&p_data->nb,
-@@ -232,27 +245,9 @@ static int cpufreq_passive_unregister_no
- return ret;
- }
-
-- for_each_possible_cpu(cpu) {
-- struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
-- if (!policy) {
-- ret = -EINVAL;
-- continue;
-- }
--
-- parent_cpu_data = get_parent_cpu_data(p_data, policy);
-- if (!parent_cpu_data) {
-- cpufreq_cpu_put(policy);
-- continue;
-- }
--
-- list_del(&parent_cpu_data->node);
-- if (parent_cpu_data->opp_table)
-- dev_pm_opp_put_opp_table(parent_cpu_data->opp_table);
-- kfree(parent_cpu_data);
-- cpufreq_cpu_put(policy);
-- }
-+ delete_parent_cpu_data(p_data);
-
-- return ret;
-+ return 0;
- }
-
- static int cpufreq_passive_register_notifier(struct devfreq *devfreq)
+++ /dev/null
-From 57e00b40033a376de3f3cf0bb9bf7590d2dd679d Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Tue, 14 Jun 2022 13:06:59 +0200
-Subject: [PATCH 1/1] PM / devfreq: Fix kernel panic with cpu based scaling to
- passive gov
-
-The cpufreq passive register notifier can PROBE_DEFER and the devfreq
-struct is freed and then reallocaed on probe retry.
-The current logic assume that the code can't PROBE_DEFER so the devfreq
-struct in the this variable in devfreq_passive_data is assumed to be
-(if already set) always correct.
-This cause kernel panic as the code try to access the wrong address.
-To correctly handle this, update the this variable in
-devfreq_passive_data to the devfreq reallocated struct.
-
-Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
----
- drivers/devfreq/governor_passive.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -401,8 +401,7 @@ static int devfreq_passive_event_handler
- if (!p_data)
- return -EINVAL;
-
-- if (!p_data->this)
-- p_data->this = devfreq;
-+ p_data->this = devfreq;
-
- switch (event) {
- case DEVFREQ_GOV_START:
+++ /dev/null
-From 46d05776a1a5dd8eb479e868f5ff4f4b97d68238 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Mon, 6 Jun 2022 12:39:19 +0200
-Subject: [PATCH v4 3/4] PM / devfreq: Rework freq_table to be local to devfreq
- struct
-
-Currently we reference the freq_table to the profile defined one and we
-make changes on it. Devfreq never supported PROBE_DEFER before the cpu
-based scaling support to the passive governor and assumed that a devfreq
-device could only had error and be done with it.
-Now that a device can PROBE_DEFER a rework to the freq_table logic is
-required.
-
-If a device PROBE_DEFER on the GOV_START, the freq_table is already set
-in the device profile struct and its init is skipped. This is due to the
-fact that it's common for devs to declare this kind of struct static.
-This cause the devfreq logic to find a freq table declared (freq_table
-not NULL) with random data and poiting to the old addrs freed by devm.
-
-This problem CAN be solved by devs by clearing the freq_table in their
-profile struct on driver exit path but it should not be trusted and it
-looks to use a flawed logic.
-
-A better solution is to move the freq_table and max_state to the
-devfreq struct and never change the profile struct.
-This permit to correctly handle PROBE_DEFER since the devfreq struct is
-reallocated and contains new values.
-Also the profile struct should only be used to init the driver and should
-not be used by the devfreq to write the freq_table if it's not provided
-by the driver.
-
-Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/devfreq.c | 71 ++++++++++++++----------------
- drivers/devfreq/governor_passive.c | 14 +++---
- include/linux/devfreq.h | 4 ++
- 3 files changed, 45 insertions(+), 44 deletions(-)
-
---- a/drivers/devfreq/devfreq.c
-+++ b/drivers/devfreq/devfreq.c
-@@ -123,7 +123,7 @@ void devfreq_get_freq_range(struct devfr
- unsigned long *min_freq,
- unsigned long *max_freq)
- {
-- unsigned long *freq_table = devfreq->profile->freq_table;
-+ unsigned long *freq_table = devfreq->freq_table;
- s32 qos_min_freq, qos_max_freq;
-
- lockdep_assert_held(&devfreq->lock);
-@@ -133,11 +133,11 @@ void devfreq_get_freq_range(struct devfr
- * The devfreq drivers can initialize this in either ascending or
- * descending order and devfreq core supports both.
- */
-- if (freq_table[0] < freq_table[devfreq->profile->max_state - 1]) {
-+ if (freq_table[0] < freq_table[devfreq->max_state - 1]) {
- *min_freq = freq_table[0];
-- *max_freq = freq_table[devfreq->profile->max_state - 1];
-+ *max_freq = freq_table[devfreq->max_state - 1];
- } else {
-- *min_freq = freq_table[devfreq->profile->max_state - 1];
-+ *min_freq = freq_table[devfreq->max_state - 1];
- *max_freq = freq_table[0];
- }
-
-@@ -169,8 +169,8 @@ static int devfreq_get_freq_level(struct
- {
- int lev;
-
-- for (lev = 0; lev < devfreq->profile->max_state; lev++)
-- if (freq == devfreq->profile->freq_table[lev])
-+ for (lev = 0; lev < devfreq->max_state; lev++)
-+ if (freq == devfreq->freq_table[lev])
- return lev;
-
- return -EINVAL;
-@@ -178,7 +178,6 @@ static int devfreq_get_freq_level(struct
-
- static int set_freq_table(struct devfreq *devfreq)
- {
-- struct devfreq_dev_profile *profile = devfreq->profile;
- struct dev_pm_opp *opp;
- unsigned long freq;
- int i, count;
-@@ -188,25 +187,22 @@ static int set_freq_table(struct devfreq
- if (count <= 0)
- return -EINVAL;
-
-- profile->max_state = count;
-- profile->freq_table = devm_kcalloc(devfreq->dev.parent,
-- profile->max_state,
-- sizeof(*profile->freq_table),
-- GFP_KERNEL);
-- if (!profile->freq_table) {
-- profile->max_state = 0;
-+ devfreq->max_state = count;
-+ devfreq->freq_table = devm_kcalloc(devfreq->dev.parent,
-+ devfreq->max_state,
-+ sizeof(*devfreq->freq_table),
-+ GFP_KERNEL);
-+ if (!devfreq->freq_table)
- return -ENOMEM;
-- }
-
-- for (i = 0, freq = 0; i < profile->max_state; i++, freq++) {
-+ for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) {
- opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq);
- if (IS_ERR(opp)) {
-- devm_kfree(devfreq->dev.parent, profile->freq_table);
-- profile->max_state = 0;
-+ devm_kfree(devfreq->dev.parent, devfreq->freq_table);
- return PTR_ERR(opp);
- }
- dev_pm_opp_put(opp);
-- profile->freq_table[i] = freq;
-+ devfreq->freq_table[i] = freq;
- }
-
- return 0;
-@@ -246,7 +242,7 @@ int devfreq_update_status(struct devfreq
-
- if (lev != prev_lev) {
- devfreq->stats.trans_table[
-- (prev_lev * devfreq->profile->max_state) + lev]++;
-+ (prev_lev * devfreq->max_state) + lev]++;
- devfreq->stats.total_trans++;
- }
-
-@@ -834,6 +830,9 @@ struct devfreq *devfreq_add_device(struc
- if (err < 0)
- goto err_dev;
- mutex_lock(&devfreq->lock);
-+ } else {
-+ devfreq->freq_table = devfreq->profile->freq_table;
-+ devfreq->max_state = devfreq->profile->max_state;
- }
-
- devfreq->scaling_min_freq = find_available_min_freq(devfreq);
-@@ -869,8 +868,8 @@ struct devfreq *devfreq_add_device(struc
-
- devfreq->stats.trans_table = devm_kzalloc(&devfreq->dev,
- array3_size(sizeof(unsigned int),
-- devfreq->profile->max_state,
-- devfreq->profile->max_state),
-+ devfreq->max_state,
-+ devfreq->max_state),
- GFP_KERNEL);
- if (!devfreq->stats.trans_table) {
- mutex_unlock(&devfreq->lock);
-@@ -879,7 +878,7 @@ struct devfreq *devfreq_add_device(struc
- }
-
- devfreq->stats.time_in_state = devm_kcalloc(&devfreq->dev,
-- devfreq->profile->max_state,
-+ devfreq->max_state,
- sizeof(*devfreq->stats.time_in_state),
- GFP_KERNEL);
- if (!devfreq->stats.time_in_state) {
-@@ -1637,9 +1636,9 @@ static ssize_t available_frequencies_sho
-
- mutex_lock(&df->lock);
-
-- for (i = 0; i < df->profile->max_state; i++)
-+ for (i = 0; i < df->max_state; i++)
- count += scnprintf(&buf[count], (PAGE_SIZE - count - 2),
-- "%lu ", df->profile->freq_table[i]);
-+ "%lu ", df->freq_table[i]);
-
- mutex_unlock(&df->lock);
- /* Truncate the trailing space */
-@@ -1662,7 +1661,7 @@ static ssize_t trans_stat_show(struct de
-
- if (!df->profile)
- return -EINVAL;
-- max_state = df->profile->max_state;
-+ max_state = df->max_state;
-
- if (max_state == 0)
- return sprintf(buf, "Not Supported.\n");
-@@ -1679,19 +1678,17 @@ static ssize_t trans_stat_show(struct de
- len += sprintf(buf + len, " :");
- for (i = 0; i < max_state; i++)
- len += sprintf(buf + len, "%10lu",
-- df->profile->freq_table[i]);
-+ df->freq_table[i]);
-
- len += sprintf(buf + len, " time(ms)\n");
-
- for (i = 0; i < max_state; i++) {
-- if (df->profile->freq_table[i]
-- == df->previous_freq) {
-+ if (df->freq_table[i] == df->previous_freq)
- len += sprintf(buf + len, "*");
-- } else {
-+ else
- len += sprintf(buf + len, " ");
-- }
-- len += sprintf(buf + len, "%10lu:",
-- df->profile->freq_table[i]);
-+
-+ len += sprintf(buf + len, "%10lu:", df->freq_table[i]);
- for (j = 0; j < max_state; j++)
- len += sprintf(buf + len, "%10u",
- df->stats.trans_table[(i * max_state) + j]);
-@@ -1715,7 +1712,7 @@ static ssize_t trans_stat_store(struct d
- if (!df->profile)
- return -EINVAL;
-
-- if (df->profile->max_state == 0)
-+ if (df->max_state == 0)
- return count;
-
- err = kstrtoint(buf, 10, &value);
-@@ -1723,11 +1720,11 @@ static ssize_t trans_stat_store(struct d
- return -EINVAL;
-
- mutex_lock(&df->lock);
-- memset(df->stats.time_in_state, 0, (df->profile->max_state *
-+ memset(df->stats.time_in_state, 0, (df->max_state *
- sizeof(*df->stats.time_in_state)));
- memset(df->stats.trans_table, 0, array3_size(sizeof(unsigned int),
-- df->profile->max_state,
-- df->profile->max_state));
-+ df->max_state,
-+ df->max_state));
- df->stats.total_trans = 0;
- df->stats.last_update = get_jiffies_64();
- mutex_unlock(&df->lock);
---- a/drivers/devfreq/governor_passive.c
-+++ b/drivers/devfreq/governor_passive.c
-@@ -145,18 +145,18 @@ static int get_target_freq_with_devfreq(
- goto out;
-
- /* Use interpolation if required opps is not available */
-- for (i = 0; i < parent_devfreq->profile->max_state; i++)
-- if (parent_devfreq->profile->freq_table[i] == *freq)
-+ for (i = 0; i < parent_devfreq->max_state; i++)
-+ if (parent_devfreq->freq_table[i] == *freq)
- break;
-
-- if (i == parent_devfreq->profile->max_state)
-+ if (i == parent_devfreq->max_state)
- return -EINVAL;
-
-- if (i < devfreq->profile->max_state) {
-- child_freq = devfreq->profile->freq_table[i];
-+ if (i < devfreq->max_state) {
-+ child_freq = devfreq->freq_table[i];
- } else {
-- count = devfreq->profile->max_state;
-- child_freq = devfreq->profile->freq_table[count - 1];
-+ count = devfreq->max_state;
-+ child_freq = devfreq->freq_table[count - 1];
- }
-
- out:
---- a/include/linux/devfreq.h
-+++ b/include/linux/devfreq.h
-@@ -185,6 +185,10 @@ struct devfreq {
- struct notifier_block nb;
- struct delayed_work work;
-
-+ /* devfreq local freq_table */
-+ unsigned long *freq_table;
-+ unsigned int max_state;
-+
- unsigned long previous_freq;
- struct devfreq_dev_status last_status;
-
+++ /dev/null
-From eee9f767c41b03a2744d4b0f0c1a144e4ff41e78 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Mon, 6 Jun 2022 13:01:02 +0200
-Subject: [PATCH v4 4/4] PM / devfreq: Mute warning on governor PROBE_DEFER
-
-Don't print warning when a governor PROBE_DEFER as it's not a real
-GOV_START fail.
-
-Fixes: a03dacb0316f ("PM / devfreq: Add cpu based scaling support to passive governor")
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/devfreq.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/devfreq/devfreq.c
-+++ b/drivers/devfreq/devfreq.c
-@@ -930,8 +930,9 @@ struct devfreq *devfreq_add_device(struc
- err = devfreq->governor->event_handler(devfreq, DEVFREQ_GOV_START,
- NULL);
- if (err) {
-- dev_err(dev, "%s: Unable to start governor for the device\n",
-- __func__);
-+ dev_err_probe(dev, err,
-+ "%s: Unable to start governor for the device\n",
-+ __func__);
- goto err_init;
- }
- create_sysfs_files(devfreq, devfreq->governor);
+++ /dev/null
-From b360514edb4743cbf86fc377699c75e98b1264c7 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 02:18:33 +0200
-Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: reorder qcom_nand_host struct
-
-Reorder structs in nandc driver to save holes.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-2-ansuelsmth@gmail.com
----
- drivers/mtd/nand/raw/qcom_nandc.c | 107 +++++++++++++++++-------------
- 1 file changed, 62 insertions(+), 45 deletions(-)
-
---- a/drivers/mtd/nand/raw/qcom_nandc.c
-+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -237,6 +237,9 @@ nandc_set_reg(chip, reg, \
- * @bam_ce - the array of BAM command elements
- * @cmd_sgl - sgl for NAND BAM command pipe
- * @data_sgl - sgl for NAND BAM consumer/producer pipe
-+ * @last_data_desc - last DMA desc in data channel (tx/rx).
-+ * @last_cmd_desc - last DMA desc in command channel.
-+ * @txn_done - completion for NAND transfer.
- * @bam_ce_pos - the index in bam_ce which is available for next sgl
- * @bam_ce_start - the index in bam_ce which marks the start position ce
- * for current sgl. It will be used for size calculation
-@@ -249,14 +252,14 @@ nandc_set_reg(chip, reg, \
- * @rx_sgl_start - start index in data sgl for rx.
- * @wait_second_completion - wait for second DMA desc completion before making
- * the NAND transfer completion.
-- * @txn_done - completion for NAND transfer.
-- * @last_data_desc - last DMA desc in data channel (tx/rx).
-- * @last_cmd_desc - last DMA desc in command channel.
- */
- struct bam_transaction {
- struct bam_cmd_element *bam_ce;
- struct scatterlist *cmd_sgl;
- struct scatterlist *data_sgl;
-+ struct dma_async_tx_descriptor *last_data_desc;
-+ struct dma_async_tx_descriptor *last_cmd_desc;
-+ struct completion txn_done;
- u32 bam_ce_pos;
- u32 bam_ce_start;
- u32 cmd_sgl_pos;
-@@ -266,25 +269,23 @@ struct bam_transaction {
- u32 rx_sgl_pos;
- u32 rx_sgl_start;
- bool wait_second_completion;
-- struct completion txn_done;
-- struct dma_async_tx_descriptor *last_data_desc;
-- struct dma_async_tx_descriptor *last_cmd_desc;
- };
-
- /*
- * This data type corresponds to the nand dma descriptor
-+ * @dma_desc - low level DMA engine descriptor
- * @list - list for desc_info
-- * @dir - DMA transfer direction
-+ *
- * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
- * ADM
- * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
- * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
-- * @dma_desc - low level DMA engine descriptor
-+ * @dir - DMA transfer direction
- */
- struct desc_info {
-+ struct dma_async_tx_descriptor *dma_desc;
- struct list_head node;
-
-- enum dma_data_direction dir;
- union {
- struct scatterlist adm_sgl;
- struct {
-@@ -292,7 +293,7 @@ struct desc_info {
- int sgl_cnt;
- };
- };
-- struct dma_async_tx_descriptor *dma_desc;
-+ enum dma_data_direction dir;
- };
-
- /*
-@@ -336,52 +337,64 @@ struct nandc_regs {
- /*
- * NAND controller data struct
- *
-- * @controller: base controller structure
-- * @host_list: list containing all the chips attached to the
-- * controller
- * @dev: parent device
-+ *
- * @base: MMIO base
-- * @base_phys: physical base address of controller registers
-- * @base_dma: dma base address of controller registers
-+ *
- * @core_clk: controller clock
- * @aon_clk: another controller clock
- *
-+ * @regs: a contiguous chunk of memory for DMA register
-+ * writes. contains the register values to be
-+ * written to controller
-+ *
-+ * @props: properties of current NAND controller,
-+ * initialized via DT match data
-+ *
-+ * @controller: base controller structure
-+ * @host_list: list containing all the chips attached to the
-+ * controller
-+ *
- * @chan: dma channel
- * @cmd_crci: ADM DMA CRCI for command flow control
- * @data_crci: ADM DMA CRCI for data flow control
-+ *
- * @desc_list: DMA descriptor list (list of desc_infos)
- *
- * @data_buffer: our local DMA buffer for page read/writes,
- * used when we can't use the buffer provided
- * by upper layers directly
-- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
-- * functions
- * @reg_read_buf: local buffer for reading back registers via DMA
-+ *
-+ * @base_phys: physical base address of controller registers
-+ * @base_dma: dma base address of controller registers
- * @reg_read_dma: contains dma address for register read buffer
-- * @reg_read_pos: marker for data read in reg_read_buf
- *
-- * @regs: a contiguous chunk of memory for DMA register
-- * writes. contains the register values to be
-- * written to controller
-- * @cmd1/vld: some fixed controller register values
-- * @props: properties of current NAND controller,
-- * initialized via DT match data
-+ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
-+ * functions
- * @max_cwperpage: maximum QPIC codewords required. calculated
- * from all connected NAND devices pagesize
-+ *
-+ * @reg_read_pos: marker for data read in reg_read_buf
-+ *
-+ * @cmd1/vld: some fixed controller register values
- */
- struct qcom_nand_controller {
-- struct nand_controller controller;
-- struct list_head host_list;
--
- struct device *dev;
-
- void __iomem *base;
-- phys_addr_t base_phys;
-- dma_addr_t base_dma;
-
- struct clk *core_clk;
- struct clk *aon_clk;
-
-+ struct nandc_regs *regs;
-+ struct bam_transaction *bam_txn;
-+
-+ const struct qcom_nandc_props *props;
-+
-+ struct nand_controller controller;
-+ struct list_head host_list;
-+
- union {
- /* will be used only by QPIC for BAM DMA */
- struct {
-@@ -399,22 +412,22 @@ struct qcom_nand_controller {
- };
-
- struct list_head desc_list;
-- struct bam_transaction *bam_txn;
-
- u8 *data_buffer;
-+ __le32 *reg_read_buf;
-+
-+ phys_addr_t base_phys;
-+ dma_addr_t base_dma;
-+ dma_addr_t reg_read_dma;
-+
- int buf_size;
- int buf_count;
- int buf_start;
- unsigned int max_cwperpage;
-
-- __le32 *reg_read_buf;
-- dma_addr_t reg_read_dma;
- int reg_read_pos;
-
-- struct nandc_regs *regs;
--
- u32 cmd1, vld;
-- const struct qcom_nandc_props *props;
- };
-
- /*
-@@ -430,19 +443,21 @@ struct qcom_nand_controller {
- * and reserved bytes
- * @cw_data: the number of bytes within a codeword protected
- * by ECC
-- * @use_ecc: request the controller to use ECC for the
-- * upcoming read/write
-- * @bch_enabled: flag to tell whether BCH ECC mode is used
- * @ecc_bytes_hw: ECC bytes used by controller hardware for this
- * chip
-- * @status: value to be returned if NAND_CMD_STATUS command
-- * is executed
-+ *
- * @last_command: keeps track of last command on this chip. used
- * for reading correct status
- *
- * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for
- * ecc/non-ecc mode for the current nand flash
- * device
-+ *
-+ * @status: value to be returned if NAND_CMD_STATUS command
-+ * is executed
-+ * @use_ecc: request the controller to use ECC for the
-+ * upcoming read/write
-+ * @bch_enabled: flag to tell whether BCH ECC mode is used
- */
- struct qcom_nand_host {
- struct nand_chip chip;
-@@ -451,12 +466,10 @@ struct qcom_nand_host {
- int cs;
- int cw_size;
- int cw_data;
-- bool use_ecc;
-- bool bch_enabled;
- int ecc_bytes_hw;
- int spare_bytes;
- int bbm_size;
-- u8 status;
-+
- int last_command;
-
- u32 cfg0, cfg1;
-@@ -465,23 +478,27 @@ struct qcom_nand_host {
- u32 ecc_bch_cfg;
- u32 clrflashstatus;
- u32 clrreadstatus;
-+
-+ u8 status;
-+ bool use_ecc;
-+ bool bch_enabled;
- };
-
- /*
- * This data type corresponds to the NAND controller properties which varies
- * among different NAND controllers.
- * @ecc_modes - ecc mode for NAND
-+ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
- * @is_bam - whether NAND controller is using BAM
- * @is_qpic - whether NAND CTRL is part of qpic IP
- * @qpic_v2 - flag to indicate QPIC IP version 2
-- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
- */
- struct qcom_nandc_props {
- u32 ecc_modes;
-+ u32 dev_cmd_reg_start;
- bool is_bam;
- bool is_qpic;
- bool qpic_v2;
-- u32 dev_cmd_reg_start;
- };
-
- /* Frees the BAM transaction memory */
+++ /dev/null
-From 862bdedd7f4b8aebf00fdb422062e64896e97809 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 02:18:34 +0200
-Subject: [PATCH 2/2] mtd: nand: raw: qcom_nandc: add support for unprotected
- spare data pages
-
-IPQ8064 nand have special pages where a different layout scheme is used.
-These special page are used by boot partition and on reading them
-lots of warning are reported about wrong ECC data and if written to
-results in broken data and not bootable device.
-
-The layout scheme used by these special page consist in using 512 bytes
-as the codeword size (even for the last codeword) while writing to CFG0
-register. This forces the NAND controller to unprotect the 4 bytes of
-spare data.
-
-Since the kernel is unaware of this different layout for these special
-page, it does try to protect the spare data too during read/write and
-warn about CRC errors.
-
-Add support for this by permitting the user to declare these special
-pages in dts by declaring offset and size of the partition. The driver
-internally will convert these value to nand pages.
-
-On user read/write the page is checked and if it's a boot page the
-correct layout is used.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220616001835.24393-3-ansuelsmth@gmail.com
----
- drivers/mtd/nand/raw/qcom_nandc.c | 199 +++++++++++++++++++++++++++++-
- 1 file changed, 194 insertions(+), 5 deletions(-)
-
---- a/drivers/mtd/nand/raw/qcom_nandc.c
-+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -79,8 +79,10 @@
- #define DISABLE_STATUS_AFTER_WRITE 4
- #define CW_PER_PAGE 6
- #define UD_SIZE_BYTES 9
-+#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
- #define ECC_PARITY_SIZE_BYTES_RS 19
- #define SPARE_SIZE_BYTES 23
-+#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
- #define NUM_ADDR_CYCLES 27
- #define STATUS_BFR_READ 30
- #define SET_RD_MODE_AFTER_STATUS 31
-@@ -101,6 +103,7 @@
- #define ECC_MODE 4
- #define ECC_PARITY_SIZE_BYTES_BCH 8
- #define ECC_NUM_DATA_BYTES 16
-+#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
- #define ECC_FORCE_CLK_OPEN 30
-
- /* NAND_DEV_CMD1 bits */
-@@ -431,12 +434,31 @@ struct qcom_nand_controller {
- };
-
- /*
-+ * NAND special boot partitions
-+ *
-+ * @page_offset: offset of the partition where spare data is not protected
-+ * by ECC (value in pages)
-+ * @page_offset: size of the partition where spare data is not protected
-+ * by ECC (value in pages)
-+ */
-+struct qcom_nand_boot_partition {
-+ u32 page_offset;
-+ u32 page_size;
-+};
-+
-+/*
- * NAND chip structure
- *
-+ * @boot_partitions: array of boot partitions where offset and size of the
-+ * boot partitions are stored
-+ *
- * @chip: base NAND chip structure
- * @node: list node to add itself to host_list in
- * qcom_nand_controller
- *
-+ * @nr_boot_partitions: count of the boot partitions where spare data is not
-+ * protected by ECC
-+ *
- * @cs: chip select value for this chip
- * @cw_size: the number of bytes in a single step/codeword
- * of a page, consisting of all data, ecc, spare
-@@ -455,14 +477,20 @@ struct qcom_nand_controller {
- *
- * @status: value to be returned if NAND_CMD_STATUS command
- * is executed
-+ * @codeword_fixup: keep track of the current layout used by
-+ * the driver for read/write operation.
- * @use_ecc: request the controller to use ECC for the
- * upcoming read/write
- * @bch_enabled: flag to tell whether BCH ECC mode is used
- */
- struct qcom_nand_host {
-+ struct qcom_nand_boot_partition *boot_partitions;
-+
- struct nand_chip chip;
- struct list_head node;
-
-+ int nr_boot_partitions;
-+
- int cs;
- int cw_size;
- int cw_data;
-@@ -480,6 +508,7 @@ struct qcom_nand_host {
- u32 clrreadstatus;
-
- u8 status;
-+ bool codeword_fixup;
- bool use_ecc;
- bool bch_enabled;
- };
-@@ -492,6 +521,7 @@ struct qcom_nand_host {
- * @is_bam - whether NAND controller is using BAM
- * @is_qpic - whether NAND CTRL is part of qpic IP
- * @qpic_v2 - flag to indicate QPIC IP version 2
-+ * @use_codeword_fixup - whether NAND has different layout for boot partitions
- */
- struct qcom_nandc_props {
- u32 ecc_modes;
-@@ -499,6 +529,7 @@ struct qcom_nandc_props {
- bool is_bam;
- bool is_qpic;
- bool qpic_v2;
-+ bool use_codeword_fixup;
- };
-
- /* Frees the BAM transaction memory */
-@@ -1708,7 +1739,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *
- data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
- oob_size1 = host->bbm_size;
-
-- if (qcom_nandc_is_last_cw(ecc, cw)) {
-+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) {
- data_size2 = ecc->size - data_size1 -
- ((ecc->steps - 1) * 4);
- oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +
-@@ -1789,7 +1820,7 @@ check_for_erased_page(struct qcom_nand_h
- }
-
- for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {
-- if (qcom_nandc_is_last_cw(ecc, cw)) {
-+ if (qcom_nandc_is_last_cw(ecc, cw) && !host->codeword_fixup) {
- data_size = ecc->size - ((ecc->steps - 1) * 4);
- oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;
- } else {
-@@ -1947,7 +1978,7 @@ static int read_page_ecc(struct qcom_nan
- for (i = 0; i < ecc->steps; i++) {
- int data_size, oob_size;
-
-- if (qcom_nandc_is_last_cw(ecc, i)) {
-+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {
- data_size = ecc->size - ((ecc->steps - 1) << 2);
- oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
- host->spare_bytes;
-@@ -2044,6 +2075,69 @@ static int copy_last_cw(struct qcom_nand
- return ret;
- }
-
-+static bool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page)
-+{
-+ struct qcom_nand_boot_partition *boot_partition;
-+ u32 start, end;
-+ int i;
-+
-+ /*
-+ * Since the frequent access will be to the non-boot partitions like rootfs,
-+ * optimize the page check by:
-+ *
-+ * 1. Checking if the page lies after the last boot partition.
-+ * 2. Checking from the boot partition end.
-+ */
-+
-+ /* First check the last boot partition */
-+ boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1];
-+ start = boot_partition->page_offset;
-+ end = start + boot_partition->page_size;
-+
-+ /* Page is after the last boot partition end. This is NOT a boot partition */
-+ if (page > end)
-+ return false;
-+
-+ /* Actually check if it's a boot partition */
-+ if (page < end && page >= start)
-+ return true;
-+
-+ /* Check the other boot partitions starting from the second-last partition */
-+ for (i = host->nr_boot_partitions - 2; i >= 0; i--) {
-+ boot_partition = &host->boot_partitions[i];
-+ start = boot_partition->page_offset;
-+ end = start + boot_partition->page_size;
-+
-+ if (page < end && page >= start)
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page)
-+{
-+ bool codeword_fixup = qcom_nandc_is_boot_partition(host, page);
-+
-+ /* Skip conf write if we are already in the correct mode */
-+ if (codeword_fixup == host->codeword_fixup)
-+ return;
-+
-+ host->codeword_fixup = codeword_fixup;
-+
-+ host->cw_data = codeword_fixup ? 512 : 516;
-+ host->spare_bytes = host->cw_size - host->ecc_bytes_hw -
-+ host->bbm_size - host->cw_data;
-+
-+ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK);
-+ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES |
-+ host->cw_data << UD_SIZE_BYTES;
-+
-+ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK;
-+ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES;
-+ host->ecc_buf_cfg = (host->cw_data - 1) << NUM_STEPS;
-+}
-+
- /* implements ecc->read_page() */
- static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,
- int oob_required, int page)
-@@ -2052,6 +2146,9 @@ static int qcom_nandc_read_page(struct n
- struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- u8 *data_buf, *oob_buf = NULL;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- nand_read_page_op(chip, page, 0, NULL, 0);
- data_buf = buf;
- oob_buf = oob_required ? chip->oob_poi : NULL;
-@@ -2071,6 +2168,9 @@ static int qcom_nandc_read_page_raw(stru
- int cw, ret;
- u8 *data_buf = buf, *oob_buf = chip->oob_poi;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- for (cw = 0; cw < ecc->steps; cw++) {
- ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,
- page, cw);
-@@ -2091,6 +2191,9 @@ static int qcom_nandc_read_oob(struct na
- struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- struct nand_ecc_ctrl *ecc = &chip->ecc;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- clear_read_regs(nandc);
- clear_bam_transaction(nandc);
-
-@@ -2111,6 +2214,9 @@ static int qcom_nandc_write_page(struct
- u8 *data_buf, *oob_buf;
- int i, ret;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- nand_prog_page_begin_op(chip, page, 0, NULL, 0);
-
- clear_read_regs(nandc);
-@@ -2126,7 +2232,7 @@ static int qcom_nandc_write_page(struct
- for (i = 0; i < ecc->steps; i++) {
- int data_size, oob_size;
-
-- if (qcom_nandc_is_last_cw(ecc, i)) {
-+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {
- data_size = ecc->size - ((ecc->steps - 1) << 2);
- oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +
- host->spare_bytes;
-@@ -2183,6 +2289,9 @@ static int qcom_nandc_write_page_raw(str
- u8 *data_buf, *oob_buf;
- int i, ret;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- nand_prog_page_begin_op(chip, page, 0, NULL, 0);
- clear_read_regs(nandc);
- clear_bam_transaction(nandc);
-@@ -2201,7 +2310,7 @@ static int qcom_nandc_write_page_raw(str
- data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
- oob_size1 = host->bbm_size;
-
-- if (qcom_nandc_is_last_cw(ecc, i)) {
-+ if (qcom_nandc_is_last_cw(ecc, i) && !host->codeword_fixup) {
- data_size2 = ecc->size - data_size1 -
- ((ecc->steps - 1) << 2);
- oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +
-@@ -2261,6 +2370,9 @@ static int qcom_nandc_write_oob(struct n
- int data_size, oob_size;
- int ret;
-
-+ if (host->nr_boot_partitions)
-+ qcom_nandc_codeword_fixup(host, page);
-+
- host->use_ecc = true;
- clear_bam_transaction(nandc);
-
-@@ -2922,6 +3034,74 @@ static int qcom_nandc_setup(struct qcom_
-
- static const char * const probes[] = { "cmdlinepart", "ofpart", "qcomsmem", NULL };
-
-+static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc,
-+ struct qcom_nand_host *host,
-+ struct device_node *dn)
-+{
-+ struct nand_chip *chip = &host->chip;
-+ struct mtd_info *mtd = nand_to_mtd(chip);
-+ struct qcom_nand_boot_partition *boot_partition;
-+ struct device *dev = nandc->dev;
-+ int partitions_count, i, j, ret;
-+
-+ if (!of_find_property(dn, "qcom,boot-partitions", NULL))
-+ return 0;
-+
-+ partitions_count = of_property_count_u32_elems(dn, "qcom,boot-partitions");
-+ if (partitions_count <= 0) {
-+ dev_err(dev, "Error parsing boot partition\n");
-+ return partitions_count ? partitions_count : -EINVAL;
-+ }
-+
-+ host->nr_boot_partitions = partitions_count / 2;
-+ host->boot_partitions = devm_kcalloc(dev, host->nr_boot_partitions,
-+ sizeof(*host->boot_partitions), GFP_KERNEL);
-+ if (!host->boot_partitions) {
-+ host->nr_boot_partitions = 0;
-+ return -ENOMEM;
-+ }
-+
-+ for (i = 0, j = 0; i < host->nr_boot_partitions; i++, j += 2) {
-+ boot_partition = &host->boot_partitions[i];
-+
-+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j,
-+ &boot_partition->page_offset);
-+ if (ret) {
-+ dev_err(dev, "Error parsing boot partition offset at index %d\n", i);
-+ host->nr_boot_partitions = 0;
-+ return ret;
-+ }
-+
-+ if (boot_partition->page_offset % mtd->writesize) {
-+ dev_err(dev, "Boot partition offset not multiple of writesize at index %i\n",
-+ i);
-+ host->nr_boot_partitions = 0;
-+ return -EINVAL;
-+ }
-+ /* Convert offset to nand pages */
-+ boot_partition->page_offset /= mtd->writesize;
-+
-+ ret = of_property_read_u32_index(dn, "qcom,boot-partitions", j + 1,
-+ &boot_partition->page_size);
-+ if (ret) {
-+ dev_err(dev, "Error parsing boot partition size at index %d\n", i);
-+ host->nr_boot_partitions = 0;
-+ return ret;
-+ }
-+
-+ if (boot_partition->page_size % mtd->writesize) {
-+ dev_err(dev, "Boot partition size not multiple of writesize at index %i\n",
-+ i);
-+ host->nr_boot_partitions = 0;
-+ return -EINVAL;
-+ }
-+ /* Convert size to nand pages */
-+ boot_partition->page_size /= mtd->writesize;
-+ }
-+
-+ return 0;
-+}
-+
- static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
- struct qcom_nand_host *host,
- struct device_node *dn)
-@@ -2979,6 +3159,14 @@ static int qcom_nand_host_init_and_regis
- if (ret)
- nand_cleanup(chip);
-
-+ if (nandc->props->use_codeword_fixup) {
-+ ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn);
-+ if (ret) {
-+ nand_cleanup(chip);
-+ return ret;
-+ }
-+ }
-+
- return ret;
- }
-
-@@ -3144,6 +3332,7 @@ static int qcom_nandc_remove(struct plat
- static const struct qcom_nandc_props ipq806x_nandc_props = {
- .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
- .is_bam = false,
-+ .use_codeword_fixup = true,
- .dev_cmd_reg_start = 0x0,
- };
-
+++ /dev/null
-From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 30 Apr 2022 07:44:56 +0200
-Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro
-
-Use regmap_read_poll_timeout macro instead of do-while structure to tidy
-things up. Also set a timeout to prevent any sort of system stall.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
----
- drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------
- 1 file changed, 9 insertions(+), 6 deletions(-)
-
---- a/drivers/clk/qcom/clk-hfpll.c
-+++ b/drivers/clk/qcom/clk-hfpll.c
-@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl
- regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
-
- /* Wait for PLL to lock. */
-- if (hd->status_reg) {
-- do {
-- regmap_read(regmap, hd->status_reg, &val);
-- } while (!(val & BIT(hd->lock_bit)));
-- } else {
-+ if (hd->status_reg)
-+ /*
-+ * Busy wait. Should never timeout, we add a timeout to
-+ * prevent any sort of stall.
-+ */
-+ regmap_read_poll_timeout(regmap, hd->status_reg, val,
-+ !(val & BIT(hd->lock_bit)), 0,
-+ 100 * USEC_PER_MSEC);
-+ else
- udelay(60);
-- }
-
- /* Enable PLL output. */
- regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
+++ /dev/null
-From 898d0d6483a9360f1968e0a900465c1fa152a4a9 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Sat, 30 Apr 2022 07:44:58 +0200
-Subject: [PATCH 3/3] clk: qcom: clk-krait: add apq/ipq8064 errata workaround
-
-Add apq/ipq8064 errata workaround where the sec_src clock gating needs to
-be disabled during switching. krait-cc compatible is not enough to
-handle this and limit this workaround to apq/ipq8064. We check machine
-compatible to handle this.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220430054458.31321-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/clk-krait.c | 16 ++++++++++++++++
- drivers/clk/qcom/clk-krait.h | 1 +
- drivers/clk/qcom/krait-cc.c | 8 ++++++++
- 3 files changed, 25 insertions(+)
-
---- a/drivers/clk/qcom/clk-krait.c
-+++ b/drivers/clk/qcom/clk-krait.c
-@@ -18,13 +18,23 @@
- static DEFINE_SPINLOCK(krait_clock_reg_lock);
-
- #define LPL_SHIFT 8
-+#define SECCLKAGD BIT(4)
-+
- static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
- {
- unsigned long flags;
- u32 regval;
-
- spin_lock_irqsave(&krait_clock_reg_lock, flags);
-+
- regval = krait_get_l2_indirect_reg(mux->offset);
-+
-+ /* apq/ipq8064 Errata: disable sec_src clock gating during switch. */
-+ if (mux->disable_sec_src_gating) {
-+ regval |= SECCLKAGD;
-+ krait_set_l2_indirect_reg(mux->offset, regval);
-+ }
-+
- regval &= ~(mux->mask << mux->shift);
- regval |= (sel & mux->mask) << mux->shift;
- if (mux->lpl) {
-@@ -33,6 +43,12 @@ static void __krait_mux_set_sel(struct k
- }
- krait_set_l2_indirect_reg(mux->offset, regval);
-
-+ /* apq/ipq8064 Errata: re-enabled sec_src clock gating. */
-+ if (mux->disable_sec_src_gating) {
-+ regval &= ~SECCLKAGD;
-+ krait_set_l2_indirect_reg(mux->offset, regval);
-+ }
-+
- /* Wait for switch to complete. */
- mb();
- udelay(1);
---- a/drivers/clk/qcom/clk-krait.h
-+++ b/drivers/clk/qcom/clk-krait.h
-@@ -15,6 +15,7 @@ struct krait_mux_clk {
- u8 safe_sel;
- u8 old_index;
- bool reparent;
-+ bool disable_sec_src_gating;
-
- struct clk_hw hw;
- struct notifier_block clk_nb;
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -139,6 +139,14 @@ krait_add_sec_mux(struct device *dev, in
- mux->hw.init = &init;
- mux->safe_sel = 0;
-
-+ /* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
-+ * enough to limit this to apq/ipq8064. Directly check machine
-+ * compatible to correctly handle this errata.
-+ */
-+ if (of_machine_is_compatible("qcom,ipq8064") ||
-+ of_machine_is_compatible("qcom,apq8064"))
-+ mux->disable_sec_src_gating = true;
-+
- init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
- if (!init.name)
- return -ENOMEM;
+++ /dev/null
-From e4cacac0cae3ce7399b70df3bce92eac03151624 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 12 Apr 2022 16:48:39 +0200
-Subject: [PATCH 3/4] clk: introduce (devm_)hw_register_mux_parent_data_table
- API
-
-Introduce (devm_)hw_register_mux_parent_data_table new API. We have
-basic support for clk_register_mux using parent_data but we lack any API
-to provide a custom parent_map. Add these 2 new API to correctly handle
-these special configuration instead of using the generic
-__(devm_)clk_hw_register_mux API.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- include/linux/clk-provider.h | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/include/linux/clk-provider.h
-+++ b/include/linux/clk-provider.h
-@@ -955,12 +955,26 @@ struct clk *clk_register_mux_table(struc
- __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
- (parent_data), (flags), (reg), (shift), \
- BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
-+#define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
-+ num_parents, flags, reg, shift, \
-+ width, clk_mux_flags, table, \
-+ lock) \
-+ __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
-+ (parent_data), (flags), (reg), (shift), \
-+ BIT((width)) - 1, (clk_mux_flags), table, (lock))
- #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
- shift, width, clk_mux_flags, lock) \
- __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
- (parent_names), NULL, NULL, (flags), (reg), \
- (shift), BIT((width)) - 1, (clk_mux_flags), \
- NULL, (lock))
-+#define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
-+ num_parents, flags, reg, shift, \
-+ width, clk_mux_flags, table, \
-+ lock) \
-+ __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
-+ NULL, (parent_data), (flags), (reg), (shift), \
-+ BIT((width)) - 1, (clk_mux_flags), table, (lock))
-
- int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
- unsigned int val);
+++ /dev/null
-From d08c79b818767f24c3c9cbba585d8a3ec896c1a1 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 17 Feb 2022 22:43:34 +0100
-Subject: [PATCH 4/4] clk: qcom: kpss-xcc: convert to parent data API
-
-Convert the driver to parent data API. From the Documentation pll8_vote
-and pxo should be declared in the DTS so fw_name can be used instead of
-parent_names. Name is still used to save regression on old definition.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/kpss-xcc.c | 26 +++++++++-----------------
- 1 file changed, 9 insertions(+), 17 deletions(-)
-
---- a/drivers/clk/qcom/kpss-xcc.c
-+++ b/drivers/clk/qcom/kpss-xcc.c
-@@ -12,9 +12,9 @@
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
-
--static const char *aux_parents[] = {
-- "pll8_vote",
-- "pxo",
-+static const struct clk_parent_data aux_parents[] = {
-+ { .name = "pll8_vote", .fw_name = "pll8_vote" },
-+ { .name = "pxo", .fw_name = "pxo" },
- };
-
- static unsigned int aux_parent_map[] = {
-@@ -32,9 +32,9 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
- static int kpss_xcc_driver_probe(struct platform_device *pdev)
- {
- const struct of_device_id *id;
-- struct clk *clk;
- struct resource *res;
- void __iomem *base;
-+ struct clk_hw *hw;
- const char *name;
-
- id = of_match_device(kpss_xcc_match_table, &pdev->dev);
-@@ -57,24 +57,16 @@ static int kpss_xcc_driver_probe(struct
- base += 0x28;
- }
-
-- clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
-- ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
-- 0, aux_parent_map, NULL);
-+ hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
-+ ARRAY_SIZE(aux_parents), 0,
-+ base, 0, 0x3,
-+ 0, aux_parent_map, NULL);
-
-- platform_set_drvdata(pdev, clk);
--
-- return PTR_ERR_OR_ZERO(clk);
--}
--
--static int kpss_xcc_driver_remove(struct platform_device *pdev)
--{
-- clk_unregister_mux(platform_get_drvdata(pdev));
-- return 0;
-+ return PTR_ERR_OR_ZERO(hw);
- }
-
- static struct platform_driver kpss_xcc_driver = {
- .probe = kpss_xcc_driver_probe,
-- .remove = kpss_xcc_driver_remove,
- .driver = {
- .name = "kpss-xcc",
- .of_match_table = kpss_xcc_match_table,
+++ /dev/null
-From aa7fd3bb6017b343585e97a909f9b7d2fe174018 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 00:53:19 +0200
-Subject: [PATCH] ARM: dts: qcom: add rpmcc missing clocks for apq/ipq8064 and
- msm8660
-
-Add missing rpmcc pxo and cxo clock for apq8064, ipq8064 and
-msm8660 dtsi.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220706225321.26215-3-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 ++
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++
- arch/arm/boot/dts/qcom-msm8660.dtsi | 4 +++-
- 3 files changed, 7 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-apq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
-@@ -862,6 +862,8 @@
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
- #clock-cells = <1>;
-+ clocks = <&pxo_board>, <&cxo_board>;
-+ clock-names = "pxo", "cxo";
- };
-
- regulators {
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1074,6 +1074,8 @@
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
- #clock-cells = <1>;
-+ clocks = <&pxo_board>;
-+ clock-names = "pxo";
- };
- };
-
---- a/arch/arm/boot/dts/qcom-msm8660.dtsi
-+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
-@@ -56,7 +56,7 @@
- clock-frequency = <19200000>;
- };
-
-- pxo_board {
-+ pxo_board: pxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
-@@ -420,6 +420,8 @@
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
- #clock-cells = <1>;
-+ clocks = <&pxo_board>;
-+ clock-names = "pxo";
- };
-
- pm8901-regulators {
+++ /dev/null
-From 129d9cd9c25041f8b8681fd6e8584fa47c385f3b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 7 Jul 2022 00:53:20 +0200
-Subject: [PATCH] clk: qcom: clk-rpm: convert to parent_data API
-
-Convert clk-rpm driver to parent_data API.
-We keep the old pxo/cxo_board parent naming to keep compatibility with
-old DT and we use the new pxo/cxo for new implementation where these
-clock are defined in DTS.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/clk-rpm.c | 24 ++++++++++++++++--------
- 1 file changed, 16 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/qcom/clk-rpm.c
-+++ b/drivers/clk/qcom/clk-rpm.c
-@@ -23,6 +23,14 @@
- #define QCOM_RPM_SCALING_ENABLE_ID 0x2
- #define QCOM_RPM_XO_MODE_ON 0x2
-
-+static const struct clk_parent_data gcc_pxo[] = {
-+ { .fw_name = "pxo", .name = "pxo_board" },
-+};
-+
-+static const struct clk_parent_data gcc_cxo[] = {
-+ { .fw_name = "cxo", .name = "cxo_board" },
-+};
-+
- #define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
- static struct clk_rpm _platform##_##_active; \
- static struct clk_rpm _platform##_##_name = { \
-@@ -32,8 +40,8 @@
- .hw.init = &(struct clk_init_data){ \
- .ops = &clk_rpm_ops, \
- .name = #_name, \
-- .parent_names = (const char *[]){ "pxo_board" }, \
-- .num_parents = 1, \
-+ .parent_data = gcc_pxo, \
-+ .num_parents = ARRAY_SIZE(gcc_pxo), \
- }, \
- }; \
- static struct clk_rpm _platform##_##_active = { \
-@@ -44,8 +52,8 @@
- .hw.init = &(struct clk_init_data){ \
- .ops = &clk_rpm_ops, \
- .name = #_active, \
-- .parent_names = (const char *[]){ "pxo_board" }, \
-- .num_parents = 1, \
-+ .parent_data = gcc_pxo, \
-+ .num_parents = ARRAY_SIZE(gcc_pxo), \
- }, \
- }
-
-@@ -56,8 +64,8 @@
- .hw.init = &(struct clk_init_data){ \
- .ops = &clk_rpm_xo_ops, \
- .name = #_name, \
-- .parent_names = (const char *[]){ "cxo_board" }, \
-- .num_parents = 1, \
-+ .parent_data = gcc_cxo, \
-+ .num_parents = ARRAY_SIZE(gcc_cxo), \
- }, \
- }
-
-@@ -68,8 +76,8 @@
- .hw.init = &(struct clk_init_data){ \
- .ops = &clk_rpm_fixed_ops, \
- .name = #_name, \
-- .parent_names = (const char *[]){ "pxo" }, \
-- .num_parents = 1, \
-+ .parent_data = gcc_pxo, \
-+ .num_parents = ARRAY_SIZE(gcc_pxo), \
- }, \
- }
-
+++ /dev/null
-From 7df140e84a75c89962feef659d686303d3ce75e5 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 21 Oct 2022 18:53:04 +0200
-Subject: [PATCH] mtd: rawnand: qcom: handle ret from parse with codeword_fixup
-
-With use_codeword_fixup enabled, any return from
-mtd_device_parse_register gets overwritten. Aside from the clear bug, this
-is also problematic as a parser can EPROBE_DEFER and because this is not
-correctly handled, the nand is never rescanned later in the bootup
-process.
-
-An example of this problem is when smem requires additional time to be
-probed and nandc use qcomsmempart as parser. Parser will return
-EPROBE_DEFER but in the current code this ret gets overwritten by
-qcom_nand_host_parse_boot_partitions and qcom_nand_host_init_and_register
-return 0.
-
-Correctly handle the return code from mtd_device_parse_register so that
-any error from this function is not ignored.
-
-Fixes: 862bdedd7f4b ("mtd: nand: raw: qcom_nandc: add support for unprotected spare data pages")
-Cc: stable@vger.kernel.org # v6.0+
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20221021165304.19991-1-ansuelsmth@gmail.com
----
- drivers/mtd/nand/raw/qcom_nandc.c | 12 +++++++-----
- 1 file changed, 7 insertions(+), 5 deletions(-)
-
---- a/drivers/mtd/nand/raw/qcom_nandc.c
-+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -3157,16 +3157,18 @@ static int qcom_nand_host_init_and_regis
-
- ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
- if (ret)
-- nand_cleanup(chip);
-+ goto err;
-
- if (nandc->props->use_codeword_fixup) {
- ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn);
-- if (ret) {
-- nand_cleanup(chip);
-- return ret;
-- }
-+ if (ret)
-+ goto err;
- }
-
-+ return 0;
-+
-+err:
-+ nand_cleanup(chip);
- return ret;
- }
-
projects / openwrt / staging / ldir.git / commitdiff