EXYNOS5: FDT : Decode peripheral id

Api is added to decode peripheral id based on the interrupt number
of the peripheral.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index ee58dac3a0f5e1f3e6c59c99657a253835142dd0..bd499b47614ca2b1af126642931fa627d14f45ca 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
@@ -447,3 +448,31 @@ int exynos_pinmux_config(int peripheral, int flags)
                return -1;
        }
 }
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+       int err;
+       u32 cell[3];
+
+       err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+                                       ARRAY_SIZE(cell));
+       if (err)
+               return PERIPH_ID_NONE;
+
+       /* check for invalid peripheral id */
+       if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
+               return cell[1];
+
+       debug(" invalid peripheral id\n");
+       return PERIPH_ID_NONE;
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+       if (cpu_is_exynos5())
+               return  exynos5_pinmux_decode_periph_id(blob, node);
+       else
+               return PERIPH_ID_NONE;
+}
+#endif

diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 13abd2d703a58d7dacb42dd533aff3b4a6c0a8bf..89bcdfc0cc3ffec97abd7edbc9e3382d65503443 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -25,12 +25,17 @@
 #define __ASM_ARM_ARCH_PERIPH_H
 
 /*
- * Peripherals requiring clock/pinmux configuration. List will
+ * Peripherals required for pinmux configuration. List will
  * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
  *
  */
 enum periph_id {
-       PERIPH_ID_I2C0,
+       PERIPH_ID_UART0 = 51,
+       PERIPH_ID_UART1,
+       PERIPH_ID_UART2,
+       PERIPH_ID_UART3,
+       PERIPH_ID_I2C0 = 56,
        PERIPH_ID_I2C1,
        PERIPH_ID_I2C2,
        PERIPH_ID_I2C3,
@@ -38,22 +43,24 @@ enum periph_id {
        PERIPH_ID_I2C5,
        PERIPH_ID_I2C6,
        PERIPH_ID_I2C7,
-       PERIPH_ID_I2S1,
-       PERIPH_ID_SDMMC0,
+       PERIPH_ID_SPI0 = 68,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SDMMC0 = 75,
        PERIPH_ID_SDMMC1,
        PERIPH_ID_SDMMC2,
        PERIPH_ID_SDMMC3,
-       PERIPH_ID_SDMMC4,
-       PERIPH_ID_SROMC,
-       PERIPH_ID_SPI0,
-       PERIPH_ID_SPI1,
-       PERIPH_ID_SPI2,
+       PERIPH_ID_I2S1 = 99,
+
+       /* Since following peripherals do
+        * not have shared peripheral interrupts (SPIs)
+        * they are numbered arbitiraly after the maximum
+        * SPIs Exynos has (128)
+        */
+       PERIPH_ID_SROMC = 128,
        PERIPH_ID_SPI3,
        PERIPH_ID_SPI4,
-       PERIPH_ID_UART0,
-       PERIPH_ID_UART1,
-       PERIPH_ID_UART2,
-       PERIPH_ID_UART3,
+       PERIPH_ID_SDMMC4,
 
        PERIPH_ID_COUNT,
        PERIPH_ID_NONE = -1,

diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h
index 10ea736c7dd3a2091515bd4a938195b5aaee7dd4..014eebc75d97919aa85b8eef593ceeb15a9e9e4f 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/pinmux.h
+++ b/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -55,4 +55,12 @@ enum {
  */
 int exynos_pinmux_config(int peripheral, int flags);
 
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob  Device tree blob
+ * @param node  FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
 #endif