drm/i915: Perform a central cdclk state sanity check

WARN if the cdclk state doesn't match what we expect after programming.
And let's remove the WARN from bdw_set_cdclk() that's trying to achieve
the same thing in a more limite fashion.

Also take the opportunity to refactor the code to use a common function
for dumping out a cdclk state.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-11-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index fedfe3c720b62af9bc7bc5ea276bd52b2db54ebd..51cd23dd867646486caaab7dc22d93497c78c04e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -768,10 +768,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
        I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 
        intel_update_cdclk(dev_priv);
-
-       WARN(cdclk != dev_priv->cdclk.hw.cdclk,
-            "cdclk requested %d kHz but got %d kHz\n",
-            cdclk, dev_priv->cdclk.hw.cdclk);
 }
 
 static int skl_calc_cdclk(int min_cdclk, int vco)
@@ -1068,6 +1064,8 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
                goto sanitize;
 
        intel_update_cdclk(dev_priv);
+       intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
        /* Is PLL enabled and locked ? */
        if (dev_priv->cdclk.hw.vco == 0 ||
            dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1407,6 +1405,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
        u32 cdctl, expected;
 
        intel_update_cdclk(dev_priv);
+       intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
        if (dev_priv->cdclk.hw.vco == 0 ||
            dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1713,6 +1712,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
        u32 cdctl, expected;
 
        intel_update_cdclk(dev_priv);
+       intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
        if (dev_priv->cdclk.hw.vco == 0 ||
            dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1826,6 +1826,14 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
                a->voltage_level != b->voltage_level;
 }
 
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+                           const char *context)
+{
+       DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
+                        context, cdclk_state->cdclk, cdclk_state->vco,
+                        cdclk_state->ref, cdclk_state->voltage_level);
+}
+
 /**
  * intel_set_cdclk - Push the CDCLK state to the hardware
  * @dev_priv: i915 device
@@ -1843,11 +1851,15 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
        if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
                return;
 
-       DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
-                        cdclk_state->cdclk, cdclk_state->vco,
-                        cdclk_state->ref, cdclk_state->voltage_level);
+       intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
 
        dev_priv->display.set_cdclk(dev_priv, cdclk_state);
+
+       if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
+                "cdclk state doesn't match!\n")) {
+               intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
+               intel_dump_cdclk_state(cdclk_state, "[sw state]");
+       }
 }
 
 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
@@ -2280,10 +2292,6 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 {
        dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
 
-       DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
-                        dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
-                        dev_priv->cdclk.hw.ref);
-
        /*
         * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
         * Programmng [sic] note: bit[9:2] should be programmed to the number

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b5fa643e1812b792fe45fcd7dc62776ea820559d..7d7952b78a3b8ccd6dc0fd776c4a7c0d39e3025e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8857,7 +8857,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
        }
 
        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
        intel_update_cdclk(dev_priv);
+       intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 }
 
 /*
@@ -14358,6 +14360,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
        struct drm_i915_private *dev_priv = to_i915(dev);
 
        intel_update_cdclk(dev_priv);
+       intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
        dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
 
        intel_init_clock_gating(dev_priv);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3de8d98baed76f7ee2b63d56a9e88b4fd7f9ffcf..3b4eafd39f558d0d751b4a3ec902bb5b21b7018c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1336,6 +1336,8 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
                         const struct intel_cdclk_state *b);
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
                     const struct intel_cdclk_state *cdclk_state);
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+                           const char *context);
 
 /* intel_display.c */
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);