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ath79: ar913x: fix eth pll register
author
Chuanhong Guo
<gch981213@gmail.com>
Sun, 12 Aug 2018 13:13:31 +0000
(21:13 +0800)
committer
Mathias Kresin
<dev@kresin.me>
Mon, 13 Aug 2018 06:37:19 +0000
(08:37 +0200)
PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
target/linux/ath79/dts/ar9132.dtsi
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diff --git
a/target/linux/ath79/dts/ar9132.dtsi
b/target/linux/ath79/dts/ar9132.dtsi
index 01572c022e03d2042735f8c87565df4ca13de566..9d8ddcf9ba13a3ee7825ea1097821c6bd884a473 100644
(file)
--- a/
target/linux/ath79/dts/ar9132.dtsi
+++ b/
target/linux/ath79/dts/ar9132.dtsi
@@
-189,7
+189,7
@@
reg = <0x19000000 0x200
0x18070000 0x4>;
pll-data = <0x1a000000 0x13000a44 0x00441099>;
- pll-reg = <0x4 0x1
0 17
>;
+ pll-reg = <0x4 0x1
4 20
>;
pll-handle = <&pll>;
resets = <&rst 9>;
reset-names = "mac";