kernel: 5.10: Backport Armada 3720 comphy patches from 5.15
authorMarek Behún <kabel@kernel.org>
Tue, 11 Jan 2022 13:02:12 +0000 (14:02 +0100)
committerChristian Lamparter <chunkeey@gmail.com>
Sat, 15 Jan 2022 16:26:55 +0000 (17:26 +0100)
Backport 2 patches for Armada 3720 comphy from 5.15 kernel.

These are needed for clear application of pending patches that fix this
driver.

Signed-off-by: Marek Behún <kabel@kernel.org>
target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch [new file with mode: 0644]
target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch [new file with mode: 0644]

diff --git a/target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch b/target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch
new file mode 100644 (file)
index 0000000..53e7b86
--- /dev/null
@@ -0,0 +1,72 @@
+From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Fri, 27 Aug 2021 11:27:52 +0200
+Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to
+ 2500Base-X
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather
+2500Base-X mode which runs at 3.125 Gbps speed.
+
+Rename macro names and comments to 2500Base-X.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+index 810f25a47632..cc534a5c4b3b 100644
+--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+@@ -29,7 +29,7 @@
+ #define COMPHY_FW_MODE_SATA                   0x1
+ #define COMPHY_FW_MODE_SGMII                  0x2
+-#define COMPHY_FW_MODE_HS_SGMII                       0x3
++#define COMPHY_FW_MODE_2500BASEX              0x3
+ #define COMPHY_FW_MODE_USB3H                  0x4
+ #define COMPHY_FW_MODE_USB3D                  0x5
+ #define COMPHY_FW_MODE_PCIE                   0x6
+@@ -40,7 +40,7 @@
+ #define COMPHY_FW_SPEED_1_25G                 0 /* SGMII 1G */
+ #define COMPHY_FW_SPEED_2_5G                  1
+-#define COMPHY_FW_SPEED_3_125G                        2 /* SGMII 2.5G */
++#define COMPHY_FW_SPEED_3_125G                        2 /* 2500BASE-X */
+ #define COMPHY_FW_SPEED_5G                    3
+ #define COMPHY_FW_SPEED_5_15625G              4 /* XFI 5G */
+ #define COMPHY_FW_SPEED_6G                    5
+@@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
+       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
+                                   COMPHY_FW_MODE_SGMII),
+       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
+-                                  COMPHY_FW_MODE_HS_SGMII),
++                                  COMPHY_FW_MODE_2500BASEX),
+       /* lane 1 */
+       MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
+                                   COMPHY_FW_MODE_PCIE),
+       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
+                                   COMPHY_FW_MODE_SGMII),
+       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
+-                                  COMPHY_FW_MODE_HS_SGMII),
++                                  COMPHY_FW_MODE_2500BASEX),
+       /* lane 2 */
+       MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
+                                   COMPHY_FW_MODE_SATA),
+@@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(struct phy *phy)
+                                                COMPHY_FW_SPEED_1_25G);
+                       break;
+               case PHY_INTERFACE_MODE_2500BASEX:
+-                      dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
++                      dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
+                               lane->id);
+                       fw_param = COMPHY_FW_NET(fw_mode, lane->port,
+                                                COMPHY_FW_SPEED_3_125G);
+-- 
+2.34.1
+
diff --git a/target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch b/target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch
new file mode 100644 (file)
index 0000000..3b9c60a
--- /dev/null
@@ -0,0 +1,45 @@
+From e1dbe9ecf621b6f71f3d2df3e50731d583f3d27f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Fri, 27 Aug 2021 11:27:53 +0200
+Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove unsupported
+ modes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Armada 3700 does not support RXAUI, XFI and neither SFI. Remove unused
+macros for these unsupported modes.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+index cc534a5c4b3b..6781488cfc58 100644
+--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+@@ -33,18 +33,12 @@
+ #define COMPHY_FW_MODE_USB3H                  0x4
+ #define COMPHY_FW_MODE_USB3D                  0x5
+ #define COMPHY_FW_MODE_PCIE                   0x6
+-#define COMPHY_FW_MODE_RXAUI                  0x7
+-#define COMPHY_FW_MODE_XFI                    0x8
+-#define COMPHY_FW_MODE_SFI                    0x9
+ #define COMPHY_FW_MODE_USB3                   0xa
+ #define COMPHY_FW_SPEED_1_25G                 0 /* SGMII 1G */
+ #define COMPHY_FW_SPEED_2_5G                  1
+ #define COMPHY_FW_SPEED_3_125G                        2 /* 2500BASE-X */
+ #define COMPHY_FW_SPEED_5G                    3
+-#define COMPHY_FW_SPEED_5_15625G              4 /* XFI 5G */
+-#define COMPHY_FW_SPEED_6G                    5
+-#define COMPHY_FW_SPEED_10_3125G              6 /* XFI 10G */
+ #define COMPHY_FW_SPEED_MAX                   0x3F
+ #define COMPHY_FW_MODE(mode)                  ((mode) << 12)
+-- 
+2.34.1
+