clk: renesas: r8a7796: Add DRIF clock

This patch adds DRIF module clocks for r8a7796 SoC.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index f0302fba948e7a90664c596024e258a6c2dbced0..f2f56e16a7cf74cdc13f086f29f826c2e80693c3 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -128,6 +128,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
        DEF_MOD("rwdt0",                 402,   R8A7796_CLK_R),
        DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
+       DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),