--- /dev/null
+From 79b953605ded6a9a995040a1c8cc665127a6411a Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:45 +0200
+Subject: arm64: allwinner: sun50i-a64: Add dt node for the syscon control
+ module
+
+This patch add the dt node for the syscon register present on the
+Allwinner A64.
+
+Only two register are present in this syscon and the only one useful is
+the one dedicated to EMAC clock.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -129,6 +129,12 @@
+ #size-cells = <1>;
+ ranges;
+
++ syscon: syscon@1c00000 {
++ compatible = "allwinner,sun50i-a64-system-controller",
++ "syscon";
++ reg = <0x01c00000 0x1000>;
++ };
++
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun50i-a64-mmc";
+ reg = <0x01c0f000 0x1000>;
--- /dev/null
+From e53f67e981bcc5547857475241b3a4a066955f8c Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:46 +0200
+Subject: arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
+
+The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
+connections. It is very similar to the device found in the Allwinner
+H3, but lacks the internal 100 Mbit PHY and its associated control
+bits.
+This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
+it disabled at this level.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 +++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -284,6 +284,21 @@
+ bias-pull-up;
+ };
+
++ rmii_pins: rmii_pins {
++ pins = "PD10", "PD11", "PD13", "PD14", "PD17",
++ "PD18", "PD19", "PD20", "PD22", "PD23";
++ function = "emac";
++ drive-strength = <40>;
++ };
++
++ rgmii_pins: rgmii_pins {
++ pins = "PD8", "PD9", "PD10", "PD11", "PD12",
++ "PD13", "PD15", "PD16", "PD17", "PD18",
++ "PD19", "PD20", "PD21", "PD22", "PD23";
++ function = "emac";
++ drive-strength = <40>;
++ };
++
+ uart0_pins_a: uart0@0 {
+ pins = "PB8", "PB9";
+ function = "uart0";
+@@ -388,6 +403,26 @@
+ #size-cells = <0>;
+ };
+
++ emac: ethernet@1c30000 {
++ compatible = "allwinner,sun50i-a64-emac";
++ syscon = <&syscon>;
++ reg = <0x01c30000 0x100>;
++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ resets = <&ccu RST_BUS_EMAC>;
++ reset-names = "stmmaceth";
++ clocks = <&ccu CLK_BUS_EMAC>;
++ clock-names = "stmmaceth";
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mdio: mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
--- /dev/null
+From 97023943749367111b9a88e09d1b9bd157dd3326 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:47 +0200
+Subject: arm64: allwinner: pine64: Enable dwmac-sun8i
+
+The dwmac-sun8i hardware is present on the pine64
+It uses an external PHY via RMII.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -70,6 +70,15 @@
+ status = "okay";
+ };
+
++&emac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rmii_pins>;
++ phy-mode = "rmii";
++ phy-handle = <&ext_rmii_phy1>;
++ status = "okay";
++
++};
++
+ &i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+@@ -80,6 +89,13 @@
+ bias-pull-up;
+ };
+
++&mdio {
++ ext_rmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
++};
++
+ &mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
--- /dev/null
+From 94dcfdc77fc55ed1956011ceea341911c6e760a0 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Wed, 31 May 2017 09:18:48 +0200
+Subject: arm64: allwinner: pine64-plus: Enable dwmac-sun8i
+
+The dwmac-sun8i hardware is present on the pine64 plus.
+It uses an external PHY rtl8211e via RGMII.
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+@@ -46,5 +46,20 @@
+ model = "Pine64+";
+ compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
+
+- /* TODO: Camera, Ethernet PHY, touchscreen, etc. */
++ /* TODO: Camera, touchscreen, etc. */
++};
++
++&emac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_pins>;
++ phy-mode = "rgmii";
++ phy-handle = <&ext_rgmii_phy>;
++ status = "okay";
++};
++
++&mdio {
++ ext_rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
+ };
--- /dev/null
+From 3a4bae5fd44aa1cf49780dd25b3a89e6a39e8560 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe.montjoie@gmail.com>
+Date: Mon, 10 Jul 2017 20:44:40 +0200
+Subject: arm64: allwinner: sun50i-a64: Correct emac register size
+
+The datasheet said that emac register size is 0x10000 not 0x100
+
+Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+[wens@csie.org: Fixed commit subject prefix]
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -406,7 +406,7 @@
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun50i-a64-emac";
+ syscon = <&syscon>;
+- reg = <0x01c30000 0x100>;
++ reg = <0x01c30000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
--- /dev/null
+From dff751c68904cf587d918cfb6b2f5b0112f73bc9 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sat, 22 Jul 2017 10:28:51 +0800
+Subject: arm64: allwinner: a64: pine64: add missing ethernet0 alias
+
+The EMAC Ethernet controller was enabled, but an accompanying alias
+was not added. This results in unstable numbering if other Ethernet
+devices, such as a USB dongle, are present. Also, the bootloader uses
+the alias to assign a generated stable MAC address to the device node.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Fixes: 970239437493 ("arm64: allwinner: pine64: Enable dwmac-sun8i")
+[wens@csie.org: Rewrite commit log as fixing a previous patch with Fixes]
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -51,6 +51,7 @@
+ compatible = "pine64,pine64", "allwinner,sun50i-a64";
+
+ aliases {
++ ethernet0 = &emac;
+ serial0 = &uart0;
+ };
+
projects / openwrt / staging / thess.git / commitdiff