drm/amdgpu: add members in amdgpu_me for gfx queue

Update the structure for gfx10.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9d0ef6a6aab6302ea2e9f3f6f456ea3e22ad6df9..68f7d3cf4fa23e4d0677bc912077748f13cffcb7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -38,6 +38,7 @@
 #define AMDGPU_GFX_CG_DISABLED_MODE            0x00000004L
 #define AMDGPU_GFX_LBPW_DISABLED_MODE          0x00000008L
 
+#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
 
 struct amdgpu_mec {
@@ -211,6 +212,13 @@ struct amdgpu_me {
        struct amdgpu_bo                *me_fw_obj;
        uint64_t                        me_fw_gpu_addr;
        uint32_t                        *me_fw_ptr;
+       uint32_t                        num_me;
+       uint32_t                        num_pipe_per_me;
+       uint32_t                        num_queue_per_pipe;
+       void                            *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
+
+       /* These are the resources for which amdgpu takes ownership */
+       DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 };
 
 struct amdgpu_gfx {