drm/amd/display: WA for DF keeps awake after S0i3.

[Why]
DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL
is set by bios command table during dcn init_hw.

[How]
As a work around, check STATE_CNTL status before init_hw,
if it is 0 before init_hw and set to 1 after init_hw,
change it to 0.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 1ea91e153d3a6b05caebdce7291cda3e4b889495..69345ce688c65f19efc1eee8110b3c918244758b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -87,6 +87,23 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
+void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
+{
+       REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
+}
+
+bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
+{
+       uint32_t enable = 0;
+
+       REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
+
+       return true ? false : enable;
+}
+
+
 bool hubbub1_verify_allow_pstate_change_high(
        struct hubbub *hubbub)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index d6e596eef4c5523b03f0b98e36583108c5819986..d0f03d15291325e091c570525333e9f7f75c33a8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -203,6 +203,10 @@ void hubbub1_program_watermarks(
                unsigned int refclk_mhz,
                bool safe_to_lower);
 
+void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub);
+
+bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
+
 void hubbub1_toggle_watermark_change_req(
                struct hubbub *hubbub);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a881ff5559ecd2a717e28d723c75f065fbfd3df8..193184affefbebc7c555411e881195675526d3d8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -997,7 +997,21 @@ static void dcn10_init_hw(struct dc *dc)
        } else {
 
                if (!dcb->funcs->is_accelerated_mode(dcb)) {
+                       bool allow_self_fresh_force_enable =
+                                       hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+
                        bios_golden_init(dc);
+
+                       /* WA for making DF sleep when idle after resume from S0i3.
+                        * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
+                        * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
+                        * before calling command table and it changed to 1 after,
+                        * it should be set back to 0.
+                        */
+                       if (allow_self_fresh_force_enable == false &&
+                                       hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
+                               hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);
+
                        disable_vga(dc->hwseq);
                }