REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
ath9k_hw_clear_queue_interrupts(ah, q);
- if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
+ if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
ah->txok_interrupt_mask |= 1 << q;
- if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
ah->txerr_interrupt_mask |= 1 << q;
+ }
if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
ah->txdesc_interrupt_mask |= 1 << q;
if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
qi.tqi_cwmax = 0;
if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
- qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
- TXQ_FLAG_TXERRINT_ENABLE;
+ qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
}
#define ATH9K_WME_UPSD 4
enum ath9k_tx_queue_flags {
- TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
- TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
+ TXQ_FLAG_TXINT_ENABLE = 0x0001,
TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
* based intr on the EOSP frames.
*/
if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
- qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
- TXQ_FLAG_TXERRINT_ENABLE;
+ qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
} else {
if (qtype == ATH9K_TX_QUEUE_UAPSD)
qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;