Documentation: DT: add LS1012A compatible for SCFG and DCFG

Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 3b01338c7c297a878ba3bc509f82e202fae6bfae..c9c567ae227f7a3f948ddc3a2ad66ba7d3664f05 100644 (file)
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -108,7 +108,7 @@ status.
   - compatible: Should contain a chip-specific compatible string,
        Chip-specific strings are of the form "fsl,<chip>-scfg",
        The following <chip>s are known to be supported:
-       ls1021a, ls1043a, ls1046a, ls2080a.
+       ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
 
   - reg: should contain base address and length of SCFG memory-mapped registers
 
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
   - compatible: Should contain a chip-specific compatible string,
        Chip-specific strings are of the form "fsl,<chip>-dcfg",
        The following <chip>s are known to be supported:
-       ls1021a, ls1043a, ls1046a, ls2080a.
+       ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
 
   - reg : should contain base address and length of DCFG memory-mapped registers