--- /dev/null
+From 130bbde4809b011faf64f99dddc14b4b01f440c3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Tue, 12 May 2020 09:57:32 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: fix hamming oob layout
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+First 2 bytes are used in large-page nand.
+
+Fixes: ef5eeea6e911 ("mtd: nand: brcm: switch to mtd_ooblayout_ops")
+Cc: stable@vger.kernel.org
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200512075733.745374-2-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -1019,11 +1019,14 @@ static int brcmnand_hamming_ooblayout_fr
+ if (!section) {
+ /*
+ * Small-page NAND use byte 6 for BBI while large-page
+- * NAND use byte 0.
++ * NAND use bytes 0 and 1.
+ */
+- if (cfg->page_size > 512)
+- oobregion->offset++;
+- oobregion->length--;
++ if (cfg->page_size > 512) {
++ oobregion->offset += 2;
++ oobregion->length -= 2;
++ } else {
++ oobregion->length--;
++ }
+ }
+ }
+
--- /dev/null
+From d00358d7a1c50718232799e1ee10955bcd73795a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Tue, 12 May 2020 09:57:33 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: improve hamming oob layout
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The current code generates 8 oob sections:
+S1 1-5
+ECC 6-8
+S2 9-15
+S3 16-21
+ECC 22-24
+S4 25-31
+S5 32-37
+ECC 38-40
+S6 41-47
+S7 48-53
+ECC 54-56
+S8 57-63
+
+Change it by merging continuous sections:
+S1 1-5
+ECC 6-8
+S2 9-21
+ECC 22-24
+S3 25-37
+ECC 38-40
+S4 41-53
+ECC 54-56
+S5 57-63
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200512075733.745374-3-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 35 +++++++++++-------------
+ 1 file changed, 16 insertions(+), 19 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -1003,33 +1003,30 @@ static int brcmnand_hamming_ooblayout_fr
+ struct brcmnand_cfg *cfg = &host->hwcfg;
+ int sas = cfg->spare_area_size << cfg->sector_size_1k;
+ int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
++ u32 next;
+
+- if (section >= sectors * 2)
++ if (section > sectors)
+ return -ERANGE;
+
+- oobregion->offset = (section / 2) * sas;
++ next = (section * sas);
++ if (section < sectors)
++ next += 6;
+
+- if (section & 1) {
+- oobregion->offset += 9;
+- oobregion->length = 7;
++ if (section) {
++ oobregion->offset = ((section - 1) * sas) + 9;
+ } else {
+- oobregion->length = 6;
+-
+- /* First sector of each page may have BBI */
+- if (!section) {
+- /*
+- * Small-page NAND use byte 6 for BBI while large-page
+- * NAND use bytes 0 and 1.
+- */
+- if (cfg->page_size > 512) {
+- oobregion->offset += 2;
+- oobregion->length -= 2;
+- } else {
+- oobregion->length--;
+- }
++ if (cfg->page_size > 512) {
++ /* Large page NAND uses first 2 bytes for BBI */
++ oobregion->offset = 2;
++ } else {
++ /* Small page NAND uses last byte before ECC for BBI */
++ oobregion->offset = 0;
++ next--;
+ }
+ }
+
++ oobregion->length = next - oobregion->offset;
++
+ return 0;
+ }
+
--- /dev/null
+From dcb351c03f2fa6a599de1061b174167e03ee312b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Tue, 12 May 2020 10:24:51 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: correctly verify erased pages
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The current code checks that the whole OOB area is erased.
+This is a problem when JFFS2 cleanmarkers are added to the OOB, since it will
+fail due to the usable OOB bytes not being 0xff.
+Correct this by only checking that data and ECC bytes aren't 0xff.
+
+Fixes: 02b88eea9f9c ("mtd: brcmnand: Add check for erased page bitflips")
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200512082451.771212-1-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 19 +++++++++++--------
+ 1 file changed, 11 insertions(+), 8 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -1787,28 +1787,31 @@ static int brcmnand_read_by_pio(struct m
+ static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
+ struct nand_chip *chip, void *buf, u64 addr)
+ {
+- int i, sas;
+- void *oob = chip->oob_poi;
++ struct mtd_oob_region ecc;
++ int i;
+ int bitflips = 0;
+ int page = addr >> chip->page_shift;
+ int ret;
++ void *ecc_bytes;
+ void *ecc_chunk;
+
+ if (!buf)
+ buf = nand_get_data_buf(chip);
+
+- sas = mtd->oobsize / chip->ecc.steps;
+-
+ /* read without ecc for verification */
+ ret = chip->ecc.read_page_raw(chip, buf, true, page);
+ if (ret)
+ return ret;
+
+- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
++ for (i = 0; i < chip->ecc.steps; i++) {
+ ecc_chunk = buf + chip->ecc.size * i;
+- ret = nand_check_erased_ecc_chunk(ecc_chunk,
+- chip->ecc.size,
+- oob, sas, NULL, 0,
++
++ mtd_ooblayout_ecc(mtd, i, &ecc);
++ ecc_bytes = chip->oob_poi + ecc.offset;
++
++ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
++ ecc_bytes, ecc.length,
++ NULL, 0,
+ chip->ecc.strength);
+ if (ret < 0)
+ return ret;
--- /dev/null
+From 4fd639092b17d4252368b6009573339aeab5c7bd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Fri, 22 May 2020 14:15:20 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: rename v4 registers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These registers are also used on v3.3.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-2-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -269,8 +269,8 @@ enum brcmnand_reg {
+ BRCMNAND_FC_BASE,
+ };
+
+-/* BRCMNAND v4.0 */
+-static const u16 brcmnand_regs_v40[] = {
++/* BRCMNAND v3.3-v4.0 */
++static const u16 brcmnand_regs_v33[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
+@@ -522,8 +522,8 @@ static int brcmnand_revision_init(struct
+ ctrl->reg_offsets = brcmnand_regs_v60;
+ else if (ctrl->nand_version >= 0x0500)
+ ctrl->reg_offsets = brcmnand_regs_v50;
+- else if (ctrl->nand_version >= 0x0400)
+- ctrl->reg_offsets = brcmnand_regs_v40;
++ else if (ctrl->nand_version >= 0x0303)
++ ctrl->reg_offsets = brcmnand_regs_v33;
+
+ /* Chip-select stride */
+ if (ctrl->nand_version >= 0x0701)
--- /dev/null
+From 3d3fb3c5be9ce07fa85d8f67fb3922e4613b955b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Fri, 22 May 2020 14:15:21 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: fix CS0 layout
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Only v3.3-v5.0 have a different CS0 layout.
+Controllers before v3.3 use the same layout for every CS.
+
+Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-3-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -537,8 +537,9 @@ static int brcmnand_revision_init(struct
+ } else {
+ ctrl->cs_offsets = brcmnand_cs_offsets;
+
+- /* v5.0 and earlier has a different CS0 offset layout */
+- if (ctrl->nand_version <= 0x0500)
++ /* v3.3-5.0 have a different CS0 offset layout */
++ if (ctrl->nand_version >= 0x0303 &&
++ ctrl->nand_version <= 0x0500)
+ ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
+ }
+
--- /dev/null
+From eeeac9cbc4ca5b8c245972f3a765d1cb5b7ef038 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Fri, 22 May 2020 14:15:22 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: rename page sizes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Current pages sizes apply to controllers after v3.4
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-4-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -502,7 +502,7 @@ static int brcmnand_revision_init(struct
+ {
+ static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
+ static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
+- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
++ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
+
+ ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
+
+@@ -549,7 +549,7 @@ static int brcmnand_revision_init(struct
+ ctrl->max_page_size = 16 * 1024;
+ ctrl->max_block_size = 2 * 1024 * 1024;
+ } else {
+- ctrl->page_sizes = page_sizes;
++ ctrl->page_sizes = page_sizes_v3_4;
+ if (ctrl->nand_version >= 0x0600)
+ ctrl->block_sizes = block_sizes_v6;
+ else
--- /dev/null
+From 7e7c7df5d50fe06469be106967fc5b5d62be8868 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Fri, 22 May 2020 14:15:24 +0200
+Subject: [PATCH] mtd: rawnand: brcmnand: support v2.1-v2.2 controllers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2.1: tested on Netgear DGND3700v1 (BCM6368)
+v2.2: tested on Netgear DGND3700v2 (BCM6362)
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20200522121524.4161539-6-noltari@gmail.com
+---
+ drivers/mtd/nand/raw/brcmnand/brcmnand.c | 85 +++++++++++++++++++++---
+ 1 file changed, 76 insertions(+), 9 deletions(-)
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -196,6 +196,7 @@ struct brcmnand_controller {
+ const unsigned int *block_sizes;
+ unsigned int max_page_size;
+ const unsigned int *page_sizes;
++ unsigned int page_size_shift;
+ unsigned int max_oob;
+ u32 features;
+
+@@ -269,6 +270,36 @@ enum brcmnand_reg {
+ BRCMNAND_FC_BASE,
+ };
+
++/* BRCMNAND v2.1-v2.2 */
++static const u16 brcmnand_regs_v21[] = {
++ [BRCMNAND_CMD_START] = 0x04,
++ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
++ [BRCMNAND_CMD_ADDRESS] = 0x0c,
++ [BRCMNAND_INTFC_STATUS] = 0x5c,
++ [BRCMNAND_CS_SELECT] = 0x14,
++ [BRCMNAND_CS_XOR] = 0x18,
++ [BRCMNAND_LL_OP] = 0,
++ [BRCMNAND_CS0_BASE] = 0x40,
++ [BRCMNAND_CS1_BASE] = 0,
++ [BRCMNAND_CORR_THRESHOLD] = 0,
++ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
++ [BRCMNAND_UNCORR_COUNT] = 0,
++ [BRCMNAND_CORR_COUNT] = 0,
++ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
++ [BRCMNAND_CORR_ADDR] = 0x64,
++ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
++ [BRCMNAND_UNCORR_ADDR] = 0x6c,
++ [BRCMNAND_SEMAPHORE] = 0x50,
++ [BRCMNAND_ID] = 0x54,
++ [BRCMNAND_ID_EXT] = 0,
++ [BRCMNAND_LL_RDATA] = 0,
++ [BRCMNAND_OOB_READ_BASE] = 0x20,
++ [BRCMNAND_OOB_READ_10_BASE] = 0,
++ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
++ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
++ [BRCMNAND_FC_BASE] = 0x200,
++};
++
+ /* BRCMNAND v3.3-v4.0 */
+ static const u16 brcmnand_regs_v33[] = {
+ [BRCMNAND_CMD_START] = 0x04,
+@@ -467,6 +498,9 @@ enum {
+ CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
+ CFG_DEVICE_SIZE_SHIFT = 24,
+
++ /* Only for v2.1 */
++ CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
++
+ /* Only for pre-v7.1 (with no CFG_EXT register) */
+ CFG_PAGE_SIZE_SHIFT = 20,
+ CFG_BLK_SIZE_SHIFT = 28,
+@@ -502,12 +536,16 @@ static int brcmnand_revision_init(struct
+ {
+ static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
+ static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
++ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
++ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
++ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
++ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
+
+ ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
+
+- /* Only support v4.0+? */
+- if (ctrl->nand_version < 0x0400) {
++ /* Only support v2.1+ */
++ if (ctrl->nand_version < 0x0201) {
+ dev_err(ctrl->dev, "version %#x not supported\n",
+ ctrl->nand_version);
+ return -ENODEV;
+@@ -524,6 +562,8 @@ static int brcmnand_revision_init(struct
+ ctrl->reg_offsets = brcmnand_regs_v50;
+ else if (ctrl->nand_version >= 0x0303)
+ ctrl->reg_offsets = brcmnand_regs_v33;
++ else if (ctrl->nand_version >= 0x0201)
++ ctrl->reg_offsets = brcmnand_regs_v21;
+
+ /* Chip-select stride */
+ if (ctrl->nand_version >= 0x0701)
+@@ -549,14 +589,32 @@ static int brcmnand_revision_init(struct
+ ctrl->max_page_size = 16 * 1024;
+ ctrl->max_block_size = 2 * 1024 * 1024;
+ } else {
+- ctrl->page_sizes = page_sizes_v3_4;
++ if (ctrl->nand_version >= 0x0304)
++ ctrl->page_sizes = page_sizes_v3_4;
++ else if (ctrl->nand_version >= 0x0202)
++ ctrl->page_sizes = page_sizes_v2_2;
++ else
++ ctrl->page_sizes = page_sizes_v2_1;
++
++ if (ctrl->nand_version >= 0x0202)
++ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
++ else
++ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
++
+ if (ctrl->nand_version >= 0x0600)
+ ctrl->block_sizes = block_sizes_v6;
+- else
++ else if (ctrl->nand_version >= 0x0400)
+ ctrl->block_sizes = block_sizes_v4;
++ else if (ctrl->nand_version >= 0x0202)
++ ctrl->block_sizes = block_sizes_v2_2;
++ else
++ ctrl->block_sizes = block_sizes_v2_1;
+
+ if (ctrl->nand_version < 0x0400) {
+- ctrl->max_page_size = 4096;
++ if (ctrl->nand_version < 0x0202)
++ ctrl->max_page_size = 2048;
++ else
++ ctrl->max_page_size = 4096;
+ ctrl->max_block_size = 512 * 1024;
+ }
+ }
+@@ -724,6 +782,9 @@ static void brcmnand_wr_corr_thresh(stru
+ enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
+ int cs = host->cs;
+
++ if (!ctrl->reg_offsets[reg])
++ return;
++
+ if (ctrl->nand_version == 0x0702)
+ bits = 7;
+ else if (ctrl->nand_version >= 0x0600)
+@@ -782,8 +843,10 @@ static inline u32 brcmnand_spare_area_ma
+ return GENMASK(7, 0);
+ else if (ctrl->nand_version >= 0x0600)
+ return GENMASK(6, 0);
+- else
++ else if (ctrl->nand_version >= 0x0303)
+ return GENMASK(5, 0);
++ else
++ return GENMASK(4, 0);
+ }
+
+ #define NAND_ACC_CONTROL_ECC_SHIFT 16
+@@ -2146,7 +2209,7 @@ static int brcmnand_set_cfg(struct brcmn
+ (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
+ (device_size << CFG_DEVICE_SIZE_SHIFT);
+ if (cfg_offs == cfg_ext_offs) {
+- tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
++ tmp |= (page_size << ctrl->page_size_shift) |
+ (block_size << CFG_BLK_SIZE_SHIFT);
+ nand_writereg(ctrl, cfg_offs, tmp);
+ } else {
+@@ -2158,9 +2221,11 @@ static int brcmnand_set_cfg(struct brcmn
+
+ tmp = nand_readreg(ctrl, acc_control_offs);
+ tmp &= ~brcmnand_ecc_level_mask(ctrl);
+- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
+ tmp &= ~brcmnand_spare_area_mask(ctrl);
+- tmp |= cfg->spare_area_size;
++ if (ctrl->nand_version >= 0x0302) {
++ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
++ tmp |= cfg->spare_area_size;
++ }
+ nand_writereg(ctrl, acc_control_offs, tmp);
+
+ brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
+@@ -2524,6 +2589,8 @@ const struct dev_pm_ops brcmnand_pm_ops
+ EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
+
+ static const struct of_device_id brcmnand_of_match[] = {
++ { .compatible = "brcm,brcmnand-v2.1" },
++ { .compatible = "brcm,brcmnand-v2.2" },
+ { .compatible = "brcm,brcmnand-v4.0" },
+ { .compatible = "brcm,brcmnand-v5.0" },
+ { .compatible = "brcm,brcmnand-v6.0" },
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -1787,28 +1787,31 @@ static int brcmnand_read_by_pio(struct m
- static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
- struct nand_chip *chip, void *buf, u64 addr)
- {
-- int i, sas;
-- void *oob = chip->oob_poi;
-+ struct mtd_oob_region ecc;
-+ int i;
- int bitflips = 0;
- int page = addr >> chip->page_shift;
- int ret;
-+ void *ecc_bytes;
- void *ecc_chunk;
-
- if (!buf)
- buf = nand_get_data_buf(chip);
-
-- sas = mtd->oobsize / chip->ecc.steps;
--
- /* read without ecc for verification */
- ret = chip->ecc.read_page_raw(chip, buf, true, page);
- if (ret)
- return ret;
-
-- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
-+ for (i = 0; i < chip->ecc.steps; i++) {
- ecc_chunk = buf + chip->ecc.size * i;
-- ret = nand_check_erased_ecc_chunk(ecc_chunk,
-- chip->ecc.size,
-- oob, sas, NULL, 0,
-+
-+ mtd_ooblayout_ecc(mtd, i, &ecc);
-+ ecc_bytes = chip->oob_poi + ecc.offset;
-+
-+ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
-+ ecc_bytes, ecc.length,
-+ NULL, 0,
- chip->ecc.strength);
- if (ret < 0)
- return ret;
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -1019,11 +1019,14 @@ static int brcmnand_hamming_ooblayout_fr
- if (!section) {
- /*
- * Small-page NAND use byte 6 for BBI while large-page
-- * NAND use byte 0.
-+ * NAND use bytes 0 and 1.
- */
-- if (cfg->page_size > 512)
-- oobregion->offset++;
-- oobregion->length--;
-+ if (cfg->page_size > 512) {
-+ oobregion->offset += 2;
-+ oobregion->length -= 2;
-+ } else {
-+ oobregion->length--;
-+ }
- }
- }
-
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -1003,33 +1003,30 @@ static int brcmnand_hamming_ooblayout_fr
- struct brcmnand_cfg *cfg = &host->hwcfg;
- int sas = cfg->spare_area_size << cfg->sector_size_1k;
- int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
-+ u32 next;
-
-- if (section >= sectors * 2)
-+ if (section > sectors)
- return -ERANGE;
-
-- oobregion->offset = (section / 2) * sas;
-+ next = (section * sas);
-+ if (section < sectors)
-+ next += 6;
-
-- if (section & 1) {
-- oobregion->offset += 9;
-- oobregion->length = 7;
-+ if (section) {
-+ oobregion->offset = ((section - 1) * sas) + 9;
- } else {
-- oobregion->length = 6;
--
-- /* First sector of each page may have BBI */
-- if (!section) {
-- /*
-- * Small-page NAND use byte 6 for BBI while large-page
-- * NAND use bytes 0 and 1.
-- */
-- if (cfg->page_size > 512) {
-- oobregion->offset += 2;
-- oobregion->length -= 2;
-- } else {
-- oobregion->length--;
-- }
-+ if (cfg->page_size > 512) {
-+ /* Large page NAND uses first 2 bytes for BBI */
-+ oobregion->offset = 2;
-+ } else {
-+ /* Small page NAND uses last byte before ECC for BBI */
-+ oobregion->offset = 0;
-+ next--;
- }
- }
-
-+ oobregion->length = next - oobregion->offset;
-+
- return 0;
- }
-
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -269,8 +269,8 @@ enum brcmnand_reg {
- BRCMNAND_FC_BASE,
- };
-
--/* BRCMNAND v4.0 */
--static const u16 brcmnand_regs_v40[] = {
-+/* BRCMNAND v3.3-v4.0 */
-+static const u16 brcmnand_regs_v33[] = {
- [BRCMNAND_CMD_START] = 0x04,
- [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
- [BRCMNAND_CMD_ADDRESS] = 0x0c,
-@@ -522,8 +522,8 @@ static int brcmnand_revision_init(struct
- ctrl->reg_offsets = brcmnand_regs_v60;
- else if (ctrl->nand_version >= 0x0500)
- ctrl->reg_offsets = brcmnand_regs_v50;
-- else if (ctrl->nand_version >= 0x0400)
-- ctrl->reg_offsets = brcmnand_regs_v40;
-+ else if (ctrl->nand_version >= 0x0303)
-+ ctrl->reg_offsets = brcmnand_regs_v33;
-
- /* Chip-select stride */
- if (ctrl->nand_version >= 0x0701)
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -537,8 +537,9 @@ static int brcmnand_revision_init(struct
- } else {
- ctrl->cs_offsets = brcmnand_cs_offsets;
-
-- /* v5.0 and earlier has a different CS0 offset layout */
-- if (ctrl->nand_version <= 0x0500)
-+ /* v3.3-5.0 have a different CS0 offset layout */
-+ if (ctrl->nand_version >= 0x0303 &&
-+ ctrl->nand_version <= 0x0500)
- ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
- }
-
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -502,7 +502,7 @@ static int brcmnand_revision_init(struct
- {
- static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
- static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
-- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
-+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
-
- ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
-
-@@ -549,7 +549,7 @@ static int brcmnand_revision_init(struct
- ctrl->max_page_size = 16 * 1024;
- ctrl->max_block_size = 2 * 1024 * 1024;
- } else {
-- ctrl->page_sizes = page_sizes;
-+ ctrl->page_sizes = page_sizes_v3_4;
- if (ctrl->nand_version >= 0x0600)
- ctrl->block_sizes = block_sizes_v6;
- else
+++ /dev/null
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -196,6 +196,7 @@ struct brcmnand_controller {
- const unsigned int *block_sizes;
- unsigned int max_page_size;
- const unsigned int *page_sizes;
-+ unsigned int page_size_shift;
- unsigned int max_oob;
- u32 features;
-
-@@ -269,6 +270,36 @@ enum brcmnand_reg {
- BRCMNAND_FC_BASE,
- };
-
-+/* BRCMNAND v2.1-v2.2 */
-+static const u16 brcmnand_regs_v21[] = {
-+ [BRCMNAND_CMD_START] = 0x04,
-+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
-+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
-+ [BRCMNAND_INTFC_STATUS] = 0x5c,
-+ [BRCMNAND_CS_SELECT] = 0x14,
-+ [BRCMNAND_CS_XOR] = 0x18,
-+ [BRCMNAND_LL_OP] = 0,
-+ [BRCMNAND_CS0_BASE] = 0x40,
-+ [BRCMNAND_CS1_BASE] = 0,
-+ [BRCMNAND_CORR_THRESHOLD] = 0,
-+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
-+ [BRCMNAND_UNCORR_COUNT] = 0,
-+ [BRCMNAND_CORR_COUNT] = 0,
-+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
-+ [BRCMNAND_CORR_ADDR] = 0x64,
-+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
-+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
-+ [BRCMNAND_SEMAPHORE] = 0x50,
-+ [BRCMNAND_ID] = 0x54,
-+ [BRCMNAND_ID_EXT] = 0,
-+ [BRCMNAND_LL_RDATA] = 0,
-+ [BRCMNAND_OOB_READ_BASE] = 0x20,
-+ [BRCMNAND_OOB_READ_10_BASE] = 0,
-+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
-+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
-+ [BRCMNAND_FC_BASE] = 0x200,
-+};
-+
- /* BRCMNAND v3.3-v4.0 */
- static const u16 brcmnand_regs_v33[] = {
- [BRCMNAND_CMD_START] = 0x04,
-@@ -467,6 +498,9 @@ enum {
- CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
- CFG_DEVICE_SIZE_SHIFT = 24,
-
-+ /* Only for v2.1 */
-+ CFG_PAGE_SIZE_SHIFT_v2_1 = 30,
-+
- /* Only for pre-v7.1 (with no CFG_EXT register) */
- CFG_PAGE_SIZE_SHIFT = 20,
- CFG_BLK_SIZE_SHIFT = 28,
-@@ -502,12 +536,16 @@ static int brcmnand_revision_init(struct
- {
- static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
- static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
-+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
-+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
- static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
-+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
-+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
-
- ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
-
-- /* Only support v4.0+? */
-- if (ctrl->nand_version < 0x0400) {
-+ /* Only support v2.1+ */
-+ if (ctrl->nand_version < 0x0201) {
- dev_err(ctrl->dev, "version %#x not supported\n",
- ctrl->nand_version);
- return -ENODEV;
-@@ -524,6 +562,8 @@ static int brcmnand_revision_init(struct
- ctrl->reg_offsets = brcmnand_regs_v50;
- else if (ctrl->nand_version >= 0x0303)
- ctrl->reg_offsets = brcmnand_regs_v33;
-+ else if (ctrl->nand_version >= 0x0201)
-+ ctrl->reg_offsets = brcmnand_regs_v21;
-
- /* Chip-select stride */
- if (ctrl->nand_version >= 0x0701)
-@@ -549,14 +589,32 @@ static int brcmnand_revision_init(struct
- ctrl->max_page_size = 16 * 1024;
- ctrl->max_block_size = 2 * 1024 * 1024;
- } else {
-- ctrl->page_sizes = page_sizes_v3_4;
-+ if (ctrl->nand_version >= 0x0304)
-+ ctrl->page_sizes = page_sizes_v3_4;
-+ else if (ctrl->nand_version >= 0x0202)
-+ ctrl->page_sizes = page_sizes_v2_2;
-+ else
-+ ctrl->page_sizes = page_sizes_v2_1;
-+
-+ if (ctrl->nand_version >= 0x0202)
-+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
-+ else
-+ ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
-+
- if (ctrl->nand_version >= 0x0600)
- ctrl->block_sizes = block_sizes_v6;
-- else
-+ else if (ctrl->nand_version >= 0x0400)
- ctrl->block_sizes = block_sizes_v4;
-+ else if (ctrl->nand_version >= 0x0202)
-+ ctrl->block_sizes = block_sizes_v2_2;
-+ else
-+ ctrl->block_sizes = block_sizes_v2_1;
-
- if (ctrl->nand_version < 0x0400) {
-- ctrl->max_page_size = 4096;
-+ if (ctrl->nand_version < 0x0202)
-+ ctrl->max_page_size = 2048;
-+ else
-+ ctrl->max_page_size = 4096;
- ctrl->max_block_size = 512 * 1024;
- }
- }
-@@ -724,6 +782,9 @@ static void brcmnand_wr_corr_thresh(stru
- enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
- int cs = host->cs;
-
-+ if (!ctrl->reg_offsets[reg])
-+ return;
-+
- if (ctrl->nand_version == 0x0702)
- bits = 7;
- else if (ctrl->nand_version >= 0x0600)
-@@ -782,8 +843,10 @@ static inline u32 brcmnand_spare_area_ma
- return GENMASK(7, 0);
- else if (ctrl->nand_version >= 0x0600)
- return GENMASK(6, 0);
-- else
-+ else if (ctrl->nand_version >= 0x0303)
- return GENMASK(5, 0);
-+ else
-+ return GENMASK(4, 0);
- }
-
- #define NAND_ACC_CONTROL_ECC_SHIFT 16
-@@ -2146,7 +2209,7 @@ static int brcmnand_set_cfg(struct brcmn
- (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
- (device_size << CFG_DEVICE_SIZE_SHIFT);
- if (cfg_offs == cfg_ext_offs) {
-- tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
-+ tmp |= (page_size << ctrl->page_size_shift) |
- (block_size << CFG_BLK_SIZE_SHIFT);
- nand_writereg(ctrl, cfg_offs, tmp);
- } else {
-@@ -2158,9 +2221,11 @@ static int brcmnand_set_cfg(struct brcmn
-
- tmp = nand_readreg(ctrl, acc_control_offs);
- tmp &= ~brcmnand_ecc_level_mask(ctrl);
-- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
- tmp &= ~brcmnand_spare_area_mask(ctrl);
-- tmp |= cfg->spare_area_size;
-+ if (ctrl->nand_version >= 0x0302) {
-+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
-+ tmp |= cfg->spare_area_size;
-+ }
- nand_writereg(ctrl, acc_control_offs, tmp);
-
- brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
-@@ -2524,6 +2589,8 @@ const struct dev_pm_ops brcmnand_pm_ops
- EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
-
- static const struct of_device_id brcmnand_of_match[] = {
-+ { .compatible = "brcm,brcmnand-v2.1" },
-+ { .compatible = "brcm,brcmnand-v2.2" },
- { .compatible = "brcm,brcmnand-v4.0" },
- { .compatible = "brcm,brcmnand-v5.0" },
- { .compatible = "brcm,brcmnand-v6.0" },
projects / openwrt / staging / neocturne.git / commitdiff