ipq806x: fix missing clk and reset

Patch 0030 wrongly disables gsbi1 instead of gsbi4.
Fix the wrong patch and also include other fix from the original qsdk source.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>

diff --git a/target/linux/ipq806x/patches-5.10/0030-clk-Disable-i2c-device-on-gsbi4.patch b/target/linux/ipq806x/patches-5.10/0030-clk-Disable-i2c-device-on-gsbi4.patch
deleted file mode 100644 (file)
index a5fb714..0000000
--- a/target/linux/ipq806x/patches-5.10/0030-clk-Disable-i2c-device-on-gsbi4.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 08:16:10 +0100
-Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4
-
-This patch was not annotated and comes from the v4.4 tree.
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq806x.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -365,7 +365,7 @@ static struct clk_rcg gsbi1_uart_src = {
-                       .parent_names = gcc_pxo_pll8,
-                       .num_parents = 2,
-                       .ops = &clk_rcg_ops,
--                      .flags = CLK_SET_PARENT_GATE,
-+                      .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
-               },
-       },
- };
-@@ -383,7 +383,7 @@ static struct clk_branch gsbi1_uart_clk
-                       },
-                       .num_parents = 1,
-                       .ops = &clk_branch_ops,
--                      .flags = CLK_SET_RATE_PARENT,
-+                      .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-               },
-       },
- };
-@@ -961,6 +961,7 @@ static struct clk_branch gsbi1_h_clk = {
-               .hw.init = &(struct clk_init_data){
-                       .name = "gsbi1_h_clk",
-                       .ops = &clk_branch_ops,
-+                      .flags = CLK_IGNORE_UNUSED,
-               },
-       },
- };

diff --git a/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch
new file mode 100644 (file)
index 0000000..a09453e
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch
@@ -0,0 +1,120 @@
+From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 16:52:56 +0100
+Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
+
+Some flag are missing from the original code.
+These clk can't be set using the protected-clock proprities as they
+cause the malfunction of the serial interface.
+These clks are needed for the rpm interface to work proprely or the
+cpu regulators starts to fail as soon as they are disabled by the
+kernel.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
+index d6b7adb4be38..fbb8644c4a43 100644
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
+               .parent_names = (const char *[]){ "pxo" },
+               .num_parents = 1,
+               .ops = &clk_pll_ops,
++              .flags = CLK_IS_CRITICAL,
+       },
+ };
+ 
+@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
+                       .parent_names = gcc_pxo_pll8,
+                       .num_parents = 2,
+                       .ops = &clk_rcg_ops,
+-                      .flags = CLK_SET_PARENT_GATE,
++                      .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk = {
+                       .parent_names = (const char *[]){ "gsbi4_qup_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+-                      .flags = CLK_SET_RATE_PARENT,
++                      .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
+                       .parent_names = gcc_pxo_pll8,
+                       .num_parents = 2,
+                       .ops = &clk_rcg_ops,
+-                      .flags = CLK_SET_PARENT_GATE,
++                      .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk = {
+                       .parent_names = (const char *[]){ "gsbi7_qup_src" },
+                       .num_parents = 1,
+                       .ops = &clk_branch_ops,
+-                      .flags = CLK_SET_RATE_PARENT,
++                      .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
+               .hw.init = &(struct clk_init_data){
+                       .name = "gsbi4_h_clk",
+                       .ops = &clk_branch_ops,
++                      .flags = CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -1293,6 +1295,7 @@ static struct clk_rcg sdc1_src = {
+                       .parent_names = gcc_pxo_pll8,
+                       .num_parents = 2,
+                       .ops = &clk_rcg_ops,
++                      .flags = CLK_SET_RATE_GATE,
+               },
+       }
+ };
+@@ -1341,6 +1344,7 @@ static struct clk_rcg sdc3_src = {
+                       .parent_names = gcc_pxo_pll8,
+                       .num_parents = 2,
+                       .ops = &clk_rcg_ops,
++                      .flags = CLK_SET_RATE_GATE,
+               },
+       }
+ };
+@@ -1424,6 +1428,7 @@ static struct clk_rcg tsif_ref_src = {
+                       .parent_names = gcc_pxo_pll8,
+                       .num_parents = 2,
+                       .ops = &clk_rcg_ops,
++                      .flags = CLK_SET_RATE_GATE,
+               },
+       }
+ };
+@@ -2694,7 +2699,8 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
+                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+                       .num_parents = 5,
+                       .ops = &clk_dyn_rcg_ops,
+-                      .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
++                      .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
++                               CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+@@ -2747,7 +2753,8 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
+                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+                       .num_parents = 5,
+                       .ops = &clk_dyn_rcg_ops,
+-                      .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
++                      .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
++                               CLK_IGNORE_UNUSED,
+               },
+       },
+ };
+-- 
+2.29.2
+

diff --git a/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch b/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch
new file mode 100644 (file)
index 0000000..877f751
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch
@@ -0,0 +1,66 @@
+From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:00:07 +0100
+Subject: [PATCH 2/4] ipq806x: lcc: add missing reset
+
+Add missing reset for ipq806x lcc clk
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/lcc-ipq806x.c               | 8 ++++++++
+ include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 +
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
+index 1a2be4aeb31d..ee48642bb872 100644
+--- a/drivers/clk/qcom/lcc-ipq806x.c
++++ b/drivers/clk/qcom/lcc-ipq806x.c
+@@ -12,6 +12,7 @@
+ #include <linux/of_device.h>
+ #include <linux/clk-provider.h>
+ #include <linux/regmap.h>
++#include <linux/reset-controller.h>
+ 
+ #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
+ 
+@@ -22,6 +23,7 @@
+ #include "clk-branch.h"
+ #include "clk-regmap-divider.h"
+ #include "clk-regmap-mux.h"
++#include "reset.h"
+ 
+ static struct clk_pll pll4 = {
+       .l_reg = 0x4,
+@@ -39,6 +41,10 @@ static struct clk_pll pll4 = {
+       },
+ };
+ 
++static const struct qcom_reset_map lcc_ipq806x_resets[] = {
++      [LCC_PCM_RESET] = { 0x54, 13 },
++};
++
+ static const struct pll_config pll4_config = {
+       .l = 0xf,
+       .m = 0x91,
+@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq806x_desc = {
+       .config = &lcc_ipq806x_regmap_config,
+       .clks = lcc_ipq806x_clks,
+       .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
++      .resets = lcc_ipq806x_resets,
++      .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
+ };
+ 
+ static const struct of_device_id lcc_ipq806x_match_table[] = {
+diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
+index 25b92bbf0ab4..73318b1ce29e 100644
+--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h
++++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
+@@ -19,4 +19,5 @@
+ #define SPDIF_CLK                     10
+ #define AHBIX_CLK                     11
+ 
++#define LCC_PCM_RESET                 0
+ #endif
+-- 
+2.29.2
+

diff --git a/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch
new file mode 100644 (file)
index 0000000..777c54c
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch
@@ -0,0 +1,62 @@
+From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:08:16 +0100
+Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable
+
+Add missing enable disable mux function. Add extra check to
+div2_round_rate.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
+index 59f1af415b58..ba796b621669 100644
+--- a/drivers/clk/qcom/clk-krait.c
++++ b/drivers/clk/qcom/clk-krait.c
+@@ -68,7 +68,25 @@ static u8 krait_mux_get_parent(struct clk_hw *hw)
+       return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
+ }
+ 
++static int krait_mux_enable(struct clk_hw *hw)
++{
++      struct krait_mux_clk *mux = to_krait_mux_clk(hw);
++
++      __krait_mux_set_sel(mux, mux->en_mask);
++
++      return 0;
++}
++
++static void krait_mux_disable(struct clk_hw *hw)
++{
++      struct krait_mux_clk *mux = to_krait_mux_clk(hw);
++
++      __krait_mux_set_sel(mux, mux->safe_sel);
++}
++
+ const struct clk_ops krait_mux_clk_ops = {
++      .enable = krait_mux_enable,
++      .disable = krait_mux_disable,
+       .set_parent = krait_mux_set_parent,
+       .get_parent = krait_mux_get_parent,
+       .determine_rate = __clk_mux_determine_rate_closest,
+@@ -79,8 +97,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+ static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+ {
+-      *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+-      return DIV_ROUND_UP(*parent_rate, 2);
++      struct clk_hw *hw_parent = clk_hw_get_parent(hw);
++
++      if (hw_parent) {
++              *parent_rate = clk_hw_round_rate(hw_parent, rate * 2);
++              return DIV_ROUND_UP(*parent_rate, 2);
++      } else
++              return -1;
+ }
+ 
+ static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
+-- 
+2.29.2
+

diff --git a/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
new file mode 100644 (file)
index 0000000..1231f88
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
@@ -0,0 +1,381 @@
+From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sun, 7 Feb 2021 17:23:38 +0100
+Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
+
+Add missing clk and reset needed for nss additional core and crypto
+engine.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++
+ include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-
+ include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +
+ 3 files changed, 259 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
+index fbb8644c4a43..c36bcdf013d0 100644
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
+ 
+ static struct pll_freq_tbl pll18_freq_tbl[] = {
+       NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
++      NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
+       NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
++      NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
+ };
+ 
+ static struct clk_pll pll18 = {
+@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
+       },
+ };
+ 
++static struct clk_pll pll11 = {
++      .l_reg = 0x3184,
++      .m_reg = 0x3188,
++      .n_reg = 0x318c,
++      .config_reg = 0x3194,
++      .mode_reg = 0x3180,
++      .status_reg = 0x3198,
++      .status_bit = 16,
++      .clkr.hw.init = &(struct clk_init_data){
++              .name = "pll11",
++              .parent_names = (const char *[]){ "pxo" },
++              .num_parents = 1,
++              .ops = &clk_pll_ops,
++      },
++};
++
+ enum {
+       P_PXO,
+       P_PLL8,
+@@ -253,6 +271,7 @@ enum {
+       P_CXO,
+       P_PLL14,
+       P_PLL18,
++      P_PLL11,
+ };
+ 
+ static const struct parent_map gcc_pxo_pll8_map[] = {
+@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
+       "pll18",
+ };
+ 
++static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
++      { P_PXO, 0 },
++      { P_PLL8, 4 },
++      { P_PLL0, 2 },
++      { P_PLL14, 5 },
++      { P_PLL18, 1 },
++      { P_PLL11, 3 },
++};
++
++static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
++      "pxo",
++      "pll8_vote",
++      "pll0_vote",
++      "pll14",
++      "pll18",
++      "pll11"
++};
++
++static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
++      { P_PXO, 0 },
++      { P_PLL3, 6 },
++      { P_PLL0, 2 },
++      { P_PLL14, 5 },
++      { P_PLL18, 1 },
++      { P_PLL11, 3 },
++};
++
++static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
++      "pxo",
++      "pll3",
++      "pll0_vote",
++      "pll14",
++      "pll18",
++      "pll11"
++};
++
+ static struct freq_tbl clk_tbl_gsbi_uart[] = {
+       {  1843200, P_PLL8, 2,  6, 625 },
+       {  3686400, P_PLL8, 2, 12, 625 },
+@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
+       {  20210000, P_PLL8,  1, 1,  19 },
+       {  24000000, P_PLL8,  4, 1,   4 },
+       {  48000000, P_PLL8,  4, 1,   2 },
++      {  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
+       {  64000000, P_PLL8,  3, 1,   2 },
+       {  96000000, P_PLL8,  4, 0,   0 },
+       { 192000000, P_PLL8,  2, 0,   0 },
+@@ -2647,7 +2703,9 @@ static const struct freq_tbl clk_tbl_nss[] = {
+       { 110000000, P_PLL18, 1, 1, 5 },
+       { 275000000, P_PLL18, 2, 0, 0 },
+       { 550000000, P_PLL18, 1, 0, 0 },
++      { 600000000, P_PLL18, 1, 0, 0 },
+       { 733000000, P_PLL18, 1, 0, 0 },
++      { 800000000, P_PLL18, 1, 0, 0 },
+       { }
+ };
+ 
+@@ -2759,6 +2817,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
+       },
+ };
+ 
++static const struct freq_tbl clk_tbl_ce5_core[] = {
++      { 150000000, P_PLL3, 8, 1, 1 },
++      { 213200000, P_PLL11, 5, 1, 1 },
++      { }
++};
++
++static struct clk_dyn_rcg ce5_core_src = {
++      .ns_reg[0] = 0x36C4,
++      .ns_reg[1] = 0x36C8,
++      .bank_reg = 0x36C0,
++      .s[0] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
++      },
++      .s[1] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
++      },
++      .p[0] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .p[1] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .mux_sel_bit = 0,
++      .freq_tbl = clk_tbl_ce5_core,
++      .clkr = {
++              .enable_reg = 0x36C0,
++              .enable_mask = BIT(1),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_core_src",
++                      .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
++                      .num_parents = 6,
++                      .ops = &clk_dyn_rcg_ops,
++              },
++      },
++};
++
++static struct clk_branch ce5_core_clk = {
++      .halt_reg = 0x2FDC,
++      .halt_bit = 5,
++      .hwcg_reg = 0x36CC,
++      .hwcg_bit = 6,
++      .clkr = {
++              .enable_reg = 0x36CC,
++              .enable_mask = BIT(4),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_core_clk",
++                      .parent_names = (const char *[]){
++                              "ce5_core_src",
++                      },
++                      .num_parents = 1,
++                      .ops = &clk_branch_ops,
++                      .flags = CLK_SET_RATE_PARENT,
++              },
++      },
++};
++
++static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
++      { 160000000, P_PLL0, 5, 1, 1 },
++      { 213200000, P_PLL11, 5, 1, 1 },
++      { }
++};
++
++static struct clk_dyn_rcg ce5_a_clk_src = {
++      .ns_reg[0] = 0x3d84,
++      .ns_reg[1] = 0x3d88,
++      .bank_reg = 0x3d80,
++      .s[0] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++      },
++      .s[1] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++      },
++      .p[0] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .p[1] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .mux_sel_bit = 0,
++      .freq_tbl = clk_tbl_ce5_a_clk,
++      .clkr = {
++              .enable_reg = 0x3d80,
++              .enable_mask = BIT(1),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_a_clk_src",
++                      .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
++                      .num_parents = 6,
++                      .ops = &clk_dyn_rcg_ops,
++              },
++      },
++};
++
++static struct clk_branch ce5_a_clk = {
++      .halt_reg = 0x3c20,
++      .halt_bit = 12,
++      .hwcg_reg = 0x3d8c,
++      .hwcg_bit = 6,
++      .clkr = {
++              .enable_reg = 0x3d8c,
++              .enable_mask = BIT(4),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_a_clk",
++                      .parent_names = (const char *[]){
++                              "ce5_a_clk_src",
++                      },
++                      .num_parents = 1,
++                      .ops = &clk_branch_ops,
++                      .flags = CLK_SET_RATE_PARENT,
++              },
++      },
++};
++
++static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
++      { 160000000, P_PLL0, 5, 1, 1 },
++      { 213200000, P_PLL11, 5, 1, 1 },
++      { }
++};
++
++static struct clk_dyn_rcg ce5_h_clk_src = {
++      .ns_reg[0] = 0x3c64,
++      .ns_reg[1] = 0x3c68,
++      .bank_reg = 0x3c60,
++      .s[0] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++      },
++      .s[1] = {
++              .src_sel_shift = 0,
++              .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
++      },
++      .p[0] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .p[1] = {
++              .pre_div_shift = 3,
++              .pre_div_width = 4,
++      },
++      .mux_sel_bit = 0,
++      .freq_tbl = clk_tbl_ce5_h_clk,
++      .clkr = {
++              .enable_reg = 0x3c60,
++              .enable_mask = BIT(1),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_h_clk_src",
++                      .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
++                      .num_parents = 6,
++                      .ops = &clk_dyn_rcg_ops,
++              },
++      },
++};
++
++static struct clk_branch ce5_h_clk = {
++      .halt_reg = 0x3c20,
++      .halt_bit = 11,
++      .hwcg_reg = 0x3c6c,
++      .hwcg_bit = 6,
++      .clkr = {
++              .enable_reg = 0x3c6c,
++              .enable_mask = BIT(4),
++              .hw.init = &(struct clk_init_data){
++                      .name = "ce5_h_clk",
++                      .parent_names = (const char *[]){
++                              "ce5_h_clk_src",
++                      },
++                      .num_parents = 1,
++                      .ops = &clk_branch_ops,
++                      .flags = CLK_SET_RATE_PARENT,
++              },
++      },
++};
++
+ static struct clk_regmap *gcc_ipq806x_clks[] = {
+       [PLL0] = &pll0.clkr,
+       [PLL0_VOTE] = &pll0_vote,
+@@ -2766,6 +3004,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
+       [PLL4_VOTE] = &pll4_vote,
+       [PLL8] = &pll8.clkr,
+       [PLL8_VOTE] = &pll8_vote,
++      [PLL11] = &pll11.clkr,
+       [PLL14] = &pll14.clkr,
+       [PLL14_VOTE] = &pll14_vote,
+       [PLL18] = &pll18.clkr,
+@@ -2880,6 +3119,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
+       [PLL9] = &hfpll0.clkr,
+       [PLL10] = &hfpll1.clkr,
+       [PLL12] = &hfpll_l2.clkr,
++      [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
++      [CE5_A_CLK] = &ce5_a_clk.clkr,
++      [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
++      [CE5_H_CLK] = &ce5_h_clk.clkr,
++      [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
++      [CE5_CORE_CLK] = &ce5_core_clk.clkr,
+ };
+ 
+ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
+@@ -3011,6 +3256,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
+       [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
+       [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
+       [GMAC_AHB_RESET] = { 0x3e24, 0 },
++      [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
++      [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
++      [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
++      [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
++      [CRYPTO_AHB_RESET] = { 0x3e10, 0},
+       [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
+       [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
+       [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
+diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+index 7deec14a6dee..02262d2ac899 100644
+--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+@@ -240,7 +240,7 @@
+ #define PLL14                                 232
+ #define PLL14_VOTE                            233
+ #define PLL18                                 234
+-#define CE5_SRC                                       235
++#define CE5_A_CLK                             235
+ #define CE5_H_CLK                             236
+ #define CE5_CORE_CLK                          237
+ #define CE3_SLEEP_CLK                         238
+@@ -283,5 +283,8 @@
+ #define EBI2_AON_CLK                          281
+ #define NSSTCM_CLK_SRC                                282
+ #define NSSTCM_CLK                            283
++#define CE5_A_CLK_SRC                         285
++#define CE5_H_CLK_SRC                         286
++#define CE5_CORE_CLK_SRC                      287
+ 
+ #endif
+diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+index 26b6f9200620..020c9cf18751 100644
+--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+@@ -163,5 +163,10 @@
+ #define NSS_CAL_PRBS_RST_N_RESET                      154
+ #define NSS_LCKDT_RST_N_RESET                         155
+ #define NSS_SRDS_N_RESET                              156
++#define CRYPTO_ENG1_RESET                             157
++#define CRYPTO_ENG2_RESET                             158
++#define CRYPTO_ENG3_RESET                             159
++#define CRYPTO_ENG4_RESET                             160
++#define CRYPTO_AHB_RESET                              161
+ 
+ #endif
+-- 
+2.29.2
+