clk: qcom: add EBI2 clocks to the MSM8660 GCC

This adds the EBI2 2X and EBI2 clocks to the MSM8660/APQ8060
GCC. This is necessary to enable clocking of the external bus
interface so that peripherals on it can be mounted. These two
clocks are simple gated branch clocks.

In the vendor tree clock-8x60, these clocks have some kind of
dependency, the EBI2 clock has .depends = &ebi2_2x_clk.c,
what this means is undocumented, it doesn't seem like there
is a parent/child relationship, so the solution I chose was to
just have the EBI2 driver get and enable both clocks.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index 6dc55864979c8843e03cb792b57f1af8e64ecdc6..c347a0d44bc8b0bbd108c92992099f3634b82134 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -2290,6 +2290,32 @@ static struct clk_branch sdc5_h_clk = {
        },
 };
 
+static struct clk_branch ebi2_2x_clk = {
+       .halt_reg = 0x2fcc,
+       .halt_bit = 18,
+       .clkr = {
+               .enable_reg = 0x2660,
+               .enable_mask = BIT(4),
+               .hw.init = &(struct clk_init_data){
+                       .name = "ebi2_2x_clk",
+                       .ops = &clk_branch_ops,
+               },
+       },
+};
+
+static struct clk_branch ebi2_clk = {
+       .halt_reg = 0x2fcc,
+       .halt_bit = 19,
+       .clkr = {
+               .enable_reg = 0x2664,
+               .enable_mask = BIT(4),
+               .hw.init = &(struct clk_init_data){
+                       .name = "ebi2_clk",
+                       .ops = &clk_branch_ops,
+               },
+       },
+};
+
 static struct clk_branch adm0_clk = {
        .halt_reg = 0x2fdc,
        .halt_check = BRANCH_HALT_VOTED,
@@ -2533,6 +2559,8 @@ static struct clk_regmap *gcc_msm8660_clks[] = {
        [SDC3_H_CLK] = &sdc3_h_clk.clkr,
        [SDC4_H_CLK] = &sdc4_h_clk.clkr,
        [SDC5_H_CLK] = &sdc5_h_clk.clkr,
+       [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
+       [EBI2_CLK] = &ebi2_clk.clkr,
        [ADM0_CLK] = &adm0_clk.clkr,
        [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
        [ADM1_CLK] = &adm1_clk.clkr,