x86: queensbay: Change PCIe root ports' interrupt routing

So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 873de7be9ddf7f7c565f5ed8f6f0c9e5aee6304c..d27b2d9ec635f1ec6f705fae429cc5b47f816578 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,17 +69,18 @@ void cpu_irq_init(void)
         * Route TunnelCreek PCI device interrupt pin to PIRQ
         *
         * Since PCIe downstream ports received INTx are routed to PIRQ
-        * A/B/C/D directly and not configurable, we route internal PCI
-        * device's INTx to PIRQ E/F/G/H.
+        * A/B/C/D directly and not configurable, we have to route PCIe
+        * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+        * on TunneCreek, route them to PIRQ E/F/G/H.
         */
        writew(PIRQE, &rcba->d02ir);
        writew(PIRQF, &rcba->d03ir);
        writew(PIRQG, &rcba->d27ir);
        writew(PIRQH, &rcba->d31ir);
-       writew(PIRQE, &rcba->d23ir);
-       writew(PIRQF, &rcba->d24ir);
-       writew(PIRQG, &rcba->d25ir);
-       writew(PIRQH, &rcba->d26ir);
+       writew(PIRQA, &rcba->d23ir);
+       writew(PIRQB, &rcba->d24ir);
+       writew(PIRQC, &rcba->d25ir);
+       writew(PIRQD, &rcba->d26ir);
 }
 
 int arch_misc_init(void)

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index b77c65a463728db16d3715a42080f44a2401842b..60da1f544bcd8fb41e34db214d6b1094b31d7d53 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -169,10 +169,22 @@
                                /* TunnelCreek PCI devices */
                                PCI_BDF(0, 2, 0) INTA PIRQE
                                PCI_BDF(0, 3, 0) INTA PIRQF
-                               PCI_BDF(0, 23, 0) INTA PIRQE
-                               PCI_BDF(0, 24, 0) INTA PIRQF
-                               PCI_BDF(0, 25, 0) INTA PIRQG
-                               PCI_BDF(0, 26, 0) INTA PIRQH
+                               PCI_BDF(0, 23, 0) INTA PIRQA
+                               PCI_BDF(0, 23, 0) INTB PIRQB
+                               PCI_BDF(0, 23, 0) INTC PIRQC
+                               PCI_BDF(0, 23, 0) INTD PIRQD
+                               PCI_BDF(0, 24, 0) INTA PIRQB
+                               PCI_BDF(0, 24, 0) INTB PIRQC
+                               PCI_BDF(0, 24, 0) INTC PIRQD
+                               PCI_BDF(0, 24, 0) INTD PIRQA
+                               PCI_BDF(0, 25, 0) INTA PIRQC
+                               PCI_BDF(0, 25, 0) INTB PIRQD
+                               PCI_BDF(0, 25, 0) INTC PIRQA
+                               PCI_BDF(0, 25, 0) INTD PIRQB
+                               PCI_BDF(0, 26, 0) INTA PIRQD
+                               PCI_BDF(0, 26, 0) INTB PIRQA
+                               PCI_BDF(0, 26, 0) INTC PIRQB
+                               PCI_BDF(0, 26, 0) INTD PIRQC
                                PCI_BDF(0, 27, 0) INTA PIRQG
                                /*
                                 * Topcliff PCI devices