*/
static inline int is_usr_def_mapping(u32 format_id)
{
- return ((format_id & 0xF0) == 0x40) ? 1 : 0;
+ return (format_id & 0xF0) == 0x40 ? 1 : 0;
}
/*
CSI2_IRQ_FIFO_OVF)) {
dev_dbg(iss->dev,
"CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
- (csi2_irqstatus &
- CSI2_IRQ_OCP_ERR) ? 1 : 0,
- (csi2_irqstatus &
- CSI2_IRQ_SHORT_PACKET) ? 1 : 0,
- (csi2_irqstatus &
- CSI2_IRQ_ECC_NO_CORRECTION) ? 1 : 0,
- (csi2_irqstatus &
- CSI2_IRQ_COMPLEXIO_ERR) ? 1 : 0,
- (csi2_irqstatus &
- CSI2_IRQ_FIFO_OVF) ? 1 : 0);
+ csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
+ csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
+ csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
+ csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
+ csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
pipe->error = true;
}
return -EINVAL;
}
- ctrl->vp_only_enable =
- (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
+ ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
return 0;
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN) &
~IPIPE_SRC_EN_EN) |
- enable ? IPIPE_SRC_EN_EN : 0,
+ (enable ? IPIPE_SRC_EN_EN : 0),
iss->regs[OMAP4_ISS_MEM_ISP_IPIPE] + IPIPE_SRC_EN);
}
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
~ISIF_SYNCEN_DWEN) |
- enable ? ISIF_SYNCEN_DWEN : 0,
+ (enable ? ISIF_SYNCEN_DWEN : 0),
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
}
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN) &
~ISIF_SYNCEN_SYEN) |
- enable ? ISIF_SYNCEN_SYEN : 0,
+ (enable ? ISIF_SYNCEN_SYEN : 0),
iss->regs[OMAP4_ISS_MEM_ISP_ISIF] + ISIF_SYNCEN);
}
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN) &
~RSZ_SRC_EN_SRC_EN) |
- enable ? RSZ_SRC_EN_SRC_EN : 0,
+ (enable ? RSZ_SRC_EN_SRC_EN : 0),
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_EN);
/* TODO: Enable RSZB */
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN) &
~RSZ_EN_EN) |
- enable ? RSZ_EN_EN : 0,
+ (enable ? RSZ_EN_EN : 0),
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RZA_EN);
}
/* Select RSZ input */
writel((readl(iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0) &
~RSZ_SRC_FMT0_SEL) |
- (resizer->input == RESIZER_INPUT_IPIPEIF) ? RSZ_SRC_FMT0_SEL : 0,
+ (resizer->input == RESIZER_INPUT_IPIPEIF ? RSZ_SRC_FMT0_SEL : 0),
iss->regs[OMAP4_ISS_MEM_ISP_RESIZER] + RSZ_SRC_FMT0);
/* RSZ ignores WEN signal from IPIPE/IPIPEIF */
if (events & (ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR |
ISP5_IRQ_RSZ_FIFO_OVF)) {
dev_dbg(iss->dev, "RSZ Err: FIFO_IN_BLK:%d, FIFO_OVF:%d\n",
- (events &
- ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR) ? 1 : 0,
- (events &
- ISP5_IRQ_RSZ_FIFO_OVF) ? 1 : 0);
+ events & ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR ? 1 : 0,
+ events & ISP5_IRQ_RSZ_FIFO_OVF ? 1 : 0);
pipe->error = true;
}