rockchip: rk3399: enable secure accessing for SRAM
authorXing Zheng <zhengxing@rock-chips.com>
Tue, 14 Feb 2017 10:03:20 +0000 (18:03 +0800)
committerXing Zheng <zhengxing@rock-chips.com>
Fri, 24 Feb 2017 12:07:45 +0000 (20:07 +0800)
Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
plat/rockchip/rk3399/drivers/secure/secure.c
plat/rockchip/rk3399/drivers/secure/secure.h

index f2e9ab03d937990ce809df4aee0c12c36999b820..d3c8cb8a0616dc067342341516be5a28174ec45b 100644 (file)
@@ -163,7 +163,7 @@ void secure_sgrf_init(void)
        mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
                      SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
        mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
-                     SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
+                     SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
 }
 
 void secure_sgrf_ddr_rgn_init(void)
index 6eb2237c4fcfc51f35abb80063ad046be11226ec..12a875c8fd7f22d82dd18cfb376fc8929aef2946 100644 (file)
@@ -62,6 +62,8 @@
 
 #define SGRF_PMUSRAM_S                 BIT(8)
 
+#define SGRF_INTSRAM_S                 BIT(13)
+
 /* ddr region */
 #define SGRF_DDR_RGN_0_16_WMSK         0x0fff  /* DDR RGN 0~16 size mask */