Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
- SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
+ SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
}
void secure_sgrf_ddr_rgn_init(void)
#define SGRF_PMUSRAM_S BIT(8)
+#define SGRF_INTSRAM_S BIT(13)
+
/* ddr region */
#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */