+++ /dev/null
-CONFIG_AHCI_SUNXI=y
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-CONFIG_ARCH_NR_GPIO=288
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_ARM_CPU_SUSPEND is not set
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_NR_BANKS=8
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
-CONFIG_AUDIT_GENERIC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AVERAGE=y
-CONFIG_BCH=y
-CONFIG_BINFMT_MISC=y
-CONFIG_BLK_CGROUP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_BOUNCE=y
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_FREEZER=y
-# CONFIG_CGROUP_PERF is not set
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk rootwait root=/dev/mmcblk0p2"
-CONFIG_CMDLINE_FORCE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACTION=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUSETS=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BLK_CGROUP is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_PL01X is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DIRECT_IO=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_OF=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_SUNXI=y
-# CONFIG_DW_DMAC_CORE is not set
-CONFIG_DYNAMIC_DEBUG=y
-# CONFIG_EEPROM_SUNXI_SID is not set
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_EXPERT is not set
-CONFIG_EXT4_FS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GARP=y
-CONFIG_GENERIC_ACL=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_BPF_JIT=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_MUX=y
-# CONFIG_I2C_MUX_GPIO is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-# CONFIG_I2C_MUX_PCA954x is not set
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_INPUT_MISC is not set
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IPC_NS=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KSM=y
-CONFIG_KTIME_SCALAR=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MEMCG is not set
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-# CONFIG_NEON is not set
-# CONFIG_NETPRIO_CGROUP is not set
-# CONFIG_NET_CLS_CGROUP is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_NS=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_PTP_1588_CLOCK=y
-# CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_RCU_BOOST is not set
-CONFIG_RCU_CPU_STALL_VERBOSE=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REGMAP=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESOURCE_COUNTERS=y
-# CONFIG_RFKILL_REGULATOR is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SCHED_HRTICK=y
-CONFIG_SCSI=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_8250_SYSRQ=y
-CONFIG_SERIO=y
-# CONFIG_SERIO_APBPS2 is not set
-# CONFIG_SERIO_OLPC_APSP is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLUB_DEBUG_ON is not set
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_SUN4I=y
-# CONFIG_SPI_SUN6I is not set
-# CONFIG_STAGING is not set
-# CONFIG_STMMAC_DA is not set
-# CONFIG_STMMAC_DEBUG_FS is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STOP_MACHINE=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_TASK_XACCT=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UID16=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USER_NS is not set
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_XEN is not set
-CONFIG_XFRM_ALGO=y
-CONFIG_XFRM_USER=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-# CONFIG_ZBUD is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-From a968e9dc5983d258a4aa7e496d58c92e9e4cf670 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Sat, 14 Sep 2013 21:37:59 -0300
-Subject: [PATCH] clk: composite: .determine_rate support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds .determine_rate support to the composite clock. It will
-use the .determine_rate callback from the rate component if available,
-and fall back on the mux component otherwise. This allows composite
-clocks to enjoy the benefits of automatic clock reparenting.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/clk-composite.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/clk/clk-composite.c
-+++ b/drivers/clk/clk-composite.c
-@@ -55,6 +55,30 @@ static unsigned long clk_composite_recal
- return rate_ops->recalc_rate(rate_hw, parent_rate);
- }
-
-+static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long *best_parent_rate,
-+ struct clk **best_parent_p)
-+{
-+ struct clk_composite *composite = to_clk_composite(hw);
-+ const struct clk_ops *rate_ops = composite->rate_ops;
-+ const struct clk_ops *mux_ops = composite->mux_ops;
-+ struct clk_hw *rate_hw = composite->rate_hw;
-+ struct clk_hw *mux_hw = composite->mux_hw;
-+
-+ if (rate_hw && rate_ops && rate_ops->determine_rate) {
-+ rate_hw->clk = hw->clk;
-+ return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
-+ best_parent_p);
-+ } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
-+ mux_hw->clk = hw->clk;
-+ return mux_ops->determine_rate(rate_hw, rate, best_parent_rate,
-+ best_parent_p);
-+ } else {
-+ pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
-+ return 0;
-+ }
-+}
-+
- static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
- {
-@@ -147,6 +171,8 @@ struct clk *clk_register_composite(struc
- composite->mux_ops = mux_ops;
- clk_composite_ops->get_parent = clk_composite_get_parent;
- clk_composite_ops->set_parent = clk_composite_set_parent;
-+ if (mux_ops->determine_rate)
-+ clk_composite_ops->determine_rate = clk_composite_determine_rate;
- }
-
- if (rate_hw && rate_ops) {
-@@ -170,6 +196,8 @@ struct clk *clk_register_composite(struc
- composite->rate_hw = rate_hw;
- composite->rate_ops = rate_ops;
- clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
-+ if (rate_ops->determine_rate)
-+ clk_composite_ops->determine_rate = clk_composite_determine_rate;
- }
-
- if (gate_hw && gate_ops) {
+++ /dev/null
-From b3cb099f8b0cbe56fcfbb4fb9c7cce48afff41f0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:10 -0300
-Subject: [PATCH] clk: sunxi: factors: fix off-by-one masks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The previous code would generate one bit too long masks, and was
-needlessly complicated. This patch replaces it by simpler code that can
-generate the masks correctly.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -40,7 +40,7 @@ struct clk_factors {
-
- #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-
--#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos))
-+#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
- #define CLRMASK(len, pos) (~(SETMASK(len, pos)))
- #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
-
+++ /dev/null
-From 789bea92aba0256a7f5309992327df8729333750 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:11 -0300
-Subject: [PATCH] clk: sunxi: factors: clear variables before using them
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Random bits may get into our factors if we don't clear n, k, m and p.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -88,7 +88,7 @@ static long clk_factors_round_rate(struc
- static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-- u8 n, k, m, p;
-+ u8 n = 0, k = 0, m = 0, p = 0;
- u32 reg;
- struct clk_factors *factors = to_clk_factors(hw);
- struct clk_factors_config *config = factors->config;
+++ /dev/null
-From 7df19a0adca7806e081479eecb07365652c26ef5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 22:03:12 -0300
-Subject: [PATCH] clk: sunxi: protect core clocks from accidental shutdown
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some important clocks may get disabled as a side effect of another clock
-being disabled, because they have no consumers. This patch implements a
-mechanism so those clocks can be claimed by the driver and therefore
-remain enabled at all times.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-
-Conflicts:
- drivers/clk/sunxi/clk-sunxi.c
----
- drivers/clk/sunxi/clk-sunxi.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -616,6 +616,31 @@ static void __init of_sunxi_table_clock_
- }
- }
-
-+/**
-+ * System clock protection
-+ *
-+ * By enabling these critical clocks, we prevent their accidental gating
-+ * by the framework
-+ */
-+static void __init sunxi_clock_protect(void)
-+{
-+ struct clk *clk;
-+
-+ /* memory bus clock - sun5i+ */
-+ clk = clk_get(NULL, "mbus");
-+ if (!IS_ERR(clk)) {
-+ clk_prepare_enable(clk);
-+ clk_put(clk);
-+ }
-+
-+ /* DDR clock - sun4i+ */
-+ clk = clk_get(NULL, "pll5_ddr");
-+ if (!IS_ERR(clk)) {
-+ clk_prepare_enable(clk);
-+ clk_put(clk);
-+ }
-+}
-+
- static void __init sunxi_init_clocks(struct device_node *np)
- {
- /* Register factor clocks */
-@@ -629,6 +654,9 @@ static void __init sunxi_init_clocks(str
-
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-+
-+ /* Enable core system clocks */
-+ sunxi_clock_protect();
- }
- CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
- CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
+++ /dev/null
-From 9dc8189536f4c59bb7ad8c736021cefc1488bf74 Mon Sep 17 00:00:00 2001
-From: "Victor N. Ramos Mello" <victornrm@gmail.com>
-Date: Fri, 18 Oct 2013 20:27:51 -0300
-Subject: [PATCH] drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c
-
-Fix a possible memory leak in sun4i_osc_clk_setup().
-Moved clock-frequency check to save superfluous allocation.
-
-Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-sunxi.c | 28 +++++++++++++++++-----------
- 1 file changed, 17 insertions(+), 11 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -37,18 +37,16 @@ static void __init sun4i_osc_clk_setup(s
- const char *clk_name = node->name;
- u32 rate;
-
-+ if (of_property_read_u32(node, "clock-frequency", &rate))
-+ return;
-+
- /* allocate fixed-rate and gate clock structs */
- fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
- if (!fixed)
- return;
- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-- if (!gate) {
-- kfree(fixed);
-- return;
-- }
--
-- if (of_property_read_u32(node, "clock-frequency", &rate))
-- return;
-+ if (!gate)
-+ goto err_free_fixed;
-
- /* set up gate and fixed rate properties */
- gate->reg = of_iomap(node, 0);
-@@ -63,10 +61,18 @@ static void __init sun4i_osc_clk_setup(s
- &gate->hw, &clk_gate_ops,
- CLK_IS_ROOT);
-
-- if (!IS_ERR(clk)) {
-- of_clk_add_provider(node, of_clk_src_simple_get, clk);
-- clk_register_clkdev(clk, clk_name, NULL);
-- }
-+ if (IS_ERR(clk))
-+ goto err_free_gate;
-+
-+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
-+ clk_register_clkdev(clk, clk_name, NULL);
-+
-+ return;
-+
-+err_free_gate:
-+ kfree(gate);
-+err_free_fixed:
-+ kfree(fixed);
- }
- CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
-
+++ /dev/null
-From 8015cea648c452bbfe0fc820dcb1185beaeb8736 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:07:43 +0300
-Subject: [PATCH] reset: Add Allwinner SoCs Reset Controller Driver
-
-The Allwinner A31 and most of the other Allwinner SoCs have an IP
-maintaining a few other IPs in the SoC in reset by default. Among these
-IPs are the A31's High Speed Timers, hence why we can't use the regular
-driver construct in every cases, and need to call the registering
-function directly during machine initialisation.
-
-Apart from this, the implementation is fairly straightforward, and could
-easily be moved to a generic MMIO-based reset controller driver if the
-need ever arise.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- drivers/reset/Makefile | 1 +
- drivers/reset/reset-sunxi.c | 175 ++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 176 insertions(+)
- create mode 100644 drivers/reset/reset-sunxi.c
-
---- a/drivers/reset/Makefile
-+++ b/drivers/reset/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_RESET_CONTROLLER) += core.o
-+obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
---- /dev/null
-+++ b/drivers/reset/reset-sunxi.c
-@@ -0,0 +1,175 @@
-+/*
-+ * Allwinner SoCs Reset Controller driver
-+ *
-+ * Copyright 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset-controller.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+struct sunxi_reset_data {
-+ spinlock_t lock;
-+ void __iomem *membase;
-+ struct reset_controller_dev rcdev;
-+};
-+
-+static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct sunxi_reset_data *data = container_of(rcdev,
-+ struct sunxi_reset_data,
-+ rcdev);
-+ int bank = id / BITS_PER_LONG;
-+ int offset = id % BITS_PER_LONG;
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&data->lock, flags);
-+
-+ reg = readl(data->membase + (bank * 4));
-+ writel(reg & ~BIT(offset), data->membase + (bank * 4));
-+
-+ spin_unlock_irqrestore(&data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct sunxi_reset_data *data = container_of(rcdev,
-+ struct sunxi_reset_data,
-+ rcdev);
-+ int bank = id / BITS_PER_LONG;
-+ int offset = id % BITS_PER_LONG;
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(&data->lock, flags);
-+
-+ reg = readl(data->membase + (bank * 4));
-+ writel(reg | BIT(offset), data->membase + (bank * 4));
-+
-+ spin_unlock_irqrestore(&data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static struct reset_control_ops sunxi_reset_ops = {
-+ .assert = sunxi_reset_assert,
-+ .deassert = sunxi_reset_deassert,
-+};
-+
-+static int sunxi_reset_init(struct device_node *np)
-+{
-+ struct sunxi_reset_data *data;
-+ struct resource res;
-+ resource_size_t size;
-+ int ret;
-+
-+ data = kzalloc(sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ ret = of_address_to_resource(np, 0, &res);
-+ if (ret)
-+ goto err_alloc;
-+
-+ size = resource_size(&res);
-+ if (!request_mem_region(res.start, size, np->name)) {
-+ ret = -EBUSY;
-+ goto err_alloc;
-+ }
-+
-+ data->membase = ioremap(res.start, size);
-+ if (!data->membase) {
-+ ret = -ENOMEM;
-+ goto err_alloc;
-+ }
-+
-+ data->rcdev.owner = THIS_MODULE;
-+ data->rcdev.nr_resets = size * 32;
-+ data->rcdev.ops = &sunxi_reset_ops;
-+ data->rcdev.of_node = np;
-+ reset_controller_register(&data->rcdev);
-+
-+ return 0;
-+
-+err_alloc:
-+ kfree(data);
-+ return ret;
-+};
-+
-+/*
-+ * These are the reset controller we need to initialize early on in
-+ * our system, before we can even think of using a regular device
-+ * driver for it.
-+ */
-+static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
-+ { .compatible = "allwinner,sun6i-a31-ahb1-reset", },
-+ { /* sentinel */ },
-+};
-+
-+void __init sun6i_reset_init(void)
-+{
-+ struct device_node *np;
-+
-+ for_each_matching_node(np, sunxi_early_reset_dt_ids)
-+ sunxi_reset_init(np);
-+}
-+
-+/*
-+ * And these are the controllers we can register through the regular
-+ * device model.
-+ */
-+static const struct of_device_id sunxi_reset_dt_ids[] = {
-+ { .compatible = "allwinner,sun6i-a31-clock-reset", },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
-+
-+static int sunxi_reset_probe(struct platform_device *pdev)
-+{
-+ return sunxi_reset_init(pdev->dev.of_node);
-+}
-+
-+static int sunxi_reset_remove(struct platform_device *pdev)
-+{
-+ struct sunxi_reset_data *data = platform_get_drvdata(pdev);
-+
-+ reset_controller_unregister(&data->rcdev);
-+ iounmap(data->membase);
-+ kfree(data);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_reset_driver = {
-+ .probe = sunxi_reset_probe,
-+ .remove = sunxi_reset_remove,
-+ .driver = {
-+ .name = "sunxi-reset",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sunxi_reset_dt_ids,
-+ },
-+};
-+module_platform_driver(sunxi_reset_driver);
-+
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
-+MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 73f948fb57f489ed8252fa8480575c91f027200d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:09:55 +0300
-Subject: [PATCH] ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER
-
-The A31 has a reset controller, and we have to select this option to
-have access to the reset controller framework.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/mach-sunxi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -1,5 +1,6 @@
- config ARCH_SUNXI
- bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
-+ select ARCH_HAS_RESET_CONTROLLER
- select ARCH_REQUIRE_GPIOLIB
- select ARM_GIC
- select CLKSRC_MMIO
+++ /dev/null
-From dae0e37c2df466f5eb6459d05f392e86b4236666 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 5 Oct 2013 14:53:48 +0200
-Subject: [PATCH] ARM: sunxi: Register the A31 reset IP in init_time
-
-The A31 has a reset IP that maintains a few other IPs in reset by
-default. Among these IPs are the UARTs, and most notably the timers. We
-thus need to register the reset driver before initializing the timers so
-that the reset timer can use the reset framework.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/mach-sunxi/sunxi.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -10,6 +10,8 @@
- * warranty of any kind, whether express or implied.
- */
-
-+#include <linux/clk-provider.h>
-+#include <linux/clocksource.h>
- #include <linux/delay.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-@@ -132,8 +134,17 @@ static const char * const sun6i_board_dt
- NULL,
- };
-
-+extern void __init sun6i_reset_init(void);
-+static void __init sun6i_timer_init(void)
-+{
-+ of_clk_init(NULL);
-+ sun6i_reset_init();
-+ clocksource_of_init();
-+}
-+
- DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
- .init_machine = sunxi_dt_init,
-+ .init_time = sun6i_timer_init,
- .dt_compat = sun6i_board_dt_compat,
- .restart = sun6i_restart,
- MACHINE_END
+++ /dev/null
-From 6f5002c91f35f6b171bc608b87b3f2b55451f32b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 3 Nov 2013 10:30:13 +0100
-Subject: [PATCH] ARM: sun6i: Add SMP support for the Allwinner A31
-
-The A31 is a quad Cortex-A7. Add the logic to use the IPs used to
-control the CPU configuration and the CPU power so that we can bring up
-secondary CPUs at boot.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/mach-sunxi/Makefile | 1 +
- arch/arm/mach-sunxi/common.h | 19 +++++++
- arch/arm/mach-sunxi/headsmp.S | 9 +++
- arch/arm/mach-sunxi/platsmp.c | 124 ++++++++++++++++++++++++++++++++++++++++++
- arch/arm/mach-sunxi/sunxi.c | 3 +
- 5 files changed, 156 insertions(+)
- create mode 100644 arch/arm/mach-sunxi/common.h
- create mode 100644 arch/arm/mach-sunxi/headsmp.S
- create mode 100644 arch/arm/mach-sunxi/platsmp.c
-
---- a/arch/arm/mach-sunxi/Makefile
-+++ b/arch/arm/mach-sunxi/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
---- /dev/null
-+++ b/arch/arm/mach-sunxi/common.h
-@@ -0,0 +1,19 @@
-+/*
-+ * Core functions for Allwinner SoCs
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef __ARCH_SUNXI_COMMON_H_
-+#define __ARCH_SUNXI_COMMON_H_
-+
-+void sun6i_secondary_startup(void);
-+extern struct smp_operations sun6i_smp_ops;
-+
-+#endif /* __ARCH_SUNXI_COMMON_H_ */
---- /dev/null
-+++ b/arch/arm/mach-sunxi/headsmp.S
-@@ -0,0 +1,9 @@
-+#include <linux/linkage.h>
-+#include <linux/init.h>
-+
-+ .section ".text.head", "ax"
-+
-+ENTRY(sun6i_secondary_startup)
-+ msr cpsr_fsxc, #0xd3
-+ b secondary_startup
-+ENDPROC(sun6i_secondary_startup)
---- /dev/null
-+++ b/arch/arm/mach-sunxi/platsmp.c
-@@ -0,0 +1,124 @@
-+/*
-+ * SMP support for Allwinner SoCs
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * Based on code
-+ * Copyright (C) 2012-2013 Allwinner Ltd.
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/memory.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/smp.h>
-+
-+#include "common.h"
-+
-+#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
-+#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
-+#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
-+#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
-+#define CPUCFG_GEN_CTRL_REG 0x184
-+#define CPUCFG_PRIVATE0_REG 0x1a4
-+#define CPUCFG_PRIVATE1_REG 0x1a8
-+#define CPUCFG_DBG_CTL0_REG 0x1e0
-+#define CPUCFG_DBG_CTL1_REG 0x1e4
-+
-+#define PRCM_CPU_PWROFF_REG 0x100
-+#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
-+
-+static void __iomem *cpucfg_membase;
-+static void __iomem *prcm_membase;
-+
-+static DEFINE_SPINLOCK(cpu_lock);
-+
-+static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
-+{
-+ struct device_node *node;
-+
-+ node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
-+ if (!node) {
-+ pr_err("Missing A31 PRCM node in the device tree\n");
-+ return;
-+ }
-+
-+ prcm_membase = of_iomap(node, 0);
-+ if (!prcm_membase) {
-+ pr_err("Couldn't map A31 PRCM registers\n");
-+ return;
-+ }
-+
-+ node = of_find_compatible_node(NULL, NULL,
-+ "allwinner,sun6i-a31-cpuconfig");
-+ if (!node) {
-+ pr_err("Missing A31 CPU config node in the device tree\n");
-+ return;
-+ }
-+
-+ cpucfg_membase = of_iomap(node, 0);
-+ if (!cpucfg_membase)
-+ pr_err("Couldn't map A31 CPU config registers\n");
-+
-+}
-+
-+static int sun6i_smp_boot_secondary(unsigned int cpu,
-+ struct task_struct *idle)
-+{
-+ u32 reg;
-+ int i;
-+
-+ if (!(prcm_membase && cpucfg_membase))
-+ return -EFAULT;
-+
-+ spin_lock(&cpu_lock);
-+
-+ /* Set CPU boot address */
-+ writel(virt_to_phys(sun6i_secondary_startup),
-+ cpucfg_membase + CPUCFG_PRIVATE0_REG);
-+
-+ /* Assert the CPU core in reset */
-+ writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
-+
-+ /* Assert the L1 cache in reset */
-+ reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
-+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
-+
-+ /* Disable external debug access */
-+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+ writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+
-+ /* Power up the CPU */
-+ for (i = 0; i <= 8; i++)
-+ writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
-+ mdelay(10);
-+
-+ /* Clear CPU power-off gating */
-+ reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
-+ writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
-+ mdelay(1);
-+
-+ /* Deassert the CPU core reset */
-+ writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
-+
-+ /* Enable back the external debug accesses */
-+ reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+ writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
-+
-+ spin_unlock(&cpu_lock);
-+
-+ return 0;
-+}
-+
-+struct smp_operations sun6i_smp_ops __initdata = {
-+ .smp_prepare_cpus = sun6i_smp_prepare_cpus,
-+ .smp_boot_secondary = sun6i_smp_boot_secondary,
-+};
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -25,6 +25,8 @@
- #include <asm/mach/map.h>
- #include <asm/system_misc.h>
-
-+#include "common.h"
-+
- #define SUN4I_WATCHDOG_CTRL_REG 0x00
- #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
- #define SUN4I_WATCHDOG_MODE_REG 0x04
-@@ -147,6 +149,7 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner su
- .init_time = sun6i_timer_init,
- .dt_compat = sun6i_board_dt_compat,
- .restart = sun6i_restart,
-+ .smp = smp_ops(sun6i_smp_ops),
- MACHINE_END
-
- static const char * const sun7i_board_dt_compat[] = {
+++ /dev/null
-From f88dc0623908b574d9dcdae8815ccd0829fc6828 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 24 Sep 2013 11:10:41 +0300
-Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
-
-The A31 has a reset controller IP that maintains a few other IPs in
-reset, among which we can find the UARTs, high speed timers or the I2C.
-Now that we have support for them, add the reset controllers to the DTSI.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -212,6 +212,24 @@
- };
- };
-
-+ ahb1_rst: reset@01c202c0 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-ahb1-reset";
-+ reg = <0x01c202c0 0xc>;
-+ };
-+
-+ apb1_rst: reset@01c202d0 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-clock-reset";
-+ reg = <0x01c202d0 0x4>;
-+ };
-+
-+ apb2_rst: reset@01c202d8 {
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun6i-a31-clock-reset";
-+ reg = <0x01c202d8 0x4>;
-+ };
-+
- timer@01c20c00 {
- compatible = "allwinner,sun4i-timer";
- reg = <0x01c20c00 0xa0>;
-@@ -235,6 +253,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 16>;
-+ resets = <&apb2_rst 16>;
- status = "disabled";
- };
-
-@@ -245,6 +264,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 17>;
-+ resets = <&apb2_rst 17>;
- status = "disabled";
- };
-
-@@ -255,6 +275,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 18>;
-+ resets = <&apb2_rst 18>;
- status = "disabled";
- };
-
-@@ -265,6 +286,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 19>;
-+ resets = <&apb2_rst 19>;
- status = "disabled";
- };
-
-@@ -275,6 +297,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 20>;
-+ resets = <&apb2_rst 20>;
- status = "disabled";
- };
-
-@@ -285,6 +308,7 @@
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 21>;
-+ resets = <&apb2_rst 21>;
- status = "disabled";
- };
-
+++ /dev/null
-From abc12cd5c39556824cc9022db6eddc64e8e8dbe9 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 23 Oct 2013 17:54:39 +0100
-Subject: [PATCH] clockevent: sun4i: Fill the irq field in the clockevent
- structure
-
-The clock event structure irq field was not filled previously to the
-interrupt we're using.
-
-This was resulting in the timer not being used at all when using a
-configuration with SMP enabled on a system with several CPUs, and with
-the cpumask set to the cpu_possible_mask.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clocksource/sun4i_timer.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -191,6 +191,7 @@ static void __init sun4i_timer_init(stru
- writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-
- sun4i_clockevent.cpumask = cpumask_of(0);
-+ sun4i_clockevent.irq = irq;
-
- clockevents_config_and_register(&sun4i_clockevent, rate,
- TIMER_SYNC_TICKS, 0xffffffff);
+++ /dev/null
-From 64a9fa131380f9cef9328d0cf9f2d49a538e6dd2 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 9 Oct 2013 22:44:56 +0200
-Subject: [PATCH] clocksource: sun4i: change CPU mask to cpu_possible_mask
-
-The interrupt for the timer is a shared processor interrupt, so any CPU
-found in the system can handle it. Switch to our cpumask to
-cpu_possible_mask instead of cpumask_of(0).
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clocksource/sun4i_timer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -190,7 +190,7 @@ static void __init sun4i_timer_init(stru
- val = readl(timer_base + TIMER_IRQ_EN_REG);
- writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-
-- sun4i_clockevent.cpumask = cpumask_of(0);
-+ sun4i_clockevent.cpumask = cpu_possible_mask;
- sun4i_clockevent.irq = irq;
-
- clockevents_config_and_register(&sun4i_clockevent, rate,
+++ /dev/null
-From a4eb936767bd6a63d54734b9ce48932609ce58eb Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] clocksource: sun4i: Increase a bit the clock event and
- sources rating
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We want to keep this driver as the default provider of the clock events
-and source, yet some other driver might fit in the "desired" category of
-ratings. Hence, we need to increase a bit the rating so that we can have
-more flexibility in the ratings we choose.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/clocksource/sun4i_timer.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clocksource/sun4i_timer.c
-+++ b/drivers/clocksource/sun4i_timer.c
-@@ -114,7 +114,7 @@ static int sun4i_clkevt_next_event(unsig
-
- static struct clock_event_device sun4i_clockevent = {
- .name = "sun4i_tick",
-- .rating = 300,
-+ .rating = 350,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = sun4i_clkevt_mode,
- .set_next_event = sun4i_clkevt_next_event,
-@@ -172,7 +172,7 @@ static void __init sun4i_timer_init(stru
-
- setup_sched_clock(sun4i_timer_sched_read, 32, rate);
- clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
-- rate, 300, 32, clocksource_mmio_readl_down);
-+ rate, 350, 32, clocksource_mmio_readl_down);
-
- ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-
+++ /dev/null
-From 9212bc4a3752e9a4db2f73afd99278eb28e5dcff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:32 -0300
-Subject: [PATCH] clk: sunxi: register factors clocks behind composite
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit reworks factors clock registration to be done behind a
-composite clock. This allows us to additionally add a gate, mux or
-divisors, as it will be needed by some future PLLs.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/clk/sunxi/clk-factors.c | 63 +------------------------------------
- drivers/clk/sunxi/clk-factors.h | 16 +++++-----
- drivers/clk/sunxi/clk-sunxi.c | 70 ++++++++++++++++++++++++++++++++++++++---
- 3 files changed, 76 insertions(+), 73 deletions(-)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -30,14 +30,6 @@
- * parent - fixed parent. No clk_set_parent support
- */
-
--struct clk_factors {
-- struct clk_hw hw;
-- void __iomem *reg;
-- struct clk_factors_config *config;
-- void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
-- spinlock_t *lock;
--};
--
- #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-
- #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
-@@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct c
- return 0;
- }
-
--static const struct clk_ops clk_factors_ops = {
-+const struct clk_ops clk_factors_ops = {
- .recalc_rate = clk_factors_recalc_rate,
- .round_rate = clk_factors_round_rate,
- .set_rate = clk_factors_set_rate,
- };
--
--/**
-- * clk_register_factors - register a factors clock with
-- * the clock framework
-- * @dev: device registering this clock
-- * @name: name of this clock
-- * @parent_name: name of clock's parent
-- * @flags: framework-specific flags
-- * @reg: register address to adjust factors
-- * @config: shift and width of factors n, k, m and p
-- * @get_factors: function to calculate the factors for a given frequency
-- * @lock: shared register lock for this clock
-- */
--struct clk *clk_register_factors(struct device *dev, const char *name,
-- const char *parent_name,
-- unsigned long flags, void __iomem *reg,
-- struct clk_factors_config *config,
-- void (*get_factors)(u32 *rate, u32 parent,
-- u8 *n, u8 *k, u8 *m, u8 *p),
-- spinlock_t *lock)
--{
-- struct clk_factors *factors;
-- struct clk *clk;
-- struct clk_init_data init;
--
-- /* allocate the factors */
-- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
-- if (!factors) {
-- pr_err("%s: could not allocate factors clk\n", __func__);
-- return ERR_PTR(-ENOMEM);
-- }
--
-- init.name = name;
-- init.ops = &clk_factors_ops;
-- init.flags = flags;
-- init.parent_names = (parent_name ? &parent_name : NULL);
-- init.num_parents = (parent_name ? 1 : 0);
--
-- /* struct clk_factors assignments */
-- factors->reg = reg;
-- factors->config = config;
-- factors->lock = lock;
-- factors->hw.init = &init;
-- factors->get_factors = get_factors;
--
-- /* register the clock */
-- clk = clk_register(dev, &factors->hw);
--
-- if (IS_ERR(clk))
-- kfree(factors);
--
-- return clk;
--}
---- a/drivers/clk/sunxi/clk-factors.h
-+++ b/drivers/clk/sunxi/clk-factors.h
-@@ -17,11 +17,13 @@ struct clk_factors_config {
- u8 pwidth;
- };
-
--struct clk *clk_register_factors(struct device *dev, const char *name,
-- const char *parent_name,
-- unsigned long flags, void __iomem *reg,
-- struct clk_factors_config *config,
-- void (*get_factors) (u32 *rate, u32 parent_rate,
-- u8 *n, u8 *k, u8 *m, u8 *p),
-- spinlock_t *lock);
-+struct clk_factors {
-+ struct clk_hw hw;
-+ void __iomem *reg;
-+ struct clk_factors_config *config;
-+ void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
-+ spinlock_t *lock;
-+};
-+
-+extern const struct clk_ops clk_factors_ops;
- #endif
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -23,6 +23,9 @@
-
- static DEFINE_SPINLOCK(clk_lock);
-
-+/* Maximum number of parents our clocks have */
-+#define SUNXI_MAX_PARENTS 5
-+
- /**
- * sun4i_osc_clk_setup() - Setup function for gatable oscillator
- */
-@@ -261,7 +264,11 @@ static void sun4i_get_apb1_factors(u32 *
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-+#define SUNXI_FACTORS_MUX_MASK 0x3
-+
- struct factors_data {
-+ int enable;
-+ int mux;
- struct clk_factors_config *table;
- void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
- };
-@@ -312,16 +319,71 @@ static void __init sunxi_factors_clk_set
- struct factors_data *data)
- {
- struct clk *clk;
-+ struct clk_factors *factors;
-+ struct clk_gate *gate = NULL;
-+ struct clk_mux *mux = NULL;
-+ struct clk_hw *gate_hw = NULL;
-+ struct clk_hw *mux_hw = NULL;
- const char *clk_name = node->name;
-- const char *parent;
-+ const char *parents[SUNXI_MAX_PARENTS];
- void *reg;
-+ int i = 0;
-
- reg = of_iomap(node, 0);
-
-- parent = of_clk_get_parent_name(node, 0);
-+ /* if we have a mux, we will have >1 parents */
-+ while (i < SUNXI_MAX_PARENTS &&
-+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-+ i++;
-+
-+ factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
-+ if (!factors)
-+ return;
-+
-+ /* Add a gate if this factor clock can be gated */
-+ if (data->enable) {
-+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-+ if (!gate) {
-+ kfree(factors);
-+ return;
-+ }
-+
-+ /* set up gate properties */
-+ gate->reg = reg;
-+ gate->bit_idx = data->enable;
-+ gate->lock = &clk_lock;
-+ gate_hw = &gate->hw;
-+ }
-+
-+ /* Add a mux if this factor clock can be muxed */
-+ if (data->mux) {
-+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
-+ if (!mux) {
-+ kfree(factors);
-+ kfree(gate);
-+ return;
-+ }
-+
-+ /* set up gate properties */
-+ mux->reg = reg;
-+ mux->shift = data->mux;
-+ mux->mask = SUNXI_FACTORS_MUX_MASK;
-+ mux->lock = &clk_lock;
-+ mux_hw = &mux->hw;
-+ }
-
-- clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
-- data->table, data->getter, &clk_lock);
-+ /* set up factors properties */
-+ factors->reg = reg;
-+ factors->config = data->table;
-+ factors->get_factors = data->getter;
-+ factors->lock = &clk_lock;
-+
-+ clk = clk_register_composite(NULL, clk_name,
-+ parents, i,
-+ mux_hw, &clk_mux_ops,
-+ &factors->hw, &clk_factors_ops,
-+ gate_hw, &clk_gate_ops,
-+ i ? 0 : CLK_IS_ROOT);
-
- if (!IS_ERR(clk)) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
+++ /dev/null
-From 33574f94b0d4d8bc8af732fbcb4f911c3dd8c96b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:33 -0300
-Subject: [PATCH] clk: sunxi: clean the magic number of mux parents
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This was pointed out during the review of the factor patches. Let's
-indicate what does that magic 5 mean.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -420,13 +420,14 @@ static void __init sunxi_mux_clk_setup(s
- {
- struct clk *clk;
- const char *clk_name = node->name;
-- const char *parents[5];
-+ const char *parents[SUNXI_MAX_PARENTS];
- void *reg;
- int i = 0;
-
- reg = of_iomap(node, 0);
-
-- while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
-+ while (i < SUNXI_MAX_PARENTS &&
-+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
- clk = clk_register_mux(NULL, clk_name, parents, i,
+++ /dev/null
-From 3d56b9643ff9fff3c7ceb095e03f4ab7e149b9ce Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:34 -0300
-Subject: [PATCH] clk: sunxi: add gating support to PLL1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds gating support to PLL1 on the clock driver. This makes
-the PLL1 implementation fully compatible with PLL4 as well.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
- drivers/clk/sunxi/clk-sunxi.c | 2 ++
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -7,7 +7,7 @@ This binding uses the common clock bindi
- Required properties:
- - compatible : shall be one of the following:
- "allwinner,sun4i-osc-clk" - for a gatable oscillator
-- "allwinner,sun4i-pll1-clk" - for the main PLL clock
-+ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_a
- };
-
- static const struct factors_data sun4i_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun4i_pll1_config,
- .getter = sun4i_get_pll1_factors,
- };
-
- static const struct factors_data sun6i_a31_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun6i_a31_pll1_config,
- .getter = sun6i_a31_get_pll1_factors,
- };
+++ /dev/null
-From ff0b5fdb65bc7f10af7e83bb0919cb6bec2dc624 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:35 -0300
-Subject: [PATCH] ARM: sunxi: add PLL4 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
-device trees. PLL4 is compatible with PLL1.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 4 files changed, 28 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -66,6 +66,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -63,6 +63,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -67,6 +67,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -62,6 +62,13 @@
- clocks = <&osc24M>;
- };
-
-+ pll4: pll4@01c20018 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-pll1-clk";
-+ reg = <0x01c20018 0x4>;
-+ clocks = <&osc24M>;
-+ };
-+
- /*
- * This is a dummy clock, to be used as placeholder on
- * other mux clocks when a specific parent clock is not
+++ /dev/null
-From 8a3282a0a185108e37e7a48437b58d956ff56f4a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:36 -0300
-Subject: [PATCH] clk: sunxi: make factors_clk_setup return the clock it
- registers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-We will be needing this to register a factor clock as parent with leaf
-divisors on a single call.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- drivers/clk/sunxi/clk-sunxi.c | 15 ++++++++-------
- 1 file changed, 8 insertions(+), 7 deletions(-)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -317,8 +317,8 @@ static const struct factors_data sun4i_a
- .getter = sun4i_get_apb1_factors,
- };
-
--static void __init sunxi_factors_clk_setup(struct device_node *node,
-- struct factors_data *data)
-+static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
-+ const struct factors_data *data)
- {
- struct clk *clk;
- struct clk_factors *factors;
-@@ -340,14 +340,14 @@ static void __init sunxi_factors_clk_set
-
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
-- return;
-+ return NULL;
-
- /* Add a gate if this factor clock can be gated */
- if (data->enable) {
- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
- if (!gate) {
- kfree(factors);
-- return;
-+ return NULL;
- }
-
- /* set up gate properties */
-@@ -363,7 +363,7 @@ static void __init sunxi_factors_clk_set
- if (!mux) {
- kfree(factors);
- kfree(gate);
-- return;
-+ return NULL;
- }
-
- /* set up gate properties */
-@@ -384,13 +384,14 @@ static void __init sunxi_factors_clk_set
- parents, i,
- mux_hw, &clk_mux_ops,
- &factors->hw, &clk_factors_ops,
-- gate_hw, &clk_gate_ops,
-- i ? 0 : CLK_IS_ROOT);
-+ gate_hw, &clk_gate_ops, 0);
-
- if (!IS_ERR(clk)) {
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
- clk_register_clkdev(clk, clk_name, NULL);
- }
-+
-+ return clk;
- }
-
-
+++ /dev/null
-From 655893a197a5134a371a5c6b579f1bbce03ab413 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:37 -0300
-Subject: [PATCH] clk: sunxi: add PLL5 and PLL6 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements PLL5 and PLL6 support on the sunxi clock driver.
-These PLLs use a similar factor clock, but differ on their outputs.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
- drivers/clk/sunxi/clk-sunxi.c | 230 ++++++++++++++++++++++
- 2 files changed, 232 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -9,6 +9,8 @@ Required properties:
- "allwinner,sun4i-osc-clk" - for a gatable oscillator
- "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
-+ "allwinner,sun4i-pll5-clk" - for the PLL5 clock
-+ "allwinner,sun4i-pll6-clk" - for the PLL6 clock
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
- "allwinner,sun4i-axi-gates-clk" - for the AXI gates
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -218,6 +218,40 @@ static void sun6i_a31_get_pll1_factors(u
- }
-
- /**
-+ * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
-+ * PLL5 rate is calculated as follows
-+ * rate = parent_rate * n * (k + 1)
-+ * parent_rate is always 24Mhz
-+ */
-+
-+static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div;
-+
-+ /* Normalize value to a parent_rate multiple (24M) */
-+ div = *freq / parent_rate;
-+ *freq = parent_rate * div;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ if (div < 31)
-+ *k = 0;
-+ else if (div / 2 < 31)
-+ *k = 1;
-+ else if (div / 3 < 31)
-+ *k = 2;
-+ else
-+ *k = 3;
-+
-+ *n = DIV_ROUND_UP(div, (*k+1));
-+}
-+
-+
-+
-+/**
- * sun4i_get_apb1_factors() - calculates m, p factors for APB1
- * APB1 rate is calculated as follows
- * rate = (parent_rate >> p) / (m + 1);
-@@ -293,6 +327,13 @@ static struct clk_factors_config sun6i_a
- .mwidth = 2,
- };
-
-+static struct clk_factors_config sun4i_pll5_config = {
-+ .nshift = 8,
-+ .nwidth = 5,
-+ .kshift = 4,
-+ .kwidth = 2,
-+};
-+
- static struct clk_factors_config sun4i_apb1_config = {
- .mshift = 0,
- .mwidth = 5,
-@@ -312,6 +353,12 @@ static const struct factors_data sun6i_a
- .getter = sun6i_a31_get_pll1_factors,
- };
-
-+static const struct factors_data sun4i_pll5_data __initconst = {
-+ .enable = 31,
-+ .table = &sun4i_pll5_config,
-+ .getter = sun4i_get_pll5_factors,
-+};
-+
- static const struct factors_data sun4i_apb1_data __initconst = {
- .table = &sun4i_apb1_config,
- .getter = sun4i_get_apb1_factors,
-@@ -627,6 +674,179 @@ static void __init sunxi_gates_clk_setup
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- }
-
-+
-+
-+/**
-+ * sunxi_divs_clk_setup() helper data
-+ */
-+
-+#define SUNXI_DIVS_MAX_QTY 2
-+#define SUNXI_DIVISOR_WIDTH 2
-+
-+struct divs_data {
-+ const struct factors_data *factors; /* data for the factor clock */
-+ struct {
-+ u8 fixed; /* is it a fixed divisor? if not... */
-+ struct clk_div_table *table; /* is it a table based divisor? */
-+ u8 shift; /* otherwise it's a normal divisor with this shift */
-+ u8 pow; /* is it power-of-two based? */
-+ u8 gate; /* is it independently gateable? */
-+ } div[SUNXI_DIVS_MAX_QTY];
-+};
-+
-+static struct clk_div_table pll6_sata_tbl[] = {
-+ { .val = 0, .div = 6, },
-+ { .val = 1, .div = 12, },
-+ { .val = 2, .div = 18, },
-+ { .val = 3, .div = 24, },
-+ { } /* sentinel */
-+};
-+
-+static const struct divs_data pll5_divs_data __initconst = {
-+ .factors = &sun4i_pll5_data,
-+ .div = {
-+ { .shift = 0, .pow = 0, }, /* M, DDR */
-+ { .shift = 16, .pow = 1, }, /* P, other */
-+ }
-+};
-+
-+static const struct divs_data pll6_divs_data __initconst = {
-+ .factors = &sun4i_pll5_data,
-+ .div = {
-+ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
-+ { .fixed = 2 }, /* P, other */
-+ }
-+};
-+
-+/**
-+ * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
-+ *
-+ * These clocks look something like this
-+ * ________________________
-+ * | ___divisor 1---|----> to consumer
-+ * parent >--| pll___/___divisor 2---|----> to consumer
-+ * | \_______________|____> to consumer
-+ * |________________________|
-+ */
-+
-+static void __init sunxi_divs_clk_setup(struct device_node *node,
-+ struct divs_data *data)
-+{
-+ struct clk_onecell_data *clk_data;
-+ const char *parent = node->name;
-+ const char *clk_name;
-+ struct clk **clks, *pclk;
-+ struct clk_hw *gate_hw, *rate_hw;
-+ const struct clk_ops *rate_ops;
-+ struct clk_gate *gate = NULL;
-+ struct clk_fixed_factor *fix_factor;
-+ struct clk_divider *divider;
-+ void *reg;
-+ int i = 0;
-+ int flags, clkflags;
-+
-+ /* Set up factor clock that we will be dividing */
-+ pclk = sunxi_factors_clk_setup(node, data->factors);
-+
-+ reg = of_iomap(node, 0);
-+
-+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
-+ if (!clk_data)
-+ return;
-+
-+ clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
-+ if (!clks)
-+ goto free_clkdata;
-+
-+ clk_data->clks = clks;
-+
-+ /* It's not a good idea to have automatic reparenting changing
-+ * our RAM clock! */
-+ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
-+
-+ for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
-+ if (of_property_read_string_index(node, "clock-output-names",
-+ i, &clk_name) != 0)
-+ break;
-+
-+ gate_hw = NULL;
-+ rate_hw = NULL;
-+ rate_ops = NULL;
-+
-+ /* If this leaf clock can be gated, create a gate */
-+ if (data->div[i].gate) {
-+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-+ if (!gate)
-+ goto free_clks;
-+
-+ gate->reg = reg;
-+ gate->bit_idx = data->div[i].gate;
-+ gate->lock = &clk_lock;
-+
-+ gate_hw = &gate->hw;
-+ }
-+
-+ /* Leaves can be fixed or configurable divisors */
-+ if (data->div[i].fixed) {
-+ fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
-+ if (!fix_factor)
-+ goto free_gate;
-+
-+ fix_factor->mult = 1;
-+ fix_factor->div = data->div[i].fixed;
-+
-+ rate_hw = &fix_factor->hw;
-+ rate_ops = &clk_fixed_factor_ops;
-+ } else {
-+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
-+ if (!divider)
-+ goto free_gate;
-+
-+ flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
-+
-+ divider->reg = reg;
-+ divider->shift = data->div[i].shift;
-+ divider->width = SUNXI_DIVISOR_WIDTH;
-+ divider->flags = flags;
-+ divider->lock = &clk_lock;
-+ divider->table = data->div[i].table;
-+
-+ rate_hw = ÷r->hw;
-+ rate_ops = &clk_divider_ops;
-+ }
-+
-+ /* Wrap the (potential) gate and the divisor on a composite
-+ * clock to unify them */
-+ clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
-+ NULL, NULL,
-+ rate_hw, rate_ops,
-+ gate_hw, &clk_gate_ops,
-+ clkflags);
-+
-+ WARN_ON(IS_ERR(clk_data->clks[i]));
-+ clk_register_clkdev(clks[i], clk_name, NULL);
-+ }
-+
-+ /* The last clock available on the getter is the parent */
-+ clks[i++] = pclk;
-+
-+ /* Adjust to the real max */
-+ clk_data->clk_num = i;
-+
-+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+ return;
-+
-+free_gate:
-+ kfree(gate);
-+free_clks:
-+ kfree(clks);
-+free_clkdata:
-+ kfree(clk_data);
-+}
-+
-+
-+
- /* Matches for factors clocks */
- static const struct of_device_id clk_factors_match[] __initconst = {
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
-@@ -644,6 +864,13 @@ static const struct of_device_id clk_div
- {}
- };
-
-+/* Matches for divided outputs */
-+static const struct of_device_id clk_divs_match[] __initconst = {
-+ {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
-+ {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
-+ {}
-+};
-+
- /* Matches for mux clocks */
- static const struct of_device_id clk_mux_match[] __initconst = {
- {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
-@@ -721,6 +948,9 @@ static void __init sunxi_init_clocks(str
- /* Register divider clocks */
- of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
-
-+ /* Register divided output clocks */
-+ of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
-+
- /* Register mux clocks */
- of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
-
+++ /dev/null
-From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:38 -0300
-Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
-device trees.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++--
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------
- 4 files changed, 67 insertions(+), 18 deletions(-)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -73,6 +73,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -138,12 +154,11 @@
- "apb0_ir1", "apb0_keypad";
- };
-
-- /* dummy is pll62 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -70,6 +70,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -130,12 +146,11 @@
- "apb0_ir", "apb0_keypad";
- };
-
-- /* dummy is pll62 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -74,6 +74,22 @@
- clocks = <&osc24M>;
- };
-
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
-+ };
-+
- /* dummy is 200M */
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
-@@ -132,12 +148,11 @@
- clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
- };
-
-- /* dummy is pll6 */
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&dummy>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -69,23 +69,27 @@
- clocks = <&osc24M>;
- };
-
-- /*
-- * This is a dummy clock, to be used as placeholder on
-- * other mux clocks when a specific parent clock is not
-- * yet implemented. It should be dropped when the driver
-- * is complete.
-- */
-- pll6: pll6 {
-- #clock-cells = <0>;
-- compatible = "fixed-clock";
-- clock-frequency = <0>;
-+ pll5: pll5@01c20020 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll5-clk";
-+ reg = <0x01c20020 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll5_ddr", "pll5_other";
-+ };
-+
-+ pll6: pll6@01c20028 {
-+ #clock-cells = <1>;
-+ compatible = "allwinner,sun4i-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
- };
-
- cpu: cpu@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
-- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
-+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
- };
-
- axi: axi@01c20054 {
-@@ -144,7 +148,7 @@
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
-- clocks = <&osc24M>, <&pll6>, <&osc32k>;
-+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- };
-
- apb1: apb1@01c20058 {
+++ /dev/null
-From bdc913d1ef5143a8728ae414fcb90f9ed87a58da Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:39 -0300
-Subject: [PATCH] clk: sunxi: mod0 support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements support for the "module 0" type of clocks, as
-used by MMC, IR, NAND, SATA and other components.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Mike Turquette <mturquette@linaro.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 5 +-
- drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
- 2 files changed, 61 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -35,10 +35,13 @@ Required properties:
- "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
- "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
-+ "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
--- clocks : shall be the input parent clock(s) phandle for the clock
-+- clocks : shall be the input parent clock(s) phandle for the clock. For
-+ multiplexed clocks, the list order must match the hardware
-+ programming order.
- - #clock-cells : from common clock binding; shall be set to 0 except for
- "allwinner,*-gates-clk" where it shall be set to 1
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -295,6 +295,47 @@ static void sun4i_get_apb1_factors(u32 *
-
-
- /**
-+ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
-+ * MMC rate is calculated as follows
-+ * rate = (parent_rate >> p) / (m + 1);
-+ */
-+
-+static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div, calcm, calcp;
-+
-+ /* These clocks can only divide, so we will never be able to achieve
-+ * frequencies higher than the parent frequency */
-+ if (*freq > parent_rate)
-+ *freq = parent_rate;
-+
-+ div = parent_rate / *freq;
-+
-+ if (div < 16)
-+ calcp = 0;
-+ else if (div / 2 < 16)
-+ calcp = 1;
-+ else if (div / 4 < 16)
-+ calcp = 2;
-+ else
-+ calcp = 3;
-+
-+ calcm = DIV_ROUND_UP(div, 1 << calcp);
-+
-+ *freq = (parent_rate >> calcp) / calcm;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *m = calcm - 1;
-+ *p = calcp;
-+}
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-@@ -341,6 +382,14 @@ static struct clk_factors_config sun4i_a
- .pwidth = 2,
- };
-
-+/* user manual says "n" but it's really "p" */
-+static struct clk_factors_config sun4i_mod0_config = {
-+ .mshift = 0,
-+ .mwidth = 4,
-+ .pshift = 16,
-+ .pwidth = 2,
-+};
-+
- static const struct factors_data sun4i_pll1_data __initconst = {
- .enable = 31,
- .table = &sun4i_pll1_config,
-@@ -364,6 +413,13 @@ static const struct factors_data sun4i_a
- .getter = sun4i_get_apb1_factors,
- };
-
-+static const struct factors_data sun4i_mod0_data __initconst = {
-+ .enable = 31,
-+ .mux = 24,
-+ .table = &sun4i_mod0_config,
-+ .getter = sun4i_get_mod0_factors,
-+};
-+
- static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- const struct factors_data *data)
- {
-@@ -852,6 +908,7 @@ static const struct of_device_id clk_fac
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
- {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
-+ {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
- {}
- };
-
+++ /dev/null
-From 7d47b009bf287bf5e0817f47c40e32b7ec0e8151 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:40 -0300
-Subject: [PATCH] clk: sunxi: support better factor DT nodes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The DT nodes should look like
-
- abc_clk: clk@deadbeef {
- ...
- clock-output-names = "abc";
- }
-
-But our old DT nodes look like
-
- abc: abc@deadbeef {
- ...
- }
-
-So, let's support both formats, until we can transition everything
-to the new, correct one.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -441,6 +441,15 @@ static struct clk * __init sunxi_factors
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-+ /* Nodes should be providing the name via clock-output-names
-+ * but originally our dts didn't, and so we used node->name.
-+ * The new, better nodes look like clk@deadbeef, so we pull the
-+ * name just in this case */
-+ if (!strcmp("clk", clk_name)) {
-+ of_property_read_string_index(node, "clock-output-names",
-+ 0, &clk_name);
-+ }
-+
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
- return NULL;
+++ /dev/null
-From dda274b6f95902b619af1fb14f26e231bb420371 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:41 -0300
-Subject: [PATCH] ARM: sun4i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks present on sun4i to its device tree
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 120 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -180,6 +180,126 @@
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ mmc3_clk: clk@01c20094 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20094 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc3";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ pata_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "pata";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
-+
-+ ir1_clk: clk@01c200b4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir1";
-+ };
-+
-+ spi3_clk: clk@01c200d4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200d4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:42 -0300
-Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks available on A10 and A13. The list
-has been constructed by looking at the Allwinner code release for A10S
-and A13.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 176 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -169,6 +169,94 @@
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -170,6 +170,94 @@
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From d7904e075e3378bec09333b6a3247b3146b3dd91 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:43 -0300
-Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds all the mod0 clocks available on A20 to its device
-tree. This list was created by looking at AW's code release.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 120 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -170,6 +170,126 @@
- "apb1_uart2", "apb1_uart3", "apb1_uart4",
- "apb1_uart5", "apb1_uart6", "apb1_uart7";
- };
-+
-+ nand_clk: clk@01c20080 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20080 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "nand";
-+ };
-+
-+ ms_clk: clk@01c20084 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20084 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ms";
-+ };
-+
-+ mmc0_clk: clk@01c20088 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20088 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc0";
-+ };
-+
-+ mmc1_clk: clk@01c2008c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2008c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc1";
-+ };
-+
-+ mmc2_clk: clk@01c20090 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20090 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc2";
-+ };
-+
-+ mmc3_clk: clk@01c20094 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20094 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mmc3";
-+ };
-+
-+ ts_clk: clk@01c20098 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c20098 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ts";
-+ };
-+
-+ ss_clk: clk@01c2009c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2009c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ss";
-+ };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ pata_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "pata";
-+ };
-+
-+ ir0_clk: clk@01c200b0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b0 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir0";
-+ };
-+
-+ ir1_clk: clk@01c200b4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200b4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "ir1";
-+ };
-+
-+ spi3_clk: clk@01c200d4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200d4 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 04b5b3f9c83c0c0b472c4704d83ec7f56a485a21 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Thu, 5 Sep 2013 19:52:41 -0300
-Subject: [PATCH] clk: sunxi: factors: automatic reparenting support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit implements .determine_rate, so that our factor clocks can be
-reparented when needed.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-factors.c | 36 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/drivers/clk/sunxi/clk-factors.c
-+++ b/drivers/clk/sunxi/clk-factors.c
-@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struc
- return rate;
- }
-
-+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
-+ unsigned long *best_parent_rate,
-+ struct clk **best_parent_p)
-+{
-+ struct clk *clk = hw->clk, *parent, *best_parent = NULL;
-+ int i, num_parents;
-+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
-+
-+ /* find the parent that can help provide the fastest rate <= rate */
-+ num_parents = __clk_get_num_parents(clk);
-+ for (i = 0; i < num_parents; i++) {
-+ parent = clk_get_parent_by_index(clk, i);
-+ if (!parent)
-+ continue;
-+ if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
-+ parent_rate = __clk_round_rate(parent, rate);
-+ else
-+ parent_rate = __clk_get_rate(parent);
-+
-+ child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
-+
-+ if (child_rate <= rate && child_rate > best_child_rate) {
-+ best_parent = parent;
-+ best = parent_rate;
-+ best_child_rate = child_rate;
-+ }
-+ }
-+
-+ if (best_parent)
-+ *best_parent_p = best_parent;
-+ *best_parent_rate = best;
-+
-+ return best_child_rate;
-+}
-+
- static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct c
- }
-
- const struct clk_ops clk_factors_ops = {
-+ .determine_rate = clk_factors_determine_rate,
- .recalc_rate = clk_factors_recalc_rate,
- .round_rate = clk_factors_round_rate,
- .set_rate = clk_factors_set_rate,
+++ /dev/null
-From d3861805e84e1b54073e20dc499b9380b38bb7ab Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 3 Nov 2013 10:30:12 +0100
-Subject: [PATCH] ARM: sun6i: dt: Add IP needed to bring up the additional
- cores
-
-Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -322,5 +322,15 @@
- #interrupt-cells = <3>;
- interrupts = <1 9 0xf04>;
- };
-+
-+ cpucfg@01f01c00 {
-+ compatible = "allwinner,sun6i-a31-cpuconfig";
-+ reg = <0x01f01c00 0x300>;
-+ };
-+
-+ prcm@01f01c00 {
-+ compatible = "allwinner,sun6i-a31-prcm";
-+ reg = <0x01f01400 0x200>;
-+ };
- };
- };
+++ /dev/null
-From 0aff0370cbffeadc14456556b904c80e30b3717e Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Wed, 1 Jan 2014 10:30:48 +0800
-Subject: [PATCH] ARM: dts: sun7i: external clock outputs
-
-This commit adds the two external clock outputs available on A20 to
-its device tree. A dummy fixed factor clock is also added to serve as
-the first input of the clock outputs, which according to AW's A20 user
-manual, is the 24MHz oscillator divided by 750.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index edad6f1..0d54998 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -303,6 +303,34 @@
- clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
- clock-output-names = "mbus";
- };
-+
-+ /*
-+ * Dummy clock used by output clocks
-+ */
-+ osc24M_32k: clk@1 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-factor-clock";
-+ clock-div = <750>;
-+ clock-mult = <1>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "osc24M_32k";
-+ };
-+
-+ clk_out_a: clk@01c201f0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-out-clk";
-+ reg = <0x01c201f0 0x4>;
-+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-+ clock-output-names = "clk_out_a";
-+ };
-+
-+ clk_out_b: clk@01c201f4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-out-clk";
-+ reg = <0x01c201f4 0x4>;
-+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-+ clock-output-names = "clk_out_b";
-+ };
- };
-
- soc@01c00000 {
---
-1.8.5.5
-
+++ /dev/null
-From dfb12c0c35b6cca5e55f40870b65af87988adb3e Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:41 +0800
-Subject: [PATCH] ARM: dts: sun4i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 30 ++++++++++++++++++++----------
- 1 file changed, 20 insertions(+), 10 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 28273f9..26cf191 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -58,34 +58,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -93,7 +97,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -107,6 +111,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -114,9 +119,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -129,9 +135,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -154,9 +161,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -171,6 +179,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -178,9 +187,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 3dce8324949eaa1ab4b750e8422ce78ddceb7aa4 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:42 +0800
-Subject: [PATCH] ARM: dts: sun5i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 30 ++++++++++++++++++++----------
- arch/arm/boot/dts/sun5i-a13.dtsi | 30 ++++++++++++++++++++----------
- 2 files changed, 40 insertions(+), 20 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 2318082..b114be7 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -51,34 +51,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -86,7 +90,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -100,6 +104,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -107,9 +112,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -122,9 +128,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -143,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -159,6 +167,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -166,9 +175,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 6de40b6..5c121fc 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -52,34 +52,38 @@
- clock-frequency = <0>;
- };
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -87,7 +91,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -101,6 +105,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -108,9 +113,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
-- axi_gates: axi_gates@01c2005c {
-+ axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
-@@ -123,9 +129,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -143,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -158,6 +166,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -165,9 +174,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun5i-a13-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 5cd0fa24e51d342f175d31ecb72c2e957a6bd0af Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:43 +0800
-Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
- 1 file changed, 14 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index fc07f70..d3f1995 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -70,17 +70,19 @@
- clock-frequency = <24000000>;
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
- pll6: clk@01c20028 {
-@@ -103,6 +105,7 @@
- * Allwinner.
- */
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20050 {
-@@ -110,6 +113,7 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20050 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
- ahb1_mux: ahb1_mux@01c20054 {
-@@ -117,6 +121,7 @@
- compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-+ clock-output-names = "ahb1_mux";
- };
-
- ahb1: ahb1@01c20054 {
-@@ -124,9 +129,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1_mux>;
-+ clock-output-names = "ahb1";
- };
-
-- ahb1_gates: ahb1_gates@01c20060 {
-+ ahb1_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -152,9 +158,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c20060 {
-+ apb1_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb1-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -169,6 +176,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
-+ clock-output-names = "apb2_mux";
- };
-
- apb2: apb2@01c20058 {
-@@ -176,9 +184,10 @@
- compatible = "allwinner,sun6i-a31-apb2-div-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb2_mux>;
-+ clock-output-names = "apb2";
- };
-
-- apb2_gates: apb2_gates@01c2006c {
-+ apb2_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-apb2-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From cb6050998de262d5acf2207c5451d4f5995a5bff Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:44 +0800
-Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
-
-Device tree naming conventions state that node names should match
-node function. Change fully functioning clock nodes to match and
-add clock-output-names to all sunxi clock nodes.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
- 1 file changed, 17 insertions(+), 8 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index fe0fe47..cefd7ac 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -54,11 +54,12 @@
- #size-cells = <1>;
- ranges;
-
-- osc24M: osc24M@01c20050 {
-+ osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
- };
-
- osc32k: clk@0 {
-@@ -68,21 +69,23 @@
- clock-output-names = "osc32k";
- };
-
-- pll1: pll1@01c20000 {
-+ pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll1";
- };
-
-- pll4: pll4@01c20018 {
-+ pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
-+ clock-output-names = "pll4";
- };
-
-- pll5: pll5@01c20020 {
-+ pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
-@@ -90,7 +93,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
-- pll6: pll6@01c20028 {
-+ pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
-@@ -103,6 +106,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
-+ clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
-@@ -110,6 +114,7 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
-+ clock-output-names = "axi";
- };
-
- ahb: ahb@01c20054 {
-@@ -117,9 +122,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
-+ clock-output-names = "ahb";
- };
-
-- ahb_gates: ahb_gates@01c20060 {
-+ ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
-@@ -144,9 +150,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
-+ clock-output-names = "apb0";
- };
-
-- apb0_gates: apb0_gates@01c20068 {
-+ apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
-@@ -162,6 +169,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-+ clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
-@@ -169,9 +177,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
-+ clock-output-names = "apb1";
- };
-
-- apb1_gates: apb1_gates@01c2006c {
-+ apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun7i-a20-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
---
-1.8.5.5
-
+++ /dev/null
-From 538d4a6ca5f41039d906f28be82e0f4d26ec8ac9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 23 Dec 2013 00:32:44 -0300
-Subject: [PATCH] ARM: sunxi: dt: add nodes for the mbus clock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-mbus is the memory bus clock, and it is present on both sun5i and sun7i
-machines. Its register layout is compatible with the mod0 one.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 3 files changed, 24 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -257,6 +257,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -258,6 +258,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "ir0";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -290,6 +290,14 @@
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "spi3";
- };
-+
-+ mbus_clk: clk@01c2015c {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c2015c 0x4>;
-+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
-+ clock-output-names = "mbus";
-+ };
- };
-
- soc@01c00000 {
+++ /dev/null
-From 2af807481169af627dc63f98b773c33d85020658 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 15 Nov 2013 15:26:44 -0300
-Subject: [PATCH] ARM: sunxi: dt: add EMAC aliases
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-U-Boot uses the ethernet0 alias to locate the right node to fill in
-the MAC address of the first ethernet interface. This patch adds the
-alias on all the sunxi SoCs with EMAC. In this way, people using
-ethernet in U-Boot (eg, for tftp) can keep a consistent address on both
-U-Boot and Linux with no additional effort.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++++
- 3 files changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -15,6 +15,10 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -16,6 +16,10 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- cpu@0 {
- compatible = "arm,cortex-a8";
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -16,6 +16,10 @@
- / {
- interrupt-parent = <&gic>;
-
-+ aliases {
-+ ethernet0 = &emac;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From dfd4430579f5e53324c00e9e21fb0929bb46542c Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Sat, 7 Dec 2013 01:29:43 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add ethernet alias for GMAC
-
-U-Boot will insert MAC address into the device tree image.
-It looks up ethernet[0-5] aliases to find the ethernet nodes.
-Alias GMAC as ethernet0, as it is the only ethernet controller used.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -17,7 +17,7 @@
- interrupt-parent = <&gic>;
-
- aliases {
-- ethernet0 = &emac;
-+ ethernet0 = &gmac;
- };
-
- cpus {
+++ /dev/null
-From fdc4530902ed845fc0f31b9bbcc45e05fefe21da Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 1 Dec 2013 22:40:34 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add arch timers
-
-Note this requires a new enough uboot, otherwise things won't work, ie:
-
-https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next
-or:
-http://xenbits.xen.org/gitweb/?p=people/ianc/u-boot.git;a=shortlog;h=refs/heads/devel/sunxi-psci
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index f4ecd79..fa2ef07 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -370,6 +370,14 @@
- };
- };
-
-+ timer {
-+ compatible = "arm,armv7-timer";
-+ interrupts = <1 13 0xf08>,
-+ <1 14 0xf08>,
-+ <1 11 0xf08>,
-+ <1 10 0xf08>;
-+ };
-+
- soc@01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
---
-1.8.5.5
-
+++ /dev/null
-From aad62992a2921436ec7c054f8b80bc916b8cc9d7 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 14 Dec 2013 16:26:17 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add new sun5i-a13-olinuxino-micro board
-
-The A13-OLinuXino-MICRO is a small dev-board with the Allwinner A13 SoC:
-https://www.olimex.com/Products/OLinuXino/A13/A13-OLinuXino-MICRO/
-
-Features:
-A13 Cortex A8 processor at 1GHz, 3D Mali400 GPU
-256 MB RAM (128Mbit x 16)
-5VDC input power supply with own ICs, noise immune design
-1 USB host
-1 USB OTG which can power the board
-SD-card connector for booting the Linux image
-VGA video output
-LCD signals available on connector so you still can use LCD if you disable VGA/HDMI
-Audio output
-Microphone input pads (no connector)
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 68 +++++++++++++++++++++++++
- 2 files changed, 69 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -255,6 +255,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-hackberry.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
-+ sun5i-a13-olinuxino-micro.dtb \
- sun6i-a31-colombus.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright 2012 Maxime Ripard
-+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun5i-a13.dtsi"
-+
-+/ {
-+ model = "Olimex A13-Olinuxino Micro";
-+ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
-+
-+ soc@01c00000 {
-+ pinctrl@01c20800 {
-+ led_pins_olinuxinom: led_pins@0 {
-+ allwinner,pins = "PG9";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <1>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+
-+ uart1: serial@01c28400 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1_pins_b>;
-+ status = "okay";
-+ };
-+
-+ i2c0: i2c@01c2ac00 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c1: i2c@01c2b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c1_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c2: i2c@01c2b400 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c2_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_pins_olinuxinom>;
-+
-+ power {
-+ label = "a13-olinuxino-micro:green:power";
-+ gpios = <&pio 6 9 0>;
-+ default-state = "on";
-+ };
-+ };
-+};
+++ /dev/null
-From c6890cadc2129a07d69f3dcbfca66522c27b8069 Mon Sep 17 00:00:00 2001
-From: Carlo Caione <carlo.caione@gmail.com>
-Date: Sat, 16 Nov 2013 18:33:54 +0100
-Subject: [PATCH] ARM: sun4i/sun7i: RTC driver
-
-This patch introduces the driver for the RTC in the Allwinner A10 and
-A20 SoCs.
-
-Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
-Acked-by: Alessandro Zummo <a.zummo@towertech.it>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/rtc/Kconfig | 7 +
- drivers/rtc/Makefile | 1 +
- drivers/rtc/rtc-sunxi.c | 523 ++++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 531 insertions(+)
- create mode 100644 drivers/rtc/rtc-sunxi.c
-
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -1122,6 +1122,13 @@ config RTC_DRV_SUN4V
- If you say Y here you will get support for the Hypervisor
- based RTC on SUN4V systems.
-
-+config RTC_DRV_SUNXI
-+ tristate "Allwinner sun4i/sun7i RTC"
-+ depends on ARCH_SUNXI
-+ help
-+ If you say Y here you will get support for the RTC found on
-+ Allwinner A10/A20.
-+
- config RTC_DRV_STARFIRE
- bool "Starfire RTC"
- depends on SPARC64
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -119,6 +119,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-st
- obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
- obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
- obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
-+obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
- obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
- obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
- obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
---- /dev/null
-+++ b/drivers/rtc/rtc-sunxi.c
-@@ -0,0 +1,523 @@
-+/*
-+ * An RTC driver for Allwinner A10/A20
-+ *
-+ * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+#include <linux/types.h>
-+
-+#define SUNXI_LOSC_CTRL 0x0000
-+#define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8)
-+#define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7)
-+
-+#define SUNXI_RTC_YMD 0x0004
-+
-+#define SUNXI_RTC_HMS 0x0008
-+
-+#define SUNXI_ALRM_DHMS 0x000c
-+
-+#define SUNXI_ALRM_EN 0x0014
-+#define SUNXI_ALRM_EN_CNT_EN BIT(8)
-+
-+#define SUNXI_ALRM_IRQ_EN 0x0018
-+#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
-+
-+#define SUNXI_ALRM_IRQ_STA 0x001c
-+#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
-+
-+#define SUNXI_MASK_DH 0x0000001f
-+#define SUNXI_MASK_SM 0x0000003f
-+#define SUNXI_MASK_M 0x0000000f
-+#define SUNXI_MASK_LY 0x00000001
-+#define SUNXI_MASK_D 0x00000ffe
-+#define SUNXI_MASK_M 0x0000000f
-+
-+#define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \
-+ >> (shift))
-+
-+#define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift))
-+
-+/*
-+ * Get date values
-+ */
-+#define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0)
-+#define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8)
-+#define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16)
-+
-+/*
-+ * Get time values
-+ */
-+#define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
-+#define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Get alarm values
-+ */
-+#define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0)
-+#define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Set date values
-+ */
-+#define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x)
-+#define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8)
-+#define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16)
-+#define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift)
-+
-+/*
-+ * Set time values
-+ */
-+#define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x)
-+#define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
-+
-+/*
-+ * Set alarm values
-+ */
-+#define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x)
-+#define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8)
-+#define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16)
-+#define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21)
-+
-+/*
-+ * Time unit conversions
-+ */
-+#define SEC_IN_MIN 60
-+#define SEC_IN_HOUR (60 * SEC_IN_MIN)
-+#define SEC_IN_DAY (24 * SEC_IN_HOUR)
-+
-+/*
-+ * The year parameter passed to the driver is usually an offset relative to
-+ * the year 1900. This macro is used to convert this offset to another one
-+ * relative to the minimum year allowed by the hardware.
-+ */
-+#define SUNXI_YEAR_OFF(x) ((x)->min - 1900)
-+
-+/*
-+ * min and max year are arbitrary set considering the limited range of the
-+ * hardware register field
-+ */
-+struct sunxi_rtc_data_year {
-+ unsigned int min; /* min year allowed */
-+ unsigned int max; /* max year allowed */
-+ unsigned int mask; /* mask for the year field */
-+ unsigned char leap_shift; /* bit shift to get the leap year */
-+};
-+
-+static struct sunxi_rtc_data_year data_year_param[] = {
-+ [0] = {
-+ .min = 2010,
-+ .max = 2073,
-+ .mask = 0x3f,
-+ .leap_shift = 22,
-+ },
-+ [1] = {
-+ .min = 1970,
-+ .max = 2225,
-+ .mask = 0xff,
-+ .leap_shift = 24,
-+ },
-+};
-+
-+struct sunxi_rtc_dev {
-+ struct rtc_device *rtc;
-+ struct device *dev;
-+ struct sunxi_rtc_data_year *data_year;
-+ void __iomem *base;
-+ int irq;
-+};
-+
-+static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
-+{
-+ struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
-+ u32 val;
-+
-+ val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
-+
-+ if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
-+ val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
-+ writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
-+
-+ rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
-+
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static void sunxi_rtc_setaie(int to, struct sunxi_rtc_dev *chip)
-+{
-+ u32 alrm_val = 0;
-+ u32 alrm_irq_val = 0;
-+
-+ if (to) {
-+ alrm_val = readl(chip->base + SUNXI_ALRM_EN);
-+ alrm_val |= SUNXI_ALRM_EN_CNT_EN;
-+
-+ alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
-+ alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
-+ } else {
-+ writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
-+ chip->base + SUNXI_ALRM_IRQ_STA);
-+ }
-+
-+ writel(alrm_val, chip->base + SUNXI_ALRM_EN);
-+ writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
-+}
-+
-+static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ struct rtc_time *alrm_tm = &wkalrm->time;
-+ u32 alrm;
-+ u32 alrm_en;
-+ u32 date;
-+
-+ alrm = readl(chip->base + SUNXI_ALRM_DHMS);
-+ date = readl(chip->base + SUNXI_RTC_YMD);
-+
-+ alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
-+ alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
-+ alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
-+
-+ alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
-+ alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
-+ alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
-+ chip->data_year->mask);
-+
-+ alrm_tm->tm_mon -= 1;
-+
-+ /*
-+ * switch from (data_year->min)-relative offset to
-+ * a (1900)-relative one
-+ */
-+ alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
-+
-+ alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
-+ if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
-+ wkalrm->enabled = 1;
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ u32 date, time;
-+
-+ /*
-+ * read again in case it changes
-+ */
-+ do {
-+ date = readl(chip->base + SUNXI_RTC_YMD);
-+ time = readl(chip->base + SUNXI_RTC_HMS);
-+ } while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
-+ (time != readl(chip->base + SUNXI_RTC_HMS)));
-+
-+ rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time);
-+ rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time);
-+ rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
-+
-+ rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
-+ rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
-+ rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
-+ chip->data_year->mask);
-+
-+ rtc_tm->tm_mon -= 1;
-+
-+ /*
-+ * switch from (data_year->min)-relative offset to
-+ * a (1900)-relative one
-+ */
-+ rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
-+
-+ return rtc_valid_tm(rtc_tm);
-+}
-+
-+static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ struct rtc_time *alrm_tm = &wkalrm->time;
-+ struct rtc_time tm_now;
-+ u32 alrm = 0;
-+ unsigned long time_now = 0;
-+ unsigned long time_set = 0;
-+ unsigned long time_gap = 0;
-+ unsigned long time_gap_day = 0;
-+ unsigned long time_gap_hour = 0;
-+ unsigned long time_gap_min = 0;
-+ int ret = 0;
-+
-+ ret = sunxi_rtc_gettime(dev, &tm_now);
-+ if (ret < 0) {
-+ dev_err(dev, "Error in getting time\n");
-+ return -EINVAL;
-+ }
-+
-+ rtc_tm_to_time(alrm_tm, &time_set);
-+ rtc_tm_to_time(&tm_now, &time_now);
-+ if (time_set <= time_now) {
-+ dev_err(dev, "Date to set in the past\n");
-+ return -EINVAL;
-+ }
-+
-+ time_gap = time_set - time_now;
-+ time_gap_day = time_gap / SEC_IN_DAY;
-+ time_gap -= time_gap_day * SEC_IN_DAY;
-+ time_gap_hour = time_gap / SEC_IN_HOUR;
-+ time_gap -= time_gap_hour * SEC_IN_HOUR;
-+ time_gap_min = time_gap / SEC_IN_MIN;
-+ time_gap -= time_gap_min * SEC_IN_MIN;
-+
-+ if (time_gap_day > 255) {
-+ dev_err(dev, "Day must be in the range 0 - 255\n");
-+ return -EINVAL;
-+ }
-+
-+ sunxi_rtc_setaie(0, chip);
-+ writel(0, chip->base + SUNXI_ALRM_DHMS);
-+ usleep_range(100, 300);
-+
-+ alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
-+ SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
-+ SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
-+ SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
-+ writel(alrm, chip->base + SUNXI_ALRM_DHMS);
-+
-+ writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
-+ writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
-+
-+ sunxi_rtc_setaie(wkalrm->enabled, chip);
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
-+ unsigned int mask, unsigned int ms_timeout)
-+{
-+ const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
-+ u32 reg;
-+
-+ do {
-+ reg = readl(chip->base + offset);
-+ reg &= mask;
-+
-+ if (reg == mask)
-+ return 0;
-+
-+ } while (time_before(jiffies, timeout));
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+ u32 date = 0;
-+ u32 time = 0;
-+ int year;
-+
-+ /*
-+ * the input rtc_tm->tm_year is the offset relative to 1900. We use
-+ * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
-+ * allowed by the hardware
-+ */
-+
-+ year = rtc_tm->tm_year + 1900;
-+ if (year < chip->data_year->min || year > chip->data_year->max) {
-+ dev_err(dev, "rtc only supports year in range %d - %d\n",
-+ chip->data_year->min, chip->data_year->max);
-+ return -EINVAL;
-+ }
-+
-+ rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
-+ rtc_tm->tm_mon += 1;
-+
-+ date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
-+ SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
-+ SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
-+ chip->data_year->mask);
-+
-+ if (is_leap_year(year))
-+ date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
-+
-+ time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
-+ SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
-+ SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
-+
-+ writel(0, chip->base + SUNXI_RTC_HMS);
-+ writel(0, chip->base + SUNXI_RTC_YMD);
-+
-+ writel(time, chip->base + SUNXI_RTC_HMS);
-+
-+ /*
-+ * After writing the RTC HH-MM-SS register, the
-+ * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
-+ * be cleared until the real writing operation is finished
-+ */
-+
-+ if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
-+ SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
-+ dev_err(dev, "Failed to set rtc time.\n");
-+ return -1;
-+ }
-+
-+ writel(date, chip->base + SUNXI_RTC_YMD);
-+
-+ /*
-+ * After writing the RTC YY-MM-DD register, the
-+ * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
-+ * be cleared until the real writing operation is finished
-+ */
-+
-+ if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
-+ SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
-+ dev_err(dev, "Failed to set rtc time.\n");
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
-+{
-+ struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
-+
-+ if (!enabled)
-+ sunxi_rtc_setaie(enabled, chip);
-+
-+ return 0;
-+}
-+
-+static const struct rtc_class_ops sunxi_rtc_ops = {
-+ .read_time = sunxi_rtc_gettime,
-+ .set_time = sunxi_rtc_settime,
-+ .read_alarm = sunxi_rtc_getalarm,
-+ .set_alarm = sunxi_rtc_setalarm,
-+ .alarm_irq_enable = sunxi_rtc_alarm_irq_enable
-+};
-+
-+static const struct of_device_id sunxi_rtc_dt_ids[] = {
-+ { .compatible = "allwinner,sun4i-rtc", .data = &data_year_param[0] },
-+ { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
-+
-+static int sunxi_rtc_probe(struct platform_device *pdev)
-+{
-+ struct sunxi_rtc_dev *chip;
-+ struct resource *res;
-+ const struct of_device_id *of_id;
-+ int ret;
-+
-+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
-+ if (!chip)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, chip);
-+ chip->dev = &pdev->dev;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ chip->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(chip->base))
-+ return PTR_ERR(chip->base);
-+
-+ chip->irq = platform_get_irq(pdev, 0);
-+ if (chip->irq < 0) {
-+ dev_err(&pdev->dev, "No IRQ resource\n");
-+ return chip->irq;
-+ }
-+ ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
-+ 0, dev_name(&pdev->dev), chip);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Could not request IRQ\n");
-+ return ret;
-+ }
-+
-+ of_id = of_match_device(sunxi_rtc_dt_ids, &pdev->dev);
-+ if (!of_id) {
-+ dev_err(&pdev->dev, "Unable to setup RTC data\n");
-+ return -ENODEV;
-+ }
-+ chip->data_year = (struct sunxi_rtc_data_year *) of_id->data;
-+
-+ /* clear the alarm count value */
-+ writel(0, chip->base + SUNXI_ALRM_DHMS);
-+
-+ /* disable alarm, not generate irq pending */
-+ writel(0, chip->base + SUNXI_ALRM_EN);
-+
-+ /* disable alarm week/cnt irq, unset to cpu */
-+ writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
-+
-+ /* clear alarm week/cnt irq pending */
-+ writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
-+ SUNXI_ALRM_IRQ_STA);
-+
-+ chip->rtc = rtc_device_register("rtc-sunxi", &pdev->dev,
-+ &sunxi_rtc_ops, THIS_MODULE);
-+ if (IS_ERR(chip->rtc)) {
-+ dev_err(&pdev->dev, "unable to register device\n");
-+ return PTR_ERR(chip->rtc);
-+ }
-+
-+ dev_info(&pdev->dev, "RTC enabled\n");
-+
-+ return 0;
-+}
-+
-+static int sunxi_rtc_remove(struct platform_device *pdev)
-+{
-+ struct sunxi_rtc_dev *chip = platform_get_drvdata(pdev);
-+
-+ rtc_device_unregister(chip->rtc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_rtc_driver = {
-+ .probe = sunxi_rtc_probe,
-+ .remove = sunxi_rtc_remove,
-+ .driver = {
-+ .name = "sunxi-rtc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sunxi_rtc_dt_ids,
-+ },
-+};
-+
-+module_platform_driver(sunxi_rtc_driver);
-+
-+MODULE_DESCRIPTION("sunxi RTC driver");
-+MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From b15b9f68606134222f7aff5120c8ef70ffab92b8 Mon Sep 17 00:00:00 2001
-From: Carlo Caione <carlo.caione@gmail.com>
-Date: Wed, 16 Oct 2013 20:30:26 +0200
-Subject: [PATCH] ARM: dts: sun4i/sun7i: add RTC node
-
-Add the RTC node to DTS for Allwinner A10 and Allwinner A20.
-
-Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++
- 2 files changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -412,6 +412,12 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ rtc: rtc@01c20d00 {
-+ compatible = "allwinner,sun4i-rtc";
-+ reg = <0x01c20d00 0x20>;
-+ interrupts = <24>;
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -416,6 +416,12 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ rtc: rtc@01c20d00 {
-+ compatible = "allwinner,sun7i-a20-rtc";
-+ reg = <0x01c20d00 0x20>;
-+ interrupts = <0 24 1>;
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun7i-a20-sid";
- reg = <0x01c23800 0x200>;
+++ /dev/null
-From 3bf30f6381f9287eb99ce096bf2fa327a69c8a71 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] clocksource: Add Allwinner SoCs HS timers driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Most of the Allwinner SoCs (at this time, all but the A10) also have a
-High Speed timers that are not using the 24MHz oscillator as a source
-but rather the AHB clock running much faster.
-
-The IP is slightly different between the A10s/A13 and the one used in
-the A20/A31, since the latter have 4 timers available, while the former
-have only 2 of them.
-
-[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
- alphabetically"
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- .../bindings/timer/allwinner,sun5i-a13-hstimer.txt | 22 +++
- arch/arm/mach-sunxi/Kconfig | 1 +
- drivers/clocksource/Kconfig | 4 +
- drivers/clocksource/Makefile | 1 +
- drivers/clocksource/timer-sun5i.c | 192 +++++++++++++++++++++
- 5 files changed, 220 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
- create mode 100644 drivers/clocksource/timer-sun5i.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-@@ -0,0 +1,22 @@
-+Allwinner SoCs High Speed Timer Controller
-+
-+Required properties:
-+
-+- compatible : should be "allwinner,sun5i-a13-hstimer" or
-+ "allwinner,sun7i-a20-hstimer"
-+- reg : Specifies base physical address and size of the registers.
-+- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
-+ one)
-+- clocks: phandle to the source clock (usually the AHB clock)
-+
-+Example:
-+
-+timer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 51 1>,
-+ <0 52 1>,
-+ <0 53 1>,
-+ <0 54 1>;
-+ clocks = <&ahb1_gates 19>;
-+};
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -13,3 +13,4 @@ config ARCH_SUNXI
- select PINCTRL_SUNXI
- select SPARSE_IRQ
- select SUN4I_TIMER
-+ select SUN5I_HSTIMER
---- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -37,6 +37,10 @@ config SUN4I_TIMER
- select CLKSRC_MMIO
- bool
-
-+config SUN5I_HSTIMER
-+ select CLKSRC_MMIO
-+ bool
-+
- config VT8500_TIMER
- bool
-
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART) += moxart_time
- obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
- obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
- obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
-+obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
- obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
- obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
- obj-$(CONFIG_ARCH_NSPIRE) += zevio-timer.o
---- /dev/null
-+++ b/drivers/clocksource/timer-sun5i.c
-@@ -0,0 +1,192 @@
-+/*
-+ * Allwinner SoCs hstimer driver.
-+ *
-+ * Copyright (C) 2013 Maxime Ripard
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clockchips.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/irqreturn.h>
-+#include <linux/sched_clock.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+
-+#define TIMER_IRQ_EN_REG 0x00
-+#define TIMER_IRQ_EN(val) BIT(val)
-+#define TIMER_IRQ_ST_REG 0x04
-+#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
-+#define TIMER_CTL_ENABLE BIT(0)
-+#define TIMER_CTL_RELOAD BIT(1)
-+#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
-+#define TIMER_CTL_ONESHOT BIT(7)
-+#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
-+#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
-+#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
-+#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
-+
-+#define TIMER_SYNC_TICKS 3
-+
-+static void __iomem *timer_base;
-+static u32 ticks_per_jiffy;
-+
-+/*
-+ * When we disable a timer, we need to wait at least for 2 cycles of
-+ * the timer source clock. We will use for that the clocksource timer
-+ * that is already setup and runs at the same frequency than the other
-+ * timers, and we never will be disabled.
-+ */
-+static void sun5i_clkevt_sync(void)
-+{
-+ u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
-+
-+ while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
-+ cpu_relax();
-+}
-+
-+static void sun5i_clkevt_time_stop(u8 timer)
-+{
-+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
-+ writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
-+
-+ sun5i_clkevt_sync();
-+}
-+
-+static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
-+{
-+ writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
-+}
-+
-+static void sun5i_clkevt_time_start(u8 timer, bool periodic)
-+{
-+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
-+
-+ if (periodic)
-+ val &= ~TIMER_CTL_ONESHOT;
-+ else
-+ val |= TIMER_CTL_ONESHOT;
-+
-+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-+ timer_base + TIMER_CTL_REG(timer));
-+}
-+
-+static void sun5i_clkevt_mode(enum clock_event_mode mode,
-+ struct clock_event_device *clk)
-+{
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_PERIODIC:
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_setup(0, ticks_per_jiffy);
-+ sun5i_clkevt_time_start(0, true);
-+ break;
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_start(0, false);
-+ break;
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ default:
-+ sun5i_clkevt_time_stop(0);
-+ break;
-+ }
-+}
-+
-+static int sun5i_clkevt_next_event(unsigned long evt,
-+ struct clock_event_device *unused)
-+{
-+ sun5i_clkevt_time_stop(0);
-+ sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
-+ sun5i_clkevt_time_start(0, false);
-+
-+ return 0;
-+}
-+
-+static struct clock_event_device sun5i_clockevent = {
-+ .name = "sun5i_tick",
-+ .rating = 340,
-+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-+ .set_mode = sun5i_clkevt_mode,
-+ .set_next_event = sun5i_clkevt_next_event,
-+};
-+
-+
-+static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
-+{
-+ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-+
-+ writel(0x1, timer_base + TIMER_IRQ_ST_REG);
-+ evt->event_handler(evt);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction sun5i_timer_irq = {
-+ .name = "sun5i_timer0",
-+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
-+ .handler = sun5i_timer_interrupt,
-+ .dev_id = &sun5i_clockevent,
-+};
-+
-+static u32 sun5i_timer_sched_read(void)
-+{
-+ return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
-+}
-+
-+static void __init sun5i_timer_init(struct device_node *node)
-+{
-+ unsigned long rate;
-+ struct clk *clk;
-+ int ret, irq;
-+ u32 val;
-+
-+ timer_base = of_iomap(node, 0);
-+ if (!timer_base)
-+ panic("Can't map registers");
-+
-+ irq = irq_of_parse_and_map(node, 0);
-+ if (irq <= 0)
-+ panic("Can't parse IRQ");
-+
-+ clk = of_clk_get(node, 0);
-+ if (IS_ERR(clk))
-+ panic("Can't get timer clock");
-+ clk_prepare_enable(clk);
-+ rate = clk_get_rate(clk);
-+
-+ writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
-+ writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
-+ timer_base + TIMER_CTL_REG(1));
-+
-+ setup_sched_clock(sun5i_timer_sched_read, 32, rate);
-+ clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
-+ rate, 340, 32, clocksource_mmio_readl_down);
-+
-+ ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
-+
-+ ret = setup_irq(irq, &sun5i_timer_irq);
-+ if (ret)
-+ pr_warn("failed to setup irq %d\n", irq);
-+
-+ /* Enable timer0 interrupt */
-+ val = readl(timer_base + TIMER_IRQ_EN_REG);
-+ writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-+
-+ sun5i_clockevent.cpumask = cpu_possible_mask;
-+ sun5i_clockevent.irq = irq;
-+
-+ clockevents_config_and_register(&sun5i_clockevent, rate,
-+ TIMER_SYNC_TICKS, 0xffffffff);
-+}
-+CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
-+ sun5i_timer_init);
-+CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
-+ sun5i_timer_init);
+++ /dev/null
-From 5ace5467690055b1772dcac69dd1377735b8a34b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun5i: a10s: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A10s has support for two high speed timers. Now that we
-have a driver to support it, we can enable them in the device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -454,5 +454,12 @@
- clock-frequency = <100000>;
- status = "disabled";
- };
-+
-+ timer@01c60000 {
-+ compatible = "allwinner,sun5i-a13-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <82>, <83>;
-+ clocks = <&ahb_gates 28>;
-+ };
- };
- };
+++ /dev/null
-From 22a3eff19679e0e592e061201690670a2f5fdba7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun5i: a13: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A13 has support for two high speed timers. Now that we
-have a driver to support it, we can enable them in the device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -391,5 +391,12 @@
- clock-frequency = <100000>;
- status = "disabled";
- };
-+
-+ timer@01c60000 {
-+ compatible = "allwinner,sun5i-a13-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <82>, <83>;
-+ clocks = <&ahb_gates 28>;
-+ };
- };
- };
+++ /dev/null
-From 6c23e1fa6bd220b8f5665c150c83d4c016d95482 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 7 Nov 2013 12:01:48 +0100
-Subject: [PATCH] ARM: sun7i: a20: Add support for the High Speed Timers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Allwinner A20 has support for four high speed timers. Apart for the
-number of timers (4 vs 2), it's basically the same logic than the high
-speed timers found in the sun5i chips.
-
-Now that we have a driver to support it, we can enable them in the
-device tree.
-
-[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Tested-by: Emilio López <emilio@elopez.com.ar>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -552,6 +552,16 @@
- status = "disabled";
- };
-
-+ hstimer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 81 4>,
-+ <0 82 4>,
-+ <0 83 4>,
-+ <0 84 4>;
-+ clocks = <&ahb_gates 28>;
-+ };
-+
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From 28a9c5d93113cab73dd3a4b4a74a983151c08b9d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:09 +0100
-Subject: [PATCH] ARM: sun6i: a31: Add support for the High Speed Timers
-
-The Allwinner A31 has support for four high speed timers. Apart for the
-number of timers (4 vs 2), it's basically the same logic than the high
-speed timers found in the sun5i chips.
-
-Now that we have a driver to support it, we can enable them in the
-device tree.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -312,6 +312,17 @@
- status = "disabled";
- };
-
-+ hstimer@01c60000 {
-+ compatible = "allwinner,sun7i-a20-hstimer";
-+ reg = <0x01c60000 0x1000>;
-+ interrupts = <0 51 4>,
-+ <0 52 4>,
-+ <0 53 4>,
-+ <0 54 4>;
-+ clocks = <&ahb1_gates 19>;
-+ resets = <&ahb1_rst 19>;
-+ };
-+
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
+++ /dev/null
-From bc7a0478e6dac1304fdfdb6f3056f438b632da62 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:48 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI
-
-The GMAC uses 1 of 2 sources for its transmit clock, depending on the
-PHY interface mode. Add both sources as dummy clocks, and as parents
-to the GMAC clock node.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index cefd7ac..7d98edc 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -322,6 +322,34 @@
- };
-
- /*
-+ * The following two are dummy clocks, placeholders used in the gmac_tx
-+ * clock. The gmac driver will choose one parent depending on the PHY
-+ * interface mode, using clk_set_rate auto-reparenting.
-+ * The actual TX clock rate is not controlled by the gmac_tx clock.
-+ */
-+ mii_phy_tx_clk: clk@2 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <25000000>;
-+ clock-output-names = "mii_phy_tx";
-+ };
-+
-+ gmac_int_tx_clk: clk@3 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_int_tx";
-+ };
-+
-+ gmac_tx_clk: clk@01c20164 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-gmac-clk";
-+ reg = <0x01c20164 0x4>;
-+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
-+ clock-output-names = "gmac_tx";
-+ };
-+
-+ /*
- * Dummy clock used by output clocks
- */
- osc24M_32k: clk@1 {
---
-1.8.5.5
-
+++ /dev/null
-From 7584e81f6d9fecf0ad6e2854654b183432adb918 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:49 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 7d98edc..87eab0d 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -645,6 +645,21 @@
- status = "disabled";
- };
-
-+ gmac: ethernet@01c50000 {
-+ compatible = "allwinner,sun7i-a20-gmac";
-+ reg = <0x01c50000 0x10000>;
-+ interrupts = <0 85 4>;
-+ interrupt-names = "macirq";
-+ clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
-+ clock-names = "stmmaceth", "allwinner_gmac_tx";
-+ snps,pbl = <2>;
-+ snps,fixed-burst;
-+ snps,force_sf_dma_mode;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- hstimer@01c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
---
-1.8.5.5
-
+++ /dev/null
-From 249ac8d24efdc07f521b796b96796ffa55abe0a5 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:50 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add pin muxing options for the GMAC
-
-The A20 has EMAC and GMAC muxed on the same pins.
-Add pin sets with gmac function for MII and RGMII mode to the DTSI.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 87eab0d..9bb6fdf 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -484,6 +484,32 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ gmac_pins_mii_a: gmac_mii@0 {
-+ allwinner,pins = "PA0", "PA1", "PA2",
-+ "PA3", "PA4", "PA5", "PA6",
-+ "PA7", "PA8", "PA9", "PA10",
-+ "PA11", "PA12", "PA13", "PA14",
-+ "PA15", "PA16";
-+ allwinner,function = "gmac";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ gmac_pins_rgmii_a: gmac_rgmii@0 {
-+ allwinner,pins = "PA0", "PA1", "PA2",
-+ "PA3", "PA4", "PA5", "PA6",
-+ "PA7", "PA8", "PA10",
-+ "PA11", "PA12", "PA13",
-+ "PA15", "PA16";
-+ allwinner,function = "gmac";
-+ /*
-+ * data lines in RGMII mode use DDR mode
-+ * and need a higher signal drive strength
-+ */
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 33ba4079ea8c611c1aeca34f2d6d53a8214c14c5 Mon Sep 17 00:00:00 2001
-From: Rashika Kheria <rashika.kheria@gmail.com>
-Date: Thu, 19 Dec 2013 14:19:44 +0530
-Subject: [PATCH] drivers: net: Mark functions as static in stmmac_platform.c
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This patch marks the function stmmac_pltfr_freeze() and
-stmmac_pltfr_restore() in stmmac_platform.c as static because they are
-not used outside this file.
-
-Thus, it also removes the following warnings in
-ethernet/stmicro/stmmac/stmmac_platform.c:
-
-drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:222:5: warning: no previous prototype for ‘stmmac_pltfr_freeze’ [-Wmissing-prototypes]
-drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c:236:5: warning: no previous prototype for ‘stmmac_pltfr_restore’ [-Wmissing-prototypes]
-
-Signed-off-by: Rashika Kheria <rashika.kheria@gmail.com>
-Reviewed-by: Josh Triplett <josh@joshtriplett.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 51c9069..38bd1f4 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -219,7 +219,7 @@ static int stmmac_pltfr_resume(struct device *dev)
- return stmmac_resume(ndev);
- }
-
--int stmmac_pltfr_freeze(struct device *dev)
-+static int stmmac_pltfr_freeze(struct device *dev)
- {
- int ret;
- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
-@@ -233,7 +233,7 @@ int stmmac_pltfr_freeze(struct device *dev)
- return ret;
- }
-
--int stmmac_pltfr_restore(struct device *dev)
-+static int stmmac_pltfr_restore(struct device *dev)
- {
- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
---
-1.8.5.5
-
+++ /dev/null
-From 9cbadf094d9d479413dc8cfa77dff9e732184337 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:51:43 +0000
-Subject: [PATCH] net: stmmac: support max-speed device tree property
-
-This patch adds support to "max-speed" property which is a standard
-Ethernet device tree property. max-speed specifies maximum speed
-(specified in megabits per second) supported the device.
-
-Depending on the clocking schemes some of the boards can only support
-few link speeds, so having a way to limit the link speed in the mac
-driver would allow such setups to work reliably.
-
-Without this patch there is no way to tell the driver to limit the
-link speed.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +++-
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++
- include/linux/stmmac.h | 1 +
- 3 files changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index ecdc8ab..15192c0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -776,6 +776,7 @@ static int stmmac_init_phy(struct net_device *dev)
- char phy_id_fmt[MII_BUS_ID_SIZE + 3];
- char bus_id[MII_BUS_ID_SIZE];
- int interface = priv->plat->interface;
-+ int max_speed = priv->plat->max_speed;
- priv->oldlink = 0;
- priv->speed = 0;
- priv->oldduplex = -1;
-@@ -800,7 +801,8 @@ static int stmmac_init_phy(struct net_device *dev)
-
- /* Stop Advertising 1000BASE Capability if interface is not GMII */
- if ((interface == PHY_INTERFACE_MODE_MII) ||
-- (interface == PHY_INTERFACE_MODE_RMII))
-+ (interface == PHY_INTERFACE_MODE_RMII) ||
-+ (max_speed < 1000 && max_speed > 0))
- phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
- SUPPORTED_1000baseT_Full);
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 38bd1f4..9377ee6 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -42,6 +42,10 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- *mac = of_get_mac_address(np);
- plat->interface = of_get_phy_mode(np);
-
-+ /* Get max speed of operation from device tree */
-+ if (of_property_read_u32(np, "max-speed", &plat->max_speed))
-+ plat->max_speed = -1;
-+
- plat->bus_id = of_alias_get_id(np, "ethernet");
- if (plat->bus_id < 0)
- plat->bus_id = 0;
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index bb5deb0..33ace71 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -110,6 +110,7 @@ struct plat_stmmacenet_data {
- int force_sf_dma_mode;
- int force_thresh_dma_mode;
- int riwt_off;
-+ int max_speed;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
- int (*init)(struct platform_device *pdev);
---
-1.8.5.5
-
+++ /dev/null
-From 984203ceff27e9d6d94fbae4b043fc9afb658121 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:51:58 +0000
-Subject: [PATCH] net: stmmac: mdio: remove reset gpio free
-
-This patch removes gpio_free for reset line of the phy, driver stores
-the gpio number in its private data-structure to use in future. As the
-driver uses this pin in future this pin should not be freed.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-index fe7bc99..aab12d2 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-@@ -166,7 +166,6 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
- udelay(data->delays[1]);
- gpio_set_value(reset_gpio, active_low ? 1 : 0);
- udelay(data->delays[2]);
-- gpio_free(reset_gpio);
- }
- }
- #endif
---
-1.8.5.5
-
+++ /dev/null
-From 09f8d6960b69e474eef9d2aebdd0d536d00af0c8 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:06 +0000
-Subject: [PATCH] net: stmmac: move dma allocation to new function
-
-This patch moves dma resource allocation to a new function
-alloc_dma_desc_resources, the reason for moving this to a new function
-is to keep the memory allocations in a separate function. One more reason
-it to get suspend and hibernation cases working without releasing and
-allocating these resources during suspend-resume and freeze-restore
-cases.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 169 +++++++++++-----------
- 1 file changed, 85 insertions(+), 84 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 15192c0..532f2b4 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -996,66 +996,6 @@ static int init_dma_desc_rings(struct net_device *dev)
- pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
- txsize, rxsize, bfsize);
-
-- if (priv->extend_desc) {
-- priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
-- sizeof(struct
-- dma_extended_desc),
-- &priv->dma_rx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_erx)
-- goto err_dma;
--
-- priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
-- sizeof(struct
-- dma_extended_desc),
-- &priv->dma_tx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_etx) {
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_erx, priv->dma_rx_phy);
-- goto err_dma;
-- }
-- } else {
-- priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
-- sizeof(struct dma_desc),
-- &priv->dma_rx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_rx)
-- goto err_dma;
--
-- priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
-- sizeof(struct dma_desc),
-- &priv->dma_tx_phy,
-- GFP_KERNEL);
-- if (!priv->dma_tx) {
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_desc),
-- priv->dma_rx, priv->dma_rx_phy);
-- goto err_dma;
-- }
-- }
--
-- priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
-- GFP_KERNEL);
-- if (!priv->rx_skbuff_dma)
-- goto err_rx_skbuff_dma;
--
-- priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
-- GFP_KERNEL);
-- if (!priv->rx_skbuff)
-- goto err_rx_skbuff;
--
-- priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
-- GFP_KERNEL);
-- if (!priv->tx_skbuff_dma)
-- goto err_tx_skbuff_dma;
--
-- priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
-- GFP_KERNEL);
-- if (!priv->tx_skbuff)
-- goto err_tx_skbuff;
--
- if (netif_msg_probe(priv)) {
- pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
- (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
-@@ -1123,30 +1063,6 @@ static int init_dma_desc_rings(struct net_device *dev)
- err_init_rx_buffers:
- while (--i >= 0)
- stmmac_free_rx_buffers(priv, i);
-- kfree(priv->tx_skbuff);
--err_tx_skbuff:
-- kfree(priv->tx_skbuff_dma);
--err_tx_skbuff_dma:
-- kfree(priv->rx_skbuff);
--err_rx_skbuff:
-- kfree(priv->rx_skbuff_dma);
--err_rx_skbuff_dma:
-- if (priv->extend_desc) {
-- dma_free_coherent(priv->device, priv->dma_tx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_etx, priv->dma_tx_phy);
-- dma_free_coherent(priv->device, priv->dma_rx_size *
-- sizeof(struct dma_extended_desc),
-- priv->dma_erx, priv->dma_rx_phy);
-- } else {
-- dma_free_coherent(priv->device,
-- priv->dma_tx_size * sizeof(struct dma_desc),
-- priv->dma_tx, priv->dma_tx_phy);
-- dma_free_coherent(priv->device,
-- priv->dma_rx_size * sizeof(struct dma_desc),
-- priv->dma_rx, priv->dma_rx_phy);
-- }
--err_dma:
- return ret;
- }
-
-@@ -1182,6 +1098,85 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv)
- }
- }
-
-+static int alloc_dma_desc_resources(struct stmmac_priv *priv)
-+{
-+ unsigned int txsize = priv->dma_tx_size;
-+ unsigned int rxsize = priv->dma_rx_size;
-+ int ret = -ENOMEM;
-+
-+ priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
-+ GFP_KERNEL);
-+ if (!priv->rx_skbuff_dma)
-+ return -ENOMEM;
-+
-+ priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
-+ GFP_KERNEL);
-+ if (!priv->rx_skbuff)
-+ goto err_rx_skbuff;
-+
-+ priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
-+ GFP_KERNEL);
-+ if (!priv->tx_skbuff_dma)
-+ goto err_tx_skbuff_dma;
-+
-+ priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
-+ GFP_KERNEL);
-+ if (!priv->tx_skbuff)
-+ goto err_tx_skbuff;
-+
-+ if (priv->extend_desc) {
-+ priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
-+ sizeof(struct
-+ dma_extended_desc),
-+ &priv->dma_rx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_erx)
-+ goto err_dma;
-+
-+ priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
-+ sizeof(struct
-+ dma_extended_desc),
-+ &priv->dma_tx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_etx) {
-+ dma_free_coherent(priv->device, priv->dma_rx_size *
-+ sizeof(struct dma_extended_desc),
-+ priv->dma_erx, priv->dma_rx_phy);
-+ goto err_dma;
-+ }
-+ } else {
-+ priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
-+ sizeof(struct dma_desc),
-+ &priv->dma_rx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_rx)
-+ goto err_dma;
-+
-+ priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
-+ sizeof(struct dma_desc),
-+ &priv->dma_tx_phy,
-+ GFP_KERNEL);
-+ if (!priv->dma_tx) {
-+ dma_free_coherent(priv->device, priv->dma_rx_size *
-+ sizeof(struct dma_desc),
-+ priv->dma_rx, priv->dma_rx_phy);
-+ goto err_dma;
-+ }
-+ }
-+
-+ return 0;
-+
-+err_dma:
-+ kfree(priv->tx_skbuff);
-+err_tx_skbuff:
-+ kfree(priv->tx_skbuff_dma);
-+err_tx_skbuff_dma:
-+ kfree(priv->rx_skbuff);
-+err_rx_skbuff:
-+ kfree(priv->rx_skbuff_dma);
-+ return ret;
-+}
-+
- static void free_dma_desc_resources(struct stmmac_priv *priv)
- {
- /* Release the DMA TX/RX socket buffers */
-@@ -1623,6 +1618,12 @@ static int stmmac_open(struct net_device *dev)
- priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
- priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
-
-+ alloc_dma_desc_resources(priv);
-+ if (ret < 0) {
-+ pr_err("%s: DMA descriptors allocation failed\n", __func__);
-+ goto dma_desc_error;
-+ }
-+
- ret = init_dma_desc_rings(dev);
- if (ret < 0) {
- pr_err("%s: DMA descriptors initialization failed\n", __func__);
---
-1.8.5.5
-
+++ /dev/null
-From 523f11b5d4fd72efb72b04cd7006bfd1d1d4f341 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:14 +0000
-Subject: [PATCH] net: stmmac: move hardware setup for stmmac_open to new
- function
-
-This patch moves hardware setup part of the code in stmmac_open to a new
-function stmmac_hw_setup, the reason for doing this is to make hw
-initialization independent function so that PM functions can re-use it to
-re-initialize the IP after returning from low power state.
-This will also avoid code duplication across stmmac_resume/restore and
-stmmac_open.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 155 ++++++++++++----------
- 1 file changed, 88 insertions(+), 67 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 532f2b4..341c8dc3 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -1586,6 +1586,86 @@ static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
- }
-
- /**
-+ * stmmac_hw_setup: setup mac in a usable state.
-+ * @dev : pointer to the device structure.
-+ * Description:
-+ * This function sets up the ip in a usable state.
-+ * Return value:
-+ * 0 on success and an appropriate (-)ve integer as defined in errno.h
-+ * file on failure.
-+ */
-+static int stmmac_hw_setup(struct net_device *dev)
-+{
-+ struct stmmac_priv *priv = netdev_priv(dev);
-+ int ret;
-+
-+ ret = init_dma_desc_rings(dev);
-+ if (ret < 0) {
-+ pr_err("%s: DMA descriptors initialization failed\n", __func__);
-+ return ret;
-+ }
-+ /* DMA initialization and SW reset */
-+ ret = stmmac_init_dma_engine(priv);
-+ if (ret < 0) {
-+ pr_err("%s: DMA engine initialization failed\n", __func__);
-+ return ret;
-+ }
-+
-+ /* Copy the MAC addr into the HW */
-+ priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
-+
-+ /* If required, perform hw setup of the bus. */
-+ if (priv->plat->bus_setup)
-+ priv->plat->bus_setup(priv->ioaddr);
-+
-+ /* Initialize the MAC Core */
-+ priv->hw->mac->core_init(priv->ioaddr);
-+
-+ /* Enable the MAC Rx/Tx */
-+ stmmac_set_mac(priv->ioaddr, true);
-+
-+ /* Set the HW DMA mode and the COE */
-+ stmmac_dma_operation_mode(priv);
-+
-+ stmmac_mmc_setup(priv);
-+
-+ ret = stmmac_init_ptp(priv);
-+ if (ret)
-+ pr_warn("%s: failed PTP initialisation\n", __func__);
-+
-+#ifdef CONFIG_STMMAC_DEBUG_FS
-+ ret = stmmac_init_fs(dev);
-+ if (ret < 0)
-+ pr_warn("%s: failed debugFS registration\n", __func__);
-+#endif
-+ /* Start the ball rolling... */
-+ pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
-+ priv->hw->dma->start_tx(priv->ioaddr);
-+ priv->hw->dma->start_rx(priv->ioaddr);
-+
-+ /* Dump DMA/MAC registers */
-+ if (netif_msg_hw(priv)) {
-+ priv->hw->mac->dump_regs(priv->ioaddr);
-+ priv->hw->dma->dump_regs(priv->ioaddr);
-+ }
-+ priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
-+
-+ priv->eee_enabled = stmmac_eee_init(priv);
-+
-+ stmmac_init_tx_coalesce(priv);
-+
-+ if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
-+ priv->rx_riwt = MAX_DMA_RIWT;
-+ priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
-+ }
-+
-+ if (priv->pcs && priv->hw->mac->ctrl_ane)
-+ priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
-+
-+ return 0;
-+}
-+
-+/**
- * stmmac_open - open entry point of the driver
- * @dev : pointer to the device structure.
- * Description:
-@@ -1613,6 +1693,10 @@ static int stmmac_open(struct net_device *dev)
- }
- }
-
-+ /* Extra statistics */
-+ memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
-+ priv->xstats.threshold = tc;
-+
- /* Create and initialize the TX/RX descriptors chains. */
- priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
- priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
-@@ -1624,28 +1708,14 @@ static int stmmac_open(struct net_device *dev)
- goto dma_desc_error;
- }
-
-- ret = init_dma_desc_rings(dev);
-+ ret = stmmac_hw_setup(dev);
- if (ret < 0) {
-- pr_err("%s: DMA descriptors initialization failed\n", __func__);
-- goto dma_desc_error;
-- }
--
-- /* DMA initialization and SW reset */
-- ret = stmmac_init_dma_engine(priv);
-- if (ret < 0) {
-- pr_err("%s: DMA engine initialization failed\n", __func__);
-+ pr_err("%s: Hw setup failed\n", __func__);
- goto init_error;
- }
-
-- /* Copy the MAC addr into the HW */
-- priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
--
-- /* If required, perform hw setup of the bus. */
-- if (priv->plat->bus_setup)
-- priv->plat->bus_setup(priv->ioaddr);
--
-- /* Initialize the MAC Core */
-- priv->hw->mac->core_init(priv->ioaddr);
-+ if (priv->phydev)
-+ phy_start(priv->phydev);
-
- /* Request the IRQ lines */
- ret = request_irq(dev->irq, stmmac_interrupt,
-@@ -1678,55 +1748,6 @@ static int stmmac_open(struct net_device *dev)
- }
- }
-
-- /* Enable the MAC Rx/Tx */
-- stmmac_set_mac(priv->ioaddr, true);
--
-- /* Set the HW DMA mode and the COE */
-- stmmac_dma_operation_mode(priv);
--
-- /* Extra statistics */
-- memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
-- priv->xstats.threshold = tc;
--
-- stmmac_mmc_setup(priv);
--
-- ret = stmmac_init_ptp(priv);
-- if (ret)
-- pr_warn("%s: failed PTP initialisation\n", __func__);
--
--#ifdef CONFIG_STMMAC_DEBUG_FS
-- ret = stmmac_init_fs(dev);
-- if (ret < 0)
-- pr_warn("%s: failed debugFS registration\n", __func__);
--#endif
-- /* Start the ball rolling... */
-- pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
-- priv->hw->dma->start_tx(priv->ioaddr);
-- priv->hw->dma->start_rx(priv->ioaddr);
--
-- /* Dump DMA/MAC registers */
-- if (netif_msg_hw(priv)) {
-- priv->hw->mac->dump_regs(priv->ioaddr);
-- priv->hw->dma->dump_regs(priv->ioaddr);
-- }
--
-- if (priv->phydev)
-- phy_start(priv->phydev);
--
-- priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
--
-- priv->eee_enabled = stmmac_eee_init(priv);
--
-- stmmac_init_tx_coalesce(priv);
--
-- if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
-- priv->rx_riwt = MAX_DMA_RIWT;
-- priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
-- }
--
-- if (priv->pcs && priv->hw->mac->ctrl_ane)
-- priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
--
- napi_enable(&priv->napi);
- netif_start_queue(dev);
-
---
-1.8.5.5
-
+++ /dev/null
-From 073752aa59b3db120b2508d5bdd0598ada25fd25 Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:27 +0000
-Subject: [PATCH] net: stmmac: make stmmac_mdio_reset non-static
-
-This patch promotes stmmac_mdio_reset function from static to
-non-static, so that power management functions can decide to reset if
-the IP comes out from lowe power state specially hibernation cases.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
- 2 files changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 92be6b3..5a568015 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -110,6 +110,7 @@ struct stmmac_priv {
-
- int stmmac_mdio_unregister(struct net_device *ndev);
- int stmmac_mdio_register(struct net_device *ndev);
-+int stmmac_mdio_reset(struct mii_bus *mii);
- void stmmac_set_ethtool_ops(struct net_device *netdev);
- extern const struct stmmac_desc_ops enh_desc_ops;
- extern const struct stmmac_desc_ops ndesc_ops;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-index aab12d2..a468eb1 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
-@@ -128,7 +128,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
- * @bus: points to the mii_bus structure
- * Description: reset the MII bus
- */
--static int stmmac_mdio_reset(struct mii_bus *bus)
-+int stmmac_mdio_reset(struct mii_bus *bus)
- {
- #if defined(CONFIG_STMMAC_PLATFORM)
- struct net_device *ndev = bus->priv;
---
-1.8.5.5
-
+++ /dev/null
-From 623997fb90eab7a135c2c68a332c8450a488baca Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:35 +0000
-Subject: [PATCH] net: stmmac: fix power management suspend-resume case
-
-The driver PM resume assumes that the IP is still powered up and the
-all the register contents are not disturbed when it comes out of low
-power suspend case. This assumption is wrong, basically the driver
-should not consider any state of registers after it comes out of low
-power. However driver can keep the part of the IP powered up if its a
-wake up source. But it can not assume the register state of the IP. Also
-its possible that SOC glue layer can take the power off the IP if its
-not wake-up source to reduce the power consumption.
-
-This patch re initializes hardware by calling stmmac_hw_setup function in
-resume case.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 341c8dc3..742a83f 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2887,18 +2887,19 @@ int stmmac_resume(struct net_device *ndev)
- * this bit because it can generate problems while resuming
- * from another devices (e.g. serial console).
- */
-- if (device_may_wakeup(priv->device))
-+ if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
-- else
-+ } else {
- /* enable the clk prevously disabled */
- clk_prepare_enable(priv->stmmac_clk);
-+ /* reset the phy so that it's ready */
-+ if (priv->mii)
-+ stmmac_mdio_reset(priv->mii);
-+ }
-
- netif_device_attach(ndev);
-
-- /* Enable the MAC and DMA */
-- stmmac_set_mac(priv->ioaddr, true);
-- priv->hw->dma->start_tx(priv->ioaddr);
-- priv->hw->dma->start_rx(priv->ioaddr);
-+ stmmac_hw_setup(ndev);
-
- napi_enable(&priv->napi);
-
---
-1.8.5.5
-
+++ /dev/null
-From 33a23e223749c45ff8099ff9baa235301a3ad07f Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:44 +0000
-Subject: [PATCH] net: stmmac: use suspend functions for hibernation
-
-In hibernation freeze case the driver just releases the resources like
-dma buffers, irqs, unregisters the drivers and during restore it does
-register, request the resources. This is not really necessary, as part
-of power management all the data structures are intact, all the
-previously allocated resources can be used after coming out of low
-power.
-
-This patch uses the suspend and resume callbacks for freeze and
-restore which initializes the hardware correctly without unregistering
-or releasing the resources, this should also help in reducing the time
-to restore.
-
-Also this patch fixes a bug in stmmac_pltfr_restore and
-stmmac_pltfr_freeze where it tries to get hold of platform data via
-dev_get_platdata call, which would return NULL in device tree cases and
-the next if statement would crash as there is no NULL check.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 -
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 16 --------
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 44 ++++++----------------
- 3 files changed, 12 insertions(+), 50 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 5a568015..027f1dd 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -117,8 +117,6 @@ struct stmmac_priv {
- extern const struct stmmac_hwtimestamp stmmac_ptp;
- int stmmac_ptp_register(struct stmmac_priv *priv);
- void stmmac_ptp_unregister(struct stmmac_priv *priv);
--int stmmac_freeze(struct net_device *ndev);
--int stmmac_restore(struct net_device *ndev);
- int stmmac_resume(struct net_device *ndev);
- int stmmac_suspend(struct net_device *ndev);
- int stmmac_dvr_remove(struct net_device *ndev);
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 742a83f..c1298a0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2912,22 +2912,6 @@ int stmmac_resume(struct net_device *ndev)
-
- return 0;
- }
--
--int stmmac_freeze(struct net_device *ndev)
--{
-- if (!ndev || !netif_running(ndev))
-- return 0;
--
-- return stmmac_release(ndev);
--}
--
--int stmmac_restore(struct net_device *ndev)
--{
-- if (!ndev || !netif_running(ndev))
-- return 0;
--
-- return stmmac_open(ndev);
--}
- #endif /* CONFIG_PM */
-
- /* Driver can be configured w/ and w/ both PCI and Platf drivers
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 9377ee6..6d0bf22 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -211,55 +211,35 @@ static int stmmac_pltfr_remove(struct platform_device *pdev)
- #ifdef CONFIG_PM
- static int stmmac_pltfr_suspend(struct device *dev)
- {
-- struct net_device *ndev = dev_get_drvdata(dev);
--
-- return stmmac_suspend(ndev);
--}
--
--static int stmmac_pltfr_resume(struct device *dev)
--{
-- struct net_device *ndev = dev_get_drvdata(dev);
--
-- return stmmac_resume(ndev);
--}
--
--static int stmmac_pltfr_freeze(struct device *dev)
--{
- int ret;
-- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
-+ struct stmmac_priv *priv = netdev_priv(ndev);
- struct platform_device *pdev = to_platform_device(dev);
-
-- ret = stmmac_freeze(ndev);
-- if (plat_dat->exit)
-- plat_dat->exit(pdev);
-+ ret = stmmac_suspend(ndev);
-+ if (priv->plat->exit)
-+ priv->plat->exit(pdev);
-
- return ret;
- }
-
--static int stmmac_pltfr_restore(struct device *dev)
-+static int stmmac_pltfr_resume(struct device *dev)
- {
-- struct plat_stmmacenet_data *plat_dat = dev_get_platdata(dev);
- struct net_device *ndev = dev_get_drvdata(dev);
-+ struct stmmac_priv *priv = netdev_priv(ndev);
- struct platform_device *pdev = to_platform_device(dev);
-
-- if (plat_dat->init)
-- plat_dat->init(pdev);
-+ if (priv->plat->init)
-+ priv->plat->init(pdev);
-
-- return stmmac_restore(ndev);
-+ return stmmac_resume(ndev);
- }
-
--static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
-- .suspend = stmmac_pltfr_suspend,
-- .resume = stmmac_pltfr_resume,
-- .freeze = stmmac_pltfr_freeze,
-- .thaw = stmmac_pltfr_restore,
-- .restore = stmmac_pltfr_restore,
--};
--#else
--static const struct dev_pm_ops stmmac_pltfr_pm_ops;
- #endif /* CONFIG_PM */
-
-+static SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops,
-+ stmmac_pltfr_suspend, stmmac_pltfr_resume);
-+
- static const struct of_device_id stmmac_dt_ids[] = {
- { .compatible = "st,spear600-gmac"},
- { .compatible = "snps,dwmac-3.610"},
---
-1.8.5.5
-
+++ /dev/null
-From db88f10ad6a84c5bcb71bf51f0988a4bb1733bea Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:52:52 +0000
-Subject: [PATCH] net: stmmac: restore pinstate in pm resume.
-
-This patch adds code to restore default pinstate of the pins when it
-comes back from low power state. Without this patch the state of the
-pins would be unknown and the driver would not work.
-
-This patch also adds code to put the pins in to sleep state when the
-driver enters low power state.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index c1298a0..df7d8d6 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -43,6 +43,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/slab.h>
- #include <linux/prefetch.h>
-+#include <linux/pinctrl/consumer.h>
- #ifdef CONFIG_STMMAC_DEBUG_FS
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
-@@ -2864,6 +2865,7 @@ int stmmac_suspend(struct net_device *ndev)
- priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
- else {
- stmmac_set_mac(priv->ioaddr, false);
-+ pinctrl_pm_select_sleep_state(priv->device);
- /* Disable clock in case of PWM is off */
- clk_disable_unprepare(priv->stmmac_clk);
- }
-@@ -2890,6 +2892,7 @@ int stmmac_resume(struct net_device *ndev)
- if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
- } else {
-+ pinctrl_pm_select_default_state(priv->device);
- /* enable the clk prevously disabled */
- clk_prepare_enable(priv->stmmac_clk);
- /* reset the phy so that it's ready */
---
-1.8.5.5
-
+++ /dev/null
-From 89f7f2cfdd7ade55d5230501c21271690790ceda Mon Sep 17 00:00:00 2001
-From: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Date: Thu, 16 Jan 2014 10:53:00 +0000
-Subject: [PATCH] net: stmmac: notify the PM core of a wakeup event.
-
-In PM_SUSPEND_FREEZE and WOL(Wakeup On Lan) case, when the driver gets a
-wakeup event, either the driver or platform specific PM code should notify
-the pm core about it, so that the system can wakeup from low power.
-
-In cases where there is no involvement of platform specific PM, it
-becomes driver responsibility to notify the PM core to wakeup the
-system.
-
-Without this WOL with PM_SUSPEND_FREEZE does not work on STi based SOCs.
-
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
-Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 +++++++--
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 027f1dd..73709e9 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -105,6 +105,7 @@ struct stmmac_priv {
- unsigned int default_addend;
- u32 adv_ts;
- int use_riwt;
-+ int irq_wake;
- spinlock_t ptp_lock;
- };
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index df7d8d6..cddcf76 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2320,6 +2320,9 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
- struct net_device *dev = (struct net_device *)dev_id;
- struct stmmac_priv *priv = netdev_priv(dev);
-
-+ if (priv->irq_wake)
-+ pm_wakeup_event(priv->device, 0);
-+
- if (unlikely(!dev)) {
- pr_err("%s: invalid dev pointer\n", __func__);
- return IRQ_NONE;
-@@ -2861,9 +2864,10 @@ int stmmac_suspend(struct net_device *ndev)
- stmmac_clear_descriptors(priv);
-
- /* Enable Power down mode by programming the PMT regs */
-- if (device_may_wakeup(priv->device))
-+ if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
-- else {
-+ priv->irq_wake = 1;
-+ } else {
- stmmac_set_mac(priv->ioaddr, false);
- pinctrl_pm_select_sleep_state(priv->device);
- /* Disable clock in case of PWM is off */
-@@ -2891,6 +2895,7 @@ int stmmac_resume(struct net_device *ndev)
- */
- if (device_may_wakeup(priv->device)) {
- priv->hw->mac->pmt(priv->ioaddr, 0);
-+ priv->irq_wake = 0;
- } else {
- pinctrl_pm_select_default_state(priv->device);
- /* enable the clk prevously disabled */
---
-1.8.5.5
-
+++ /dev/null
-From 957f00fbab201f429ad81cc87ee3177e4289567d Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:51 +0800
-Subject: [PATCH] ARM: dts: sun7i: cubietruck: Enable the GMAC
-
-The CubieTruck uses the GMAC with an RGMII phy.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index f9dcb61..025ce52 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -51,6 +51,18 @@
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_rgmii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "rgmii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From 7405ae68d251191677e51aadb4308d6ce5212bbe Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:52 +0800
-Subject: [PATCH] ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC
-
-GMAC has better performance and fewer hardware issues.
-Use the GMAC in MII mode for ethernet instead of the EMAC.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ++++++++++++---------------
- 1 file changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 5c51cb8..7bf4935 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -19,21 +19,6 @@
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-- emac: ethernet@01c0b000 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&emac_pins_a>;
-- phy = <&phy1>;
-- status = "okay";
-- };
--
-- mdio@01c0b080 {
-- status = "okay";
--
-- phy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-- };
--
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-@@ -60,6 +45,18 @@
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_mii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "mii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From e401b86036245d2d62d825f0e3e12286c111b281 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:53 +0800
-Subject: [PATCH] ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of
- EMAC
-
-GMAC has better performance and fewer hardware issues.
-Use the GMAC in MII mode for ethernet instead of the EMAC.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++++++++++--------------
- 1 file changed, 12 insertions(+), 15 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index ead3013..b02a796 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -19,21 +19,6 @@
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-- emac: ethernet@01c0b000 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&emac_pins_a>;
-- phy = <&phy1>;
-- status = "okay";
-- };
--
-- mdio@01c0b080 {
-- status = "okay";
--
-- phy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-- };
--
- pinctrl@01c20800 {
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
-@@ -78,6 +63,18 @@
- pinctrl-0 = <&i2c2_pins_a>;
- status = "okay";
- };
-+
-+ gmac: ethernet@01c50000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac_pins_mii_a>;
-+ phy = <&phy1>;
-+ phy-mode = "mii";
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
- };
-
- leds {
---
-1.8.5.5
-
+++ /dev/null
-From 62866e98737e77c87f9dec99edea76ab54360770 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:40 +0800
-Subject: [PATCH] net: stmmac: Enable stmmac main clock when probing hardware
-
-The stmmac driver does not enable the main clock during the probe phase.
-If the clock was not enabled by the boot loader or was disabled by the
-kernel, hardware features and the MDIO bus would not be probed properly.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 26 +++++++++++------------
- 1 file changed, 13 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index cddcf76..0d2c4cb 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -1680,8 +1680,6 @@ static int stmmac_open(struct net_device *dev)
- struct stmmac_priv *priv = netdev_priv(dev);
- int ret;
-
-- clk_prepare_enable(priv->stmmac_clk);
--
- stmmac_check_ether_addr(priv);
-
- if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
-@@ -1819,7 +1817,6 @@ static int stmmac_release(struct net_device *dev)
- #ifdef CONFIG_STMMAC_DEBUG_FS
- stmmac_exit_fs();
- #endif
-- clk_disable_unprepare(priv->stmmac_clk);
-
- stmmac_release_ptp(priv);
-
-@@ -2727,10 +2724,18 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- if ((phyaddr >= 0) && (phyaddr <= 31))
- priv->plat->phy_addr = phyaddr;
-
-+ priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
-+ if (IS_ERR(priv->stmmac_clk)) {
-+ dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
-+ __func__);
-+ goto error_clk_get;
-+ }
-+ clk_prepare_enable(priv->stmmac_clk);
-+
- /* Init MAC and get the capabilities */
- ret = stmmac_hw_init(priv);
- if (ret)
-- goto error_free_netdev;
-+ goto error_hw_init;
-
- ndev->netdev_ops = &stmmac_netdev_ops;
-
-@@ -2768,12 +2773,6 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- goto error_netdev_register;
- }
-
-- priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
-- if (IS_ERR(priv->stmmac_clk)) {
-- pr_warn("%s: warning: cannot get CSR clock\n", __func__);
-- goto error_clk_get;
-- }
--
- /* If a specific clk_csr value is passed from the platform
- * this means that the CSR Clock Range selection cannot be
- * changed at run-time and it is fixed. Viceversa the driver'll try to
-@@ -2801,12 +2800,12 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- return priv;
-
- error_mdio_register:
-- clk_put(priv->stmmac_clk);
--error_clk_get:
- unregister_netdev(ndev);
- error_netdev_register:
- netif_napi_del(&priv->napi);
--error_free_netdev:
-+error_hw_init:
-+ clk_disable_unprepare(priv->stmmac_clk);
-+error_clk_get:
- free_netdev(ndev);
-
- return NULL;
-@@ -2833,6 +2832,7 @@ int stmmac_dvr_remove(struct net_device *ndev)
- stmmac_mdio_unregister(ndev);
- netif_carrier_off(ndev);
- unregister_netdev(ndev);
-+ clk_disable_unprepare(priv->stmmac_clk);
- free_netdev(ndev);
-
- return 0;
---
-1.8.5.5
-
+++ /dev/null
-From c5e4ddbdfa1134a36589c1466ed4abb85fe6f976 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:41 +0800
-Subject: [PATCH] net: stmmac: Add support for optional reset control
-
-The DWMAC has a reset assert line, which is used on some SoCs. Add an
-optional reset control to stmmac driver core.
-
-To support reset control deferred probing, this patch changes the driver
-probe function to return the actual error, instead of just -EINVAL.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/stmmac.txt | 3 +++
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++
- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 19 ++++++++++++++++++-
- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 4 ++--
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++--
- 6 files changed, 28 insertions(+), 5 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
-index eba0e5e..d132513 100644
---- a/Documentation/devicetree/bindings/net/stmmac.txt
-+++ b/Documentation/devicetree/bindings/net/stmmac.txt
-@@ -30,6 +30,9 @@ Required properties:
-
- Optional properties:
- - mac-address: 6 bytes, mac address
-+- resets: Should contain a phandle to the STMMAC reset signal, if any
-+- reset-names: Should contain the reset signal name "stmmaceth", if a
-+ reset phandle is given
-
- Examples:
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-index 6e52c0f..b59d1ef 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -5,6 +5,7 @@ config STMMAC_ETH
- select PHYLIB
- select CRC32
- select PTP_1588_CLOCK
-+ select RESET_CONTROLLER
- ---help---
- This is the driver for the Ethernet IPs are built around a
- Synopsys IP Core and only tested on the STMicroelectronics
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index 73709e9..c1c141f 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -32,6 +32,7 @@
- #include <linux/pci.h>
- #include "common.h"
- #include <linux/ptp_clock_kernel.h>
-+#include <linux/reset.h>
-
- struct stmmac_priv {
- /* Frequently used values are kept adjacent for cache effect */
-@@ -91,6 +92,7 @@ struct stmmac_priv {
- int wolopts;
- int wol_irq;
- struct clk *stmmac_clk;
-+ struct reset_control *stmmac_rst;
- int clk_csr;
- struct timer_list eee_ctrl_timer;
- int lpi_irq;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-index 0d2c4cb..0c5c120 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -51,6 +51,7 @@
- #include <linux/net_tstamp.h>
- #include "stmmac_ptp.h"
- #include "stmmac.h"
-+#include <linux/reset.h>
-
- #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
- #define JUMBO_LEN 9000
-@@ -2728,10 +2729,24 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- if (IS_ERR(priv->stmmac_clk)) {
- dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
- __func__);
-+ ret = PTR_ERR(priv->stmmac_clk);
- goto error_clk_get;
- }
- clk_prepare_enable(priv->stmmac_clk);
-
-+ priv->stmmac_rst = devm_reset_control_get(priv->device,
-+ STMMAC_RESOURCE_NAME);
-+ if (IS_ERR(priv->stmmac_rst)) {
-+ if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
-+ ret = -EPROBE_DEFER;
-+ goto error_hw_init;
-+ }
-+ dev_info(priv->device, "no reset control found\n");
-+ priv->stmmac_rst = NULL;
-+ }
-+ if (priv->stmmac_rst)
-+ reset_control_deassert(priv->stmmac_rst);
-+
- /* Init MAC and get the capabilities */
- ret = stmmac_hw_init(priv);
- if (ret)
-@@ -2808,7 +2823,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- error_clk_get:
- free_netdev(ndev);
-
-- return NULL;
-+ return ERR_PTR(ret);
- }
-
- /**
-@@ -2832,6 +2847,8 @@ int stmmac_dvr_remove(struct net_device *ndev)
- stmmac_mdio_unregister(ndev);
- netif_carrier_off(ndev);
- unregister_netdev(ndev);
-+ if (priv->stmmac_rst)
-+ reset_control_assert(priv->stmmac_rst);
- clk_disable_unprepare(priv->stmmac_clk);
- free_netdev(ndev);
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-index 37ba2e0..2916089 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
-@@ -100,9 +100,9 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
- stmmac_default_data();
-
- priv = stmmac_dvr_probe(&(pdev->dev), &plat_dat, addr);
-- if (!priv) {
-+ if (IS_ERR(priv)) {
- pr_err("%s: main driver probe failed", __func__);
-- ret = -ENODEV;
-+ ret = PTR_ERR(priv);
- goto err_out;
- }
- priv->dev->irq = pdev->irq;
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 6d0bf22..cc6b89a7 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -152,9 +152,9 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
- }
-
- priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
-- if (!priv) {
-+ if (IS_ERR(priv)) {
- pr_err("%s: main driver probe failed", __func__);
-- return -ENODEV;
-+ return PTR_ERR(priv);
- }
-
- /* Get MAC address if available (DT) */
---
-1.8.5.5
-
+++ /dev/null
-From 938dfdaa3c0f92e9a490d324f3bce43bbaef7632 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:42 +0800
-Subject: [PATCH] net: stmmac: Allocate and pass soc/board specific data to
- callbacks
-
-The current .init and .exit callbacks requires access to driver
-private data structures. This is not a good seperation and abstraction.
-
-Instead, we add a new .setup callback for allocating private data, and
-pass the returned pointer to the other callbacks.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/networking/stmmac.txt | 12 ++++++++----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 18 ++++++++++++++----
- include/linux/stmmac.h | 6 ++++--
- 3 files changed, 26 insertions(+), 10 deletions(-)
-
-diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt
-index cdd916d..2090895 100644
---- a/Documentation/networking/stmmac.txt
-+++ b/Documentation/networking/stmmac.txt
-@@ -127,8 +127,9 @@ struct plat_stmmacenet_data {
- int riwt_off;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
-- int (*init)(struct platform_device *pdev);
-- void (*exit)(struct platform_device *pdev);
-+ void *(*setup)(struct platform_device *pdev);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
- void *custom_cfg;
- void *custom_data;
- void *bsp_priv;
-@@ -169,10 +170,13 @@ Where:
- o bus_setup: perform HW setup of the bus. For example, on some ST platforms
- this field is used to configure the AMBA bridge to generate more
- efficient STBus traffic.
-- o init/exit: callbacks used for calling a custom initialization;
-+ o setup/init/exit: callbacks used for calling a custom initialization;
- this is sometime necessary on some platforms (e.g. ST boxes)
- where the HW needs to have set some PIO lines or system cfg
-- registers.
-+ registers. setup should return a pointer to private data,
-+ which will be stored in bsp_priv, and then passed to init and
-+ exit callbacks. init/exit callbacks should not use or modify
-+ platform data.
- o custom_cfg/custom_data: this is a custom configuration that can be passed
- while initializing the resources.
- o bsp_priv: another private pointer.
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index cc6b89a7..704a5e0 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -144,9 +144,16 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
- }
- }
-
-+ /* Custom setup (if needed) */
-+ if (plat_dat->setup) {
-+ plat_dat->bsp_priv = plat_dat->setup(pdev);
-+ if (IS_ERR(plat_dat->bsp_priv))
-+ return PTR_ERR(plat_dat->bsp_priv);
-+ }
-+
- /* Custom initialisation (if needed)*/
- if (plat_dat->init) {
-- ret = plat_dat->init(pdev);
-+ ret = plat_dat->init(pdev, plat_dat->bsp_priv);
- if (unlikely(ret))
- return ret;
- }
-@@ -203,7 +210,10 @@ static int stmmac_pltfr_remove(struct platform_device *pdev)
- int ret = stmmac_dvr_remove(ndev);
-
- if (priv->plat->exit)
-- priv->plat->exit(pdev);
-+ priv->plat->exit(pdev, priv->plat->bsp_priv);
-+
-+ if (priv->plat->free)
-+ priv->plat->free(pdev, priv->plat->bsp_priv);
-
- return ret;
- }
-@@ -218,7 +228,7 @@ static int stmmac_pltfr_suspend(struct device *dev)
-
- ret = stmmac_suspend(ndev);
- if (priv->plat->exit)
-- priv->plat->exit(pdev);
-+ priv->plat->exit(pdev, priv->plat->bsp_priv);
-
- return ret;
- }
-@@ -230,7 +240,7 @@ static int stmmac_pltfr_resume(struct device *dev)
- struct platform_device *pdev = to_platform_device(dev);
-
- if (priv->plat->init)
-- priv->plat->init(pdev);
-+ priv->plat->init(pdev, priv->plat->bsp_priv);
-
- return stmmac_resume(ndev);
- }
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index 33ace71..0a5a7ac 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -113,8 +113,10 @@ struct plat_stmmacenet_data {
- int max_speed;
- void (*fix_mac_speed)(void *priv, unsigned int speed);
- void (*bus_setup)(void __iomem *ioaddr);
-- int (*init)(struct platform_device *pdev);
-- void (*exit)(struct platform_device *pdev);
-+ void *(*setup)(struct platform_device *pdev);
-+ void (*free)(struct platform_device *pdev, void *priv);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
- void *custom_cfg;
- void *custom_data;
- void *bsp_priv;
---
-1.8.5.5
-
+++ /dev/null
-From 6aedb8c06df732625cf998c1428396914f3139b4 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:44 +0800
-Subject: [PATCH] net: stmmac: Honor DT parameter to force DMA store and
- forward mode
-
-"snps,force_sf_dma_mode" is documented in stmmac device tree bindings,
-but is never handled by the driver.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 704a5e0..634260e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -56,6 +56,8 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- sizeof(struct stmmac_mdio_bus_data),
- GFP_KERNEL);
-
-+ plat->force_sf_dma_mode = of_property_read_bool(np, "snps,force_sf_dma_mode");
-+
- /*
- * Currently only the properties needed on SPEAr600
- * are provided. All other properties should be added
---
-1.8.5.5
-
+++ /dev/null
-From 436f7ecdcc08f71ddc106b7bbe3bcbf1785f3bff Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:45 +0800
-Subject: [PATCH] net: stmmac: Deprecate snps, phy-addr and auto-detect PHY
- address
-
-The snps,phy-addr device tree property is non-standard, and should be
-removed in favor of proper phy node support. Remove it from the binding
-documents and warn if the property is still used.
-
-Most PHYs respond to address 0, but a few don't, so auto-detect PHY
-address by default, to make up for the lack of explicit address selection.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/stmmac.txt | 1 -
- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 ++++++++-
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
-index d132513..aefb639 100644
---- a/Documentation/devicetree/bindings/net/stmmac.txt
-+++ b/Documentation/devicetree/bindings/net/stmmac.txt
-@@ -12,7 +12,6 @@ Required properties:
- property
- - phy-mode: String, operation mode of the PHY interface.
- Supported values are: "mii", "rmii", "gmii", "rgmii".
--- snps,phy-addr phy address to connect to.
- - snps,reset-gpio gpio number for phy reset.
- - snps,reset-active-low boolean flag to indicate if phy reset is active low.
- - snps,reset-delays-us is triplet of delays
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 634260e..82110f1 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -50,7 +50,14 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- if (plat->bus_id < 0)
- plat->bus_id = 0;
-
-- of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr);
-+ /* Default to phy auto-detection */
-+ plat->phy_addr = -1;
-+
-+ /* "snps,phy-addr" is not a standard property. Mark it as deprecated
-+ * and warn of its use. Remove this when phy node support is added.
-+ */
-+ if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0)
-+ dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n");
-
- plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
- sizeof(struct stmmac_mdio_bus_data),
---
-1.8.5.5
-
+++ /dev/null
-From 022066f50f53000679d31eb407693085f37b3f14 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:46 +0800
-Subject: [PATCH] net: stmmac: Use driver data and callbacks tied with
- compatible strings
-
-The stmmac driver core allows passing feature flags and callbacks via
-platform data. Add a similar stmmac_of_data to pass flags and callbacks
-tied to compatible strings. This allows us to extend stmmac with glue
-layers for different SoCs.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 44 +++++++++++++++++-----
- include/linux/stmmac.h | 18 +++++++++
- 2 files changed, 52 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index 82110f1..bf119db 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -26,8 +26,20 @@
- #include <linux/io.h>
- #include <linux/of.h>
- #include <linux/of_net.h>
-+#include <linux/of_device.h>
- #include "stmmac.h"
-
-+static const struct of_device_id stmmac_dt_ids[] = {
-+ /* SoC specific glue layers should come before generic bindings */
-+ { .compatible = "st,spear600-gmac"},
-+ { .compatible = "snps,dwmac-3.610"},
-+ { .compatible = "snps,dwmac-3.70a"},
-+ { .compatible = "snps,dwmac-3.710"},
-+ { .compatible = "snps,dwmac"},
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
-+
- #ifdef CONFIG_OF
- static int stmmac_probe_config_dt(struct platform_device *pdev,
- struct plat_stmmacenet_data *plat,
-@@ -35,10 +47,32 @@ static int stmmac_probe_config_dt(struct platform_device *pdev,
- {
- struct device_node *np = pdev->dev.of_node;
- struct stmmac_dma_cfg *dma_cfg;
-+ const struct of_device_id *device;
-
- if (!np)
- return -ENODEV;
-
-+ device = of_match_device(stmmac_dt_ids, &pdev->dev);
-+ if (!device)
-+ return -ENODEV;
-+
-+ if (device->data) {
-+ const struct stmmac_of_data *data = device->data;
-+ plat->has_gmac = data->has_gmac;
-+ plat->enh_desc = data->enh_desc;
-+ plat->tx_coe = data->tx_coe;
-+ plat->rx_coe = data->rx_coe;
-+ plat->bugged_jumbo = data->bugged_jumbo;
-+ plat->pmt = data->pmt;
-+ plat->riwt_off = data->riwt_off;
-+ plat->fix_mac_speed = data->fix_mac_speed;
-+ plat->bus_setup = data->bus_setup;
-+ plat->setup = data->setup;
-+ plat->free = data->free;
-+ plat->init = data->init;
-+ plat->exit = data->exit;
-+ }
-+
- *mac = of_get_mac_address(np);
- plat->interface = of_get_phy_mode(np);
-
-@@ -259,16 +293,6 @@ static int stmmac_pltfr_resume(struct device *dev)
- static SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops,
- stmmac_pltfr_suspend, stmmac_pltfr_resume);
-
--static const struct of_device_id stmmac_dt_ids[] = {
-- { .compatible = "st,spear600-gmac"},
-- { .compatible = "snps,dwmac-3.610"},
-- { .compatible = "snps,dwmac-3.70a"},
-- { .compatible = "snps,dwmac-3.710"},
-- { .compatible = "snps,dwmac"},
-- { /* sentinel */ }
--};
--MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
--
- struct platform_driver stmmac_pltfr_driver = {
- .probe = stmmac_pltfr_probe,
- .remove = stmmac_pltfr_remove,
-diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
-index 0a5a7ac..1367974 100644
---- a/include/linux/stmmac.h
-+++ b/include/linux/stmmac.h
-@@ -121,4 +121,22 @@ struct plat_stmmacenet_data {
- void *custom_data;
- void *bsp_priv;
- };
-+
-+/* of_data for SoC glue layer device tree bindings */
-+
-+struct stmmac_of_data {
-+ int has_gmac;
-+ int enh_desc;
-+ int tx_coe;
-+ int rx_coe;
-+ int bugged_jumbo;
-+ int pmt;
-+ int riwt_off;
-+ void (*fix_mac_speed)(void *priv, unsigned int speed);
-+ void (*bus_setup)(void __iomem *ioaddr);
-+ void *(*setup)(struct platform_device *pdev);
-+ void (*free)(struct platform_device *pdev, void *priv);
-+ int (*init)(struct platform_device *pdev, void *priv);
-+ void (*exit)(struct platform_device *pdev, void *priv);
-+};
- #endif
---
-1.8.5.5
-
+++ /dev/null
-From af0bd4e9ba809391f275d0c094ac0bfbfbb3f430 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Fri, 17 Jan 2014 21:24:47 +0800
-Subject: [PATCH] net: stmmac: sunxi platform extensions for GMAC in Allwinner
- A20 SoC's
-
-The Allwinner A20 has an ethernet controller that seems to be
-an early version of Synopsys DesignWare MAC 10/100/1000 Universal,
-which is supported by the stmmac driver.
-
-Allwinner's GMAC requires setting additional registers in the SoC's
-clock control unit.
-
-The exact version of the DWMAC IP that Allwinner uses is unknown,
-thus the exact feature set is unknown.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- .../bindings/net/allwinner,sun7i-a20-gmac.txt | 27 ++++
- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
- drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
- drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 140 +++++++++++++++++++++
- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +
- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +
- 6 files changed, 185 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
- create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
-new file mode 100644
-index 0000000..ea4d752
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.txt
-@@ -0,0 +1,27 @@
-+* Allwinner GMAC ethernet controller
-+
-+This device is a platform glue layer for stmmac.
-+Please see stmmac.txt for the other unchanged properties.
-+
-+Required properties:
-+ - compatible: Should be "allwinner,sun7i-a20-gmac"
-+ - clocks: Should contain the GMAC main clock, and tx clock
-+ The tx clock type should be "allwinner,sun7i-a20-gmac-clk"
-+ - clock-names: Should contain the clock names "stmmaceth",
-+ and "allwinner_gmac_tx"
-+
-+Optional properties:
-+- phy-supply: phandle to a regulator if the PHY needs one
-+
-+Examples:
-+
-+ gmac: ethernet@01c50000 {
-+ compatible = "allwinner,sun7i-a20-gmac";
-+ reg = <0x01c50000 0x10000>,
-+ <0x01c20164 0x4>;
-+ interrupts = <0 85 1>;
-+ interrupt-names = "macirq";
-+ clocks = <&ahb_gates 49>, <&gmac_tx>;
-+ clock-names = "stmmaceth", "allwinner_gmac_tx";
-+ phy-mode = "mii";
-+ };
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-index b59d1ef..e2f202e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
-+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
-@@ -26,6 +26,17 @@ config STMMAC_PLATFORM
-
- If unsure, say N.
-
-+config DWMAC_SUNXI
-+ bool "Allwinner GMAC support"
-+ depends on STMMAC_PLATFORM && ARCH_SUNXI
-+ default y
-+ ---help---
-+ Support for Allwinner A20/A31 GMAC ethernet controllers.
-+
-+ This selects Allwinner SoC glue layer support for the
-+ stmmac device driver. This driver is used for A20/A31
-+ GMAC ethernet controller.
-+
- config STMMAC_PCI
- bool "STMMAC PCI bus support"
- depends on STMMAC_ETH && PCI
-diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
-index 356a9dd..ecadece 100644
---- a/drivers/net/ethernet/stmicro/stmmac/Makefile
-+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
-@@ -1,6 +1,7 @@
- obj-$(CONFIG_STMMAC_ETH) += stmmac.o
- stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o
- stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o
-+stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
- stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
- chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
- dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
-diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-new file mode 100644
-index 0000000..771cd15f
---- /dev/null
-+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
-@@ -0,0 +1,140 @@
-+/**
-+ * dwmac-sunxi.c - Allwinner sunxi DWMAC specific glue layer
-+ *
-+ * Copyright (C) 2013 Chen-Yu Tsai
-+ *
-+ * Chen-Yu Tsai <wens@csie.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/stmmac.h>
-+#include <linux/clk.h>
-+#include <linux/phy.h>
-+#include <linux/of_net.h>
-+#include <linux/regulator/consumer.h>
-+
-+struct sunxi_priv_data {
-+ int interface;
-+ int clk_enabled;
-+ struct clk *tx_clk;
-+ struct regulator *regulator;
-+};
-+
-+static void *sun7i_gmac_setup(struct platform_device *pdev)
-+{
-+ struct sunxi_priv_data *gmac;
-+ struct device *dev = &pdev->dev;
-+
-+ gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
-+ if (!gmac)
-+ return ERR_PTR(-ENOMEM);
-+
-+ gmac->interface = of_get_phy_mode(dev->of_node);
-+
-+ gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx");
-+ if (IS_ERR(gmac->tx_clk)) {
-+ dev_err(dev, "could not get tx clock\n");
-+ return gmac->tx_clk;
-+ }
-+
-+ /* Optional regulator for PHY */
-+ gmac->regulator = devm_regulator_get_optional(dev, "phy");
-+ if (IS_ERR(gmac->regulator)) {
-+ if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
-+ return ERR_PTR(-EPROBE_DEFER);
-+ dev_info(dev, "no regulator found\n");
-+ gmac->regulator = NULL;
-+ }
-+
-+ return gmac;
-+}
-+
-+#define SUN7I_GMAC_GMII_RGMII_RATE 125000000
-+#define SUN7I_GMAC_MII_RATE 25000000
-+
-+static int sun7i_gmac_init(struct platform_device *pdev, void *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+ int ret;
-+
-+ if (gmac->regulator) {
-+ ret = regulator_enable(gmac->regulator);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Set GMAC interface port mode
-+ *
-+ * The GMAC TX clock lines are configured by setting the clock
-+ * rate, which then uses the auto-reparenting feature of the
-+ * clock driver, and enabling/disabling the clock.
-+ */
-+ if (gmac->interface == PHY_INTERFACE_MODE_RGMII) {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
-+ clk_prepare_enable(gmac->tx_clk);
-+ gmac->clk_enabled = 1;
-+ } else {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
-+ clk_prepare(gmac->tx_clk);
-+ }
-+
-+ return 0;
-+}
-+
-+static void sun7i_gmac_exit(struct platform_device *pdev, void *priv)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+
-+ if (gmac->clk_enabled) {
-+ clk_disable(gmac->tx_clk);
-+ gmac->clk_enabled = 0;
-+ }
-+ clk_unprepare(gmac->tx_clk);
-+
-+ if (gmac->regulator)
-+ regulator_disable(gmac->regulator);
-+}
-+
-+static void sun7i_fix_speed(void *priv, unsigned int speed)
-+{
-+ struct sunxi_priv_data *gmac = priv;
-+
-+ /* only GMII mode requires us to reconfigure the clock lines */
-+ if (gmac->interface != PHY_INTERFACE_MODE_GMII)
-+ return;
-+
-+ if (gmac->clk_enabled) {
-+ clk_disable(gmac->tx_clk);
-+ gmac->clk_enabled = 0;
-+ }
-+ clk_unprepare(gmac->tx_clk);
-+
-+ if (speed == 1000) {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE);
-+ clk_prepare_enable(gmac->tx_clk);
-+ gmac->clk_enabled = 1;
-+ } else {
-+ clk_set_rate(gmac->tx_clk, SUN7I_GMAC_MII_RATE);
-+ clk_prepare(gmac->tx_clk);
-+ }
-+}
-+
-+/* of_data specifying hardware features and callbacks.
-+ * hardware features were copied from Allwinner drivers. */
-+const struct stmmac_of_data sun7i_gmac_data = {
-+ .has_gmac = 1,
-+ .tx_coe = 1,
-+ .fix_mac_speed = sun7i_fix_speed,
-+ .setup = sun7i_gmac_setup,
-+ .init = sun7i_gmac_init,
-+ .exit = sun7i_gmac_exit,
-+};
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-index c1c141f..d9af26e 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
-@@ -130,6 +130,9 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device,
- bool stmmac_eee_init(struct stmmac_priv *priv);
-
- #ifdef CONFIG_STMMAC_PLATFORM
-+#ifdef CONFIG_DWMAC_SUNXI
-+extern const struct stmmac_of_data sun7i_gmac_data;
-+#endif
- extern struct platform_driver stmmac_pltfr_driver;
- static inline int stmmac_register_platform(void)
- {
-diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-index bf119db..9d4baa8 100644
---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-@@ -30,6 +30,9 @@
- #include "stmmac.h"
-
- static const struct of_device_id stmmac_dt_ids[] = {
-+#ifdef CONFIG_DWMAC_SUNXI
-+ { .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
-+#endif
- /* SoC specific glue layers should come before generic bindings */
- { .compatible = "st,spear600-gmac"},
- { .compatible = "snps,dwmac-3.610"},
---
-1.8.5.5
-
+++ /dev/null
-From cc8e5932c671ba2d3ce511a15c19c47b015bc4ab Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 00:00:30 +0100
-Subject: [PATCH] phy-core: phy_get: Leave error logging to the caller
-
-In various cases errors may be expected, ie probe-deferral or a call to
-phy_get from a driver where the use of a phy is optional.
-
-Rather then adding all sort of complicated checks for this, and/or adding
-special functions like devm_phy_get_optional, simply don't log an error,
-and let deciding if get_phy returning an error really should result in a
-dev_err up to the caller.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/phy-core.c | 10 ++--------
- 1 file changed, 2 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
-index 5f5b0f4..b355553 100644
---- a/drivers/phy/phy-core.c
-+++ b/drivers/phy/phy-core.c
-@@ -404,17 +404,11 @@ struct phy *phy_get(struct device *dev, const char *string)
- index = of_property_match_string(dev->of_node, "phy-names",
- string);
- phy = of_phy_get(dev, index);
-- if (IS_ERR(phy)) {
-- dev_err(dev, "unable to find phy\n");
-- return phy;
-- }
- } else {
- phy = phy_lookup(dev, string);
-- if (IS_ERR(phy)) {
-- dev_err(dev, "unable to find phy\n");
-- return phy;
-- }
- }
-+ if (IS_ERR(phy))
-+ return phy;
-
- if (!try_module_get(phy->ops->owner))
- return ERR_PTR(-EPROBE_DEFER);
---
-1.8.5.5
-
+++ /dev/null
-From 37e3cce7288f7d5c34ae630f16faf48bd3d01c18 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 22:40:39 +0100
-Subject: [PATCH] phy-core: Don't propagate -ENOSUPP from
- phy_pm_runtime_get_sync to caller
-
-The phy-core allows phy_init and phy_power_on to be called multiple times,
-but before this patch -ENOSUPP from phy_pm_runtime_get_sync would be
-propagated to the caller for the 2nd and later calls.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/phy-core.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
-index b355553..6c73837 100644
---- a/drivers/phy/phy-core.c
-+++ b/drivers/phy/phy-core.c
-@@ -176,6 +176,8 @@ int phy_init(struct phy *phy)
- dev_err(&phy->dev, "phy init failed --> %d\n", ret);
- goto out;
- }
-+ } else {
-+ ret = 0; /* Override possible ret == -ENOTSUPP */
- }
- ++phy->init_count;
-
-@@ -232,6 +234,8 @@ int phy_power_on(struct phy *phy)
- dev_err(&phy->dev, "phy poweron failed --> %d\n", ret);
- goto out;
- }
-+ } else {
-+ ret = 0; /* Override possible ret == -ENOTSUPP */
- }
- ++phy->power_count;
- mutex_unlock(&phy->mutex);
---
-1.8.5.5
-
+++ /dev/null
-From 87c01c9ef0602abaa909771c6c6eab1f4c2c384d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 16:55:57 +0100
-Subject: [PATCH] phy-core: Don't allow building phy-core as a module
-
-include/phy/phy.h has stub code in there for when building without the
-phy-core enabled. This is useful for generic drivers such as ahci-platform,
-ehci-platoform and ohci-platform which have support for driving an optional
-phy passed to them through the devicetree.
-
-Since on some boards this phy functionality is not needed, being able to
-disable the phy subsystem without needing a lot of #ifdef magic in the
-driver using it is quite useful.
-
-However this breaks when the module using the phy subsystem is build-in and
-the phy-core is not, which leads to the build failing with missing symbol
-errors in the linking stage of the zImage.
-
-Which leads to gems such as this being added to the Kconfig for achi_platform:
-
- depends on GENERIC_PHY || !GENERIC_PHY
-
-Rather then duplicating this code in a lot of places using the phy-core,
-I believe it is better to simply not allow the phy-core to be built as a
-module. The phy core is quite small and has no external dependencies, so
-always building it in when enabling it should not be an issue.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/phy/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
-index afa2354..4ef8755 100644
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -5,7 +5,7 @@
- menu "PHY Subsystem"
-
- config GENERIC_PHY
-- tristate "PHY Core"
-+ bool "PHY Core"
- help
- Generic PHY support.
-
---
-1.8.5.5
-
+++ /dev/null
-From 9b10bc9f84fc221fcef9ddca92972af9b442f49d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 2 Dec 2013 16:13:32 +0100
-Subject: [PATCH] libahci: Allow drivers to override start_engine
-
-Allwinner A10 and A20 ARM SoCs have an AHCI sata controller which needs a
-special register to be poked before starting the DMA engine.
-
-This register gets reset on an ahci_stop_engine call, so there is no other
-place then ahci_start_engine where this poking can be done.
-
-This commit allows drivers to override ahci_start_engine behavior for use by
-the Allwinner AHCI driver (and potentially other drivers in the future).
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.c | 6 ++++--
- drivers/ata/ahci.h | 6 ++++++
- drivers/ata/libahci.c | 26 +++++++++++++++++++-------
- drivers/ata/sata_highbank.c | 3 ++-
- 4 files changed, 31 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
-index dc2756f..eda68b4 100644
---- a/drivers/ata/ahci.c
-+++ b/drivers/ata/ahci.c
-@@ -564,6 +564,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
- {
- struct ata_port *ap = link->ap;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- bool online;
- int rc;
-
-@@ -574,7 +575,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
- deadline, &online, NULL);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
-
-@@ -589,6 +590,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
- {
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -604,7 +606,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
- deadline, &online, NULL);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* The pseudo configuration device on SIMG4726 attached to
- * ASUS P5W-DH Deluxe doesn't send signature FIS after
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 2289efd..64d1a99d 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -323,6 +323,12 @@ struct ahci_host_priv {
- u32 em_msg_type; /* EM message type */
- struct clk *clk; /* Only for platforms supporting clk */
- void *plat_data; /* Other platform data */
-+ /*
-+ * Optional ahci_start_engine override, if not set this gets set to the
-+ * default ahci_start_engine during ahci_save_initial_config, this can
-+ * be overridden anytime before the host is activated.
-+ */
-+ void (*start_engine)(struct ata_port *ap);
- };
-
- extern int ahci_ignore_sss;
-diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
-index 36605ab..f839bb3 100644
---- a/drivers/ata/libahci.c
-+++ b/drivers/ata/libahci.c
-@@ -394,6 +394,9 @@ static ssize_t ahci_show_em_supported(struct device *dev,
- *
- * If inconsistent, config values are fixed up by this function.
- *
-+ * If it is not set already this function sets hpriv->start_engine to
-+ * ahci_start_engine.
-+ *
- * LOCKING:
- * None.
- */
-@@ -500,6 +503,9 @@ void ahci_save_initial_config(struct device *dev,
- hpriv->cap = cap;
- hpriv->cap2 = cap2;
- hpriv->port_map = port_map;
-+
-+ if (!hpriv->start_engine)
-+ hpriv->start_engine = ahci_start_engine;
- }
- EXPORT_SYMBOL_GPL(ahci_save_initial_config);
-
-@@ -766,7 +772,7 @@ static void ahci_start_port(struct ata_port *ap)
-
- /* enable DMA */
- if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* turn on LEDs */
- if (ap->flags & ATA_FLAG_EM) {
-@@ -1234,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
-
- /* restart engine */
- out_restart:
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- return rc;
- }
- EXPORT_SYMBOL_GPL(ahci_kick_engine);
-@@ -1426,6 +1432,7 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
- const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -1443,7 +1450,7 @@ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
- rc = sata_link_hardreset(link, timing, deadline, &online,
- ahci_check_ready);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- if (online)
- *class = ahci_dev_classify(ap);
-@@ -2007,10 +2014,12 @@ static void ahci_thaw(struct ata_port *ap)
-
- void ahci_error_handler(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
-+
- if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
- /* restart engine */
- ahci_stop_engine(ap);
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- sata_pmp_error_handler(ap);
-@@ -2031,6 +2040,7 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
-
- static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- struct ata_device *dev = ap->link.device;
- u32 devslp, dm, dito, mdat, deto;
-@@ -2094,7 +2104,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
- PORT_DEVSLP_ADSE);
- writel(devslp, port_mmio + PORT_DEVSLP);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- /* enable device sleep feature for the drive */
- err_mask = ata_dev_set_feature(dev,
-@@ -2106,6 +2116,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
-
- static void ahci_enable_fbs(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- struct ahci_port_priv *pp = ap->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- u32 fbs;
-@@ -2134,11 +2145,12 @@ static void ahci_enable_fbs(struct ata_port *ap)
- } else
- dev_err(ap->host->dev, "Failed to enable FBS\n");
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- static void ahci_disable_fbs(struct ata_port *ap)
- {
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- struct ahci_port_priv *pp = ap->private_data;
- void __iomem *port_mmio = ahci_port_base(ap);
- u32 fbs;
-@@ -2166,7 +2178,7 @@ static void ahci_disable_fbs(struct ata_port *ap)
- pp->fbs_enabled = false;
- }
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
- }
-
- static void ahci_pmp_attach(struct ata_port *ap)
-diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
-index 870b11e..b3b18d1 100644
---- a/drivers/ata/sata_highbank.c
-+++ b/drivers/ata/sata_highbank.c
-@@ -403,6 +403,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
- static const unsigned long timing[] = { 5, 100, 500};
- struct ata_port *ap = link->ap;
- struct ahci_port_priv *pp = ap->private_data;
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
- u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
- struct ata_taskfile tf;
- bool online;
-@@ -431,7 +432,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
- break;
- } while (!online && retry--);
-
-- ahci_start_engine(ap);
-+ hpriv->start_engine(ap);
-
- if (online)
- *class = ahci_dev_classify(ap);
---
-1.8.5.5
-
+++ /dev/null
-From bdad8090b5efdb24fa9db00d8e2891927b68dcec Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Thu, 16 Jan 2014 14:32:35 +0100
-Subject: [PATCH] ahci-platform: Add support for devices with more then 1 clock
-
-The allwinner-sun4i AHCI controller needs 2 clocks to be enabled and the
-imx AHCI controller needs 3 clocks to be enabled.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 1 +
- drivers/ata/ahci.h | 3 +-
- drivers/ata/ahci_platform.c | 119 ++++++++++++++++-----
- include/linux/ahci_platform.h | 4 +
- 4 files changed, 99 insertions(+), 28 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 89de156..3ced07d 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -10,6 +10,7 @@ Required properties:
-
- Optional properties:
- - dma-coherent : Present if dma operations are coherent
-+- clocks : a list of phandle + clock specifier pairs
-
- Example:
- sata@ffe08000 {
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 64d1a99d..c12862b 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -51,6 +51,7 @@
-
- enum {
- AHCI_MAX_PORTS = 32,
-+ AHCI_MAX_CLKS = 3,
- AHCI_MAX_SG = 168, /* hardware max is 64K */
- AHCI_DMA_BOUNDARY = 0xffffffff,
- AHCI_MAX_CMDS = 32,
-@@ -321,7 +322,7 @@ struct ahci_host_priv {
- u32 em_loc; /* enclosure management location */
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
-- struct clk *clk; /* Only for platforms supporting clk */
-+ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 4b231ba..609975d 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -87,6 +87,66 @@ struct ata_port_operations ahci_platform_ops = {
- AHCI_SHT("ahci_platform"),
- };
-
-+/**
-+ * ahci_platform_enable_clks - Enable platform clocks
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function enables all the clks found in hpriv->clks, starting
-+ * at index 0. If any clk fails to enable it disables all the clks
-+ * already enabled in reverse order, and then returns an error.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_enable_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c, rc;
-+
-+ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) {
-+ rc = clk_prepare_enable(hpriv->clks[c]);
-+ if (rc)
-+ goto disable_unprepare_clk;
-+ }
-+ return 0;
-+
-+disable_unprepare_clk:
-+ while (--c >= 0)
-+ clk_disable_unprepare(hpriv->clks[c]);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_enable_clks);
-+
-+/**
-+ * ahci_platform_disable_clks - Disable platform clocks
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function disables all the clks found in hpriv->clks, in reverse
-+ * order of ahci_platform_enable_clks (starting at the end of the array).
-+ *
-+ * LOCKING:
-+ * None.
-+ */
-+void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c;
-+
-+ for (c = AHCI_MAX_CLKS - 1; c >= 0; c--)
-+ if (hpriv->clks[c])
-+ clk_disable_unprepare(hpriv->clks[c]);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
-+
-+static void ahci_put_clks(struct ahci_host_priv *hpriv)
-+{
-+ int c;
-+
-+ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
-+ clk_put(hpriv->clks[c]);
-+}
-+
- static int ahci_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-@@ -97,6 +157,7 @@ static int ahci_probe(struct platform_device *pdev)
- struct ahci_host_priv *hpriv;
- struct ata_host *host;
- struct resource *mem;
-+ struct clk *clk;
- int irq;
- int n_ports;
- int i;
-@@ -131,17 +192,31 @@ static int ahci_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-- hpriv->clk = clk_get(dev, NULL);
-- if (IS_ERR(hpriv->clk)) {
-- dev_err(dev, "can't get clock\n");
-- } else {
-- rc = clk_prepare_enable(hpriv->clk);
-- if (rc) {
-- dev_err(dev, "clock prepare enable failed");
-- goto free_clk;
-+ for (i = 0; i < AHCI_MAX_CLKS; i++) {
-+ /*
-+ * For now we must use clk_get(dev, NULL) for the first clock,
-+ * because some platforms (da850, spear13xx) are not yet
-+ * converted to use devicetree for clocks. For new platforms
-+ * this is equivalent to of_clk_get(dev->of_node, 0).
-+ */
-+ if (i == 0)
-+ clk = clk_get(dev, NULL);
-+ else
-+ clk = of_clk_get(dev->of_node, i);
-+
-+ if (IS_ERR(clk)) {
-+ rc = PTR_ERR(clk);
-+ if (rc == -EPROBE_DEFER)
-+ goto free_clk;
-+ break;
- }
-+ hpriv->clks[i] = clk;
- }
-
-+ rc = ahci_enable_clks(dev, hpriv);
-+ if (rc)
-+ goto free_clk;
-+
- /*
- * Some platforms might need to prepare for mmio region access,
- * which could be done in the following init call. So, the mmio
-@@ -222,11 +297,9 @@ static int ahci_probe(struct platform_device *pdev)
- if (pdata && pdata->exit)
- pdata->exit(dev);
- disable_unprepare_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
- free_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_put(hpriv->clk);
-+ ahci_put_clks(hpriv);
- return rc;
- }
-
-@@ -239,10 +312,8 @@ static void ahci_host_stop(struct ata_host *host)
- if (pdata && pdata->exit)
- pdata->exit(dev);
-
-- if (!IS_ERR(hpriv->clk)) {
-- clk_disable_unprepare(hpriv->clk);
-- clk_put(hpriv->clk);
-- }
-+ ahci_disable_clks(hpriv);
-+ ahci_put_clks(hpriv);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -277,8 +348,7 @@ static int ahci_suspend(struct device *dev)
- if (pdata && pdata->suspend)
- return pdata->suspend(dev);
-
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
-
- return 0;
- }
-@@ -290,13 +360,9 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-- if (!IS_ERR(hpriv->clk)) {
-- rc = clk_prepare_enable(hpriv->clk);
-- if (rc) {
-- dev_err(dev, "clock prepare enable failed");
-- return rc;
-- }
-- }
-+ rc = ahci_enable_clks(dev, hpriv);
-+ if (rc)
-+ return rc;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
-@@ -317,8 +383,7 @@ static int ahci_resume(struct device *dev)
- return 0;
-
- disable_unprepare_clk:
-- if (!IS_ERR(hpriv->clk))
-- clk_disable_unprepare(hpriv->clk);
-+ ahci_disable_clks(hpriv);
-
- return rc;
- }
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index 73a2500..769d065 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -19,6 +19,7 @@
-
- struct device;
- struct ata_port_info;
-+struct ahci_host_priv;
-
- struct ahci_platform_data {
- int (*init)(struct device *dev, void __iomem *addr);
-@@ -30,4 +31,7 @@ struct ahci_platform_data {
- unsigned int mask_port_map;
- };
-
-+int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
-+void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
-+
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From ba6850946d9e1959be1b00f6ae06454546350c75 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 17 Jan 2014 13:23:21 +0100
-Subject: [PATCH] ahci-platform: Add support for an optional regulator for
- sata-target power
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 1 +
- drivers/ata/ahci.h | 2 ++
- drivers/ata/ahci_platform.c | 36 ++++++++++++++++++++--
- 3 files changed, 37 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 3ced07d..1ac807f 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -11,6 +11,7 @@ Required properties:
- Optional properties:
- - dma-coherent : Present if dma operations are coherent
- - clocks : a list of phandle + clock specifier pairs
-+- target-supply : regulator for SATA target power
-
- Example:
- sata@ffe08000 {
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index c12862b..bf8100c 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -37,6 +37,7 @@
-
- #include <linux/clk.h>
- #include <linux/libata.h>
-+#include <linux/regulator/consumer.h>
-
- /* Enclosure Management Control */
- #define EM_CTRL_MSG_TYPE 0x000f0000
-@@ -323,6 +324,7 @@ struct ahci_host_priv {
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
-+ struct regulator *target_pwr; /* Optional */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 609975d..907c076 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -192,6 +192,14 @@ static int ahci_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-+ hpriv->target_pwr = devm_regulator_get_optional(dev, "target");
-+ if (IS_ERR(hpriv->target_pwr)) {
-+ rc = PTR_ERR(hpriv->target_pwr);
-+ if (rc == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+ hpriv->target_pwr = NULL;
-+ }
-+
- for (i = 0; i < AHCI_MAX_CLKS; i++) {
- /*
- * For now we must use clk_get(dev, NULL) for the first clock,
-@@ -213,9 +221,15 @@ static int ahci_probe(struct platform_device *pdev)
- hpriv->clks[i] = clk;
- }
-
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ goto free_clk;
-+ }
-+
- rc = ahci_enable_clks(dev, hpriv);
- if (rc)
-- goto free_clk;
-+ goto disable_regulator;
-
- /*
- * Some platforms might need to prepare for mmio region access,
-@@ -298,6 +312,9 @@ static int ahci_probe(struct platform_device *pdev)
- pdata->exit(dev);
- disable_unprepare_clk:
- ahci_disable_clks(hpriv);
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
- free_clk:
- ahci_put_clks(hpriv);
- return rc;
-@@ -314,6 +331,9 @@ static void ahci_host_stop(struct ata_host *host)
-
- ahci_disable_clks(hpriv);
- ahci_put_clks(hpriv);
-+
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -350,6 +370,9 @@ static int ahci_suspend(struct device *dev)
-
- ahci_disable_clks(hpriv);
-
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+
- return 0;
- }
-
-@@ -360,9 +383,15 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ return rc;
-+ }
-+
- rc = ahci_enable_clks(dev, hpriv);
- if (rc)
-- return rc;
-+ goto disable_regulator;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
-@@ -384,6 +413,9 @@ static int ahci_resume(struct device *dev)
-
- disable_unprepare_clk:
- ahci_disable_clks(hpriv);
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-
- return rc;
- }
---
-1.8.5.5
-
+++ /dev/null
-From 05d5a60ae336c122e478cc002afccc880d462b3b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 14:54:40 +0100
-Subject: [PATCH] ahci-platform: Add enable_ / disable_resources helper
- functions
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 112 ++++++++++++++++++++++++++++--------------
- include/linux/ahci_platform.h | 2 +
- 2 files changed, 77 insertions(+), 37 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 907c076..6ebbc17 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -139,6 +139,68 @@ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
- }
- EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
-
-+/**
-+ * ahci_platform_enable_resources - Enable platform resources
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function enables all ahci_platform managed resources in
-+ * the following order:
-+ * 1) Regulator
-+ * 2) Clocks (through ahci_platform_enable_clks)
-+ *
-+ * If resource enabling fails at any point the previous enabled
-+ * resources are disabled in reverse order.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
-+{
-+ int rc;
-+
-+ if (hpriv->target_pwr) {
-+ rc = regulator_enable(hpriv->target_pwr);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ rc = ahci_platform_enable_clks(hpriv);
-+ if (rc)
-+ goto disable_regulator;
-+
-+ return 0;
-+
-+disable_regulator:
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+ return rc;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
-+
-+/**
-+ * ahci_platform_disable_resources - Disable platform resources
-+ * @hpriv: host private area to store config values
-+ *
-+ * This function disables all ahci_platform managed resources in
-+ * the following order:
-+ * 1) Clocks (through ahci_platform_disable_clks)
-+ * 2) Regulator
-+ *
-+ * LOCKING:
-+ * None.
-+ */
-+void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
-+{
-+ ahci_platform_disable_clks(hpriv);
-+
-+ if (hpriv->target_pwr)
-+ regulator_disable(hpriv->target_pwr);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_disable_resources);
-+
- static void ahci_put_clks(struct ahci_host_priv *hpriv)
- {
- int c;
-@@ -221,15 +283,9 @@ static int ahci_probe(struct platform_device *pdev)
- hpriv->clks[i] = clk;
- }
-
-- if (hpriv->target_pwr) {
-- rc = regulator_enable(hpriv->target_pwr);
-- if (rc)
-- goto free_clk;
-- }
--
-- rc = ahci_enable_clks(dev, hpriv);
-+ rc = ahci_platform_enable_resources(hpriv);
- if (rc)
-- goto disable_regulator;
-+ goto free_clk;
-
- /*
- * Some platforms might need to prepare for mmio region access,
-@@ -240,7 +296,7 @@ static int ahci_probe(struct platform_device *pdev)
- if (pdata && pdata->init) {
- rc = pdata->init(dev, hpriv->mmio);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
- }
-
- ahci_save_initial_config(dev, hpriv,
-@@ -310,11 +366,8 @@ static int ahci_probe(struct platform_device *pdev)
- pdata_exit:
- if (pdata && pdata->exit)
- pdata->exit(dev);
--disable_unprepare_clk:
-- ahci_disable_clks(hpriv);
--disable_regulator:
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
- free_clk:
- ahci_put_clks(hpriv);
- return rc;
-@@ -329,11 +382,8 @@ static void ahci_host_stop(struct ata_host *host)
- if (pdata && pdata->exit)
- pdata->exit(dev);
-
-- ahci_disable_clks(hpriv);
-+ ahci_platform_disable_resources(hpriv);
- ahci_put_clks(hpriv);
--
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
- }
-
- #ifdef CONFIG_PM_SLEEP
-@@ -368,10 +418,7 @@ static int ahci_suspend(struct device *dev)
- if (pdata && pdata->suspend)
- return pdata->suspend(dev);
-
-- ahci_disable_clks(hpriv);
--
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+ ahci_platform_disable_resources(hpriv);
-
- return 0;
- }
-@@ -383,26 +430,20 @@ static int ahci_resume(struct device *dev)
- struct ahci_host_priv *hpriv = host->private_data;
- int rc;
-
-- if (hpriv->target_pwr) {
-- rc = regulator_enable(hpriv->target_pwr);
-- if (rc)
-- return rc;
-- }
--
-- rc = ahci_enable_clks(dev, hpriv);
-+ rc = ahci_platform_enable_resources(hpriv);
- if (rc)
-- goto disable_regulator;
-+ return rc;
-
- if (pdata && pdata->resume) {
- rc = pdata->resume(dev);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
- }
-
- if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
- rc = ahci_reset_controller(host);
- if (rc)
-- goto disable_unprepare_clk;
-+ goto disable_resources;
-
- ahci_init_controller(host);
- }
-@@ -411,11 +452,8 @@ static int ahci_resume(struct device *dev)
-
- return 0;
-
--disable_unprepare_clk:
-- ahci_disable_clks(hpriv);
--disable_regulator:
-- if (hpriv->target_pwr)
-- regulator_disable(hpriv->target_pwr);
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-
- return rc;
- }
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index 769d065..b674b01 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -33,5 +33,7 @@ struct ahci_platform_data {
-
- int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
- void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
-+int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
-+void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
-
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 98601575da5276173233dd575bdd61cccdeb861a Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 14:58:04 +0100
-Subject: [PATCH] ahci-platform: "Library-ise" ahci_probe functionality
-
-ahci_probe consists of 3 steps:
-1) Get resources (get mmio, clks, regulator)
-2) Enable resources, handled by ahci_platform_enable_resouces
-3) The more or less standard ahci-host controller init sequence
-
-This commit refactors step 1 and 3 into separate functions, so the platform
-drivers for AHCI implementations which need a specific order in step 2,
-and / or need to do some custom register poking at some time, can re-use
-ahci-platform.c code without needing to copy and paste it.
-
-Note that ahci_platform_init_host's prototype takes the 3 non function
-members of ahci_platform_data as arguments, the idea is that drivers using
-the new exported utility functions will not use ahci_platform_data at all,
-and hopefully in the future ahci_platform_data can go away entirely.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 195 ++++++++++++++++++++++++++++--------------
- include/linux/ahci_platform.h | 14 +++
- 2 files changed, 144 insertions(+), 65 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 6ebbc17..7f3f2ac 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -201,64 +201,64 @@ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
- }
- EXPORT_SYMBOL_GPL(ahci_platform_disable_resources);
-
--static void ahci_put_clks(struct ahci_host_priv *hpriv)
-+static void ahci_platform_put_resources(struct device *dev, void *res)
- {
-+ struct ahci_host_priv *hpriv = res;
- int c;
-
- for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
- clk_put(hpriv->clks[c]);
- }
-
--static int ahci_probe(struct platform_device *pdev)
-+/**
-+ * ahci_platform_get_resources - Get platform resources
-+ * @pdev: platform device to get resources for
-+ *
-+ * This function allocates an ahci_host_priv struct, and gets the
-+ * following resources, storing a reference to them inside the returned
-+ * struct:
-+ *
-+ * 1) mmio registers (IORESOURCE_MEM 0, mandatory)
-+ * 2) regulator for controlling the targets power (optional)
-+ * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
-+ * or for non devicetree enabled platforms a single clock
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * The allocated ahci_host_priv on success, otherwise an ERR_PTR value
-+ */
-+struct ahci_host_priv *ahci_platform_get_resources(
-+ struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-- struct ahci_platform_data *pdata = dev_get_platdata(dev);
-- const struct platform_device_id *id = platform_get_device_id(pdev);
-- struct ata_port_info pi = ahci_port_info[id ? id->driver_data : 0];
-- const struct ata_port_info *ppi[] = { &pi, NULL };
- struct ahci_host_priv *hpriv;
-- struct ata_host *host;
-- struct resource *mem;
- struct clk *clk;
-- int irq;
-- int n_ports;
-- int i;
-- int rc;
-+ int i, rc = -ENOMEM;
-
-- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!mem) {
-- dev_err(dev, "no mmio space\n");
-- return -EINVAL;
-- }
-+ if (!devres_open_group(dev, NULL, GFP_KERNEL))
-+ return ERR_PTR(-ENOMEM);
-
-- irq = platform_get_irq(pdev, 0);
-- if (irq <= 0) {
-- dev_err(dev, "no irq\n");
-- return -EINVAL;
-- }
-+ hpriv = devres_alloc(ahci_platform_put_resources, sizeof(*hpriv),
-+ GFP_KERNEL);
-+ if (!hpriv)
-+ goto err_out;
-
-- if (pdata && pdata->ata_port_info)
-- pi = *pdata->ata_port_info;
-+ devres_add(dev, hpriv);
-
-- hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
-- if (!hpriv) {
-- dev_err(dev, "can't alloc ahci_host_priv\n");
-- return -ENOMEM;
-- }
--
-- hpriv->flags |= (unsigned long)pi.private_data;
--
-- hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
-+ hpriv->mmio = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
- if (!hpriv->mmio) {
-- dev_err(dev, "can't map %pR\n", mem);
-- return -ENOMEM;
-+ dev_err(dev, "no mmio space\n");
-+ goto err_out;
- }
-
- hpriv->target_pwr = devm_regulator_get_optional(dev, "target");
- if (IS_ERR(hpriv->target_pwr)) {
- rc = PTR_ERR(hpriv->target_pwr);
- if (rc == -EPROBE_DEFER)
-- return -EPROBE_DEFER;
-+ goto err_out;
- hpriv->target_pwr = NULL;
- }
-
-@@ -277,33 +277,62 @@ static int ahci_probe(struct platform_device *pdev)
- if (IS_ERR(clk)) {
- rc = PTR_ERR(clk);
- if (rc == -EPROBE_DEFER)
-- goto free_clk;
-+ goto err_out;
- break;
- }
- hpriv->clks[i] = clk;
- }
-
-- rc = ahci_platform_enable_resources(hpriv);
-- if (rc)
-- goto free_clk;
-+ devres_remove_group(dev, NULL);
-+ return hpriv;
-
-- /*
-- * Some platforms might need to prepare for mmio region access,
-- * which could be done in the following init call. So, the mmio
-- * region shouldn't be accessed before init (if provided) has
-- * returned successfully.
-- */
-- if (pdata && pdata->init) {
-- rc = pdata->init(dev, hpriv->mmio);
-- if (rc)
-- goto disable_resources;
-- }
-+err_out:
-+ devres_release_group(dev, NULL);
-+ return ERR_PTR(rc);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
-+
-+/**
-+ * ahci_platform_init_host - Bring up an ahci-platform host
-+ * @pdev: platform device pointer for the host
-+ * @hpriv: ahci-host private data for the host
-+ * @pi_template: template for the ata_port_info to use
-+ * @force_port_map: param passed to ahci_save_initial_config
-+ * @mask_port_map: param passed to ahci_save_initial_config
-+ *
-+ * This function does all the usual steps needed to bring up an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be initialized / enabled before calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_init_host(struct platform_device *pdev,
-+ struct ahci_host_priv *hpriv,
-+ const struct ata_port_info *pi_template,
-+ unsigned int force_port_map,
-+ unsigned int mask_port_map)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ata_port_info pi = *pi_template;
-+ const struct ata_port_info *ppi[] = { &pi, NULL };
-+ struct ata_host *host;
-+ int i, irq, n_ports, rc;
-
-- ahci_save_initial_config(dev, hpriv,
-- pdata ? pdata->force_port_map : 0,
-- pdata ? pdata->mask_port_map : 0);
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq <= 0) {
-+ dev_err(dev, "no irq\n");
-+ return -EINVAL;
-+ }
-
- /* prepare host */
-+ hpriv->flags |= (unsigned long)pi.private_data;
-+
-+ ahci_save_initial_config(dev, hpriv, force_port_map, mask_port_map);
-+
- if (hpriv->cap & HOST_CAP_NCQ)
- pi.flags |= ATA_FLAG_NCQ;
-
-@@ -320,10 +349,8 @@ static int ahci_probe(struct platform_device *pdev)
- n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
-
- host = ata_host_alloc_pinfo(dev, ppi, n_ports);
-- if (!host) {
-- rc = -ENOMEM;
-- goto pdata_exit;
-- }
-+ if (!host)
-+ return -ENOMEM;
-
- host->private_data = hpriv;
-
-@@ -338,7 +365,8 @@ static int ahci_probe(struct platform_device *pdev)
- for (i = 0; i < host->n_ports; i++) {
- struct ata_port *ap = host->ports[i];
-
-- ata_port_desc(ap, "mmio %pR", mem);
-+ ata_port_desc(ap, "mmio %pR",
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
- ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
-
- /* set enclosure management message type */
-@@ -352,13 +380,53 @@ static int ahci_probe(struct platform_device *pdev)
-
- rc = ahci_reset_controller(host);
- if (rc)
-- goto pdata_exit;
-+ return rc;
-
- ahci_init_controller(host);
- ahci_print_info(host, "platform");
-
-- rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
-- &ahci_platform_sht);
-+ return ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
-+ &ahci_platform_sht);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_init_host);
-+
-+static int ahci_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ahci_platform_data *pdata = dev_get_platdata(dev);
-+ const struct platform_device_id *id = platform_get_device_id(pdev);
-+ const struct ata_port_info *pi_template;
-+ struct ahci_host_priv *hpriv;
-+ int rc;
-+
-+ hpriv = ahci_platform_get_resources(pdev);
-+ if (IS_ERR(hpriv))
-+ return PTR_ERR(hpriv);
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ /*
-+ * Some platforms might need to prepare for mmio region access,
-+ * which could be done in the following init call. So, the mmio
-+ * region shouldn't be accessed before init (if provided) has
-+ * returned successfully.
-+ */
-+ if (pdata && pdata->init) {
-+ rc = pdata->init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+ }
-+
-+ if (pdata && pdata->ata_port_info)
-+ pi_template = pdata->ata_port_info;
-+ else
-+ pi_template = &ahci_port_info[id ? id->driver_data : 0];
-+
-+ rc = ahci_platform_init_host(pdev, hpriv, pi_template,
-+ pdata ? pdata->force_port_map : 0,
-+ pdata ? pdata->mask_port_map : 0);
- if (rc)
- goto pdata_exit;
-
-@@ -368,8 +436,6 @@ static int ahci_probe(struct platform_device *pdev)
- pdata->exit(dev);
- disable_resources:
- ahci_platform_disable_resources(hpriv);
--free_clk:
-- ahci_put_clks(hpriv);
- return rc;
- }
-
-@@ -383,7 +449,6 @@ static void ahci_host_stop(struct ata_host *host)
- pdata->exit(dev);
-
- ahci_platform_disable_resources(hpriv);
-- ahci_put_clks(hpriv);
- }
-
- #ifdef CONFIG_PM_SLEEP
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index b674b01..b80c51c 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -20,7 +20,14 @@
- struct device;
- struct ata_port_info;
- struct ahci_host_priv;
-+struct platform_device;
-
-+/*
-+ * Note ahci_platform_data is deprecated, it is only kept around for use
-+ * by the old da850 and spear13xx ahci code.
-+ * New drivers should instead declare their own platform_driver struct, and
-+ * use ahci_platform* functions in their own probe, suspend and resume methods.
-+ */
- struct ahci_platform_data {
- int (*init)(struct device *dev, void __iomem *addr);
- void (*exit)(struct device *dev);
-@@ -35,5 +42,12 @@ struct ahci_platform_data {
- void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
- int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
- void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
-+struct ahci_host_priv *ahci_platform_get_resources(
-+ struct platform_device *pdev);
-+int ahci_platform_init_host(struct platform_device *pdev,
-+ struct ahci_host_priv *hpriv,
-+ const struct ata_port_info *pi_template,
-+ unsigned int force_port_map,
-+ unsigned int mask_port_map);
-
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 041cf8356a4eb91ee8118004b2bc9c78cdd7866c Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 20 Jan 2014 15:52:07 +0100
-Subject: [PATCH] ahci-platform: "Library-ise" suspend / resume functionality
-
-Split suspend / resume code into host suspend / resume functionality and
-resource enable / disabling phases, and export the new suspend_ / resume_host
-functions.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 109 ++++++++++++++++++++++++++++++++++++------
- include/linux/ahci_platform.h | 5 ++
- 2 files changed, 99 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 7f3f2ac..bdadec1 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -452,14 +452,26 @@ static void ahci_host_stop(struct ata_host *host)
- }
-
- #ifdef CONFIG_PM_SLEEP
--static int ahci_suspend(struct device *dev)
-+/**
-+ * ahci_platform_suspend_host - Suspend an ahci-platform host
-+ * @dev: device pointer for the host
-+ *
-+ * This function does all the usual steps needed to suspend an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be disabled after calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_suspend_host(struct device *dev)
- {
-- struct ahci_platform_data *pdata = dev_get_platdata(dev);
- struct ata_host *host = dev_get_drvdata(dev);
- struct ahci_host_priv *hpriv = host->private_data;
- void __iomem *mmio = hpriv->mmio;
- u32 ctl;
-- int rc;
-
- if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
- dev_err(dev, "firmware update required for suspend/resume\n");
-@@ -476,7 +488,64 @@ static int ahci_suspend(struct device *dev)
- writel(ctl, mmio + HOST_CTL);
- readl(mmio + HOST_CTL); /* flush */
-
-- rc = ata_host_suspend(host, PMSG_SUSPEND);
-+ return ata_host_suspend(host, PMSG_SUSPEND);
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_suspend_host);
-+
-+/**
-+ * ahci_platform_resume_host - Resume an ahci-platform host
-+ * @dev: device pointer for the host
-+ *
-+ * This function does all the usual steps needed to resume an
-+ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
-+ * must be initialized / enabled before calling this.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_resume_host(struct device *dev)
-+{
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ int rc;
-+
-+ if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
-+ rc = ahci_reset_controller(host);
-+ if (rc)
-+ return rc;
-+
-+ ahci_init_controller(host);
-+ }
-+
-+ ata_host_resume(host);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(ahci_platform_resume_host);
-+
-+/**
-+ * ahci_platform_suspend - Suspend an ahci-platform device
-+ * @dev: the platform device to suspend
-+ *
-+ * This function suspends the host associated with the device, followed
-+ * by disabling all the resources of the device.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_suspend(struct device *dev)
-+{
-+ struct ahci_platform_data *pdata = dev_get_platdata(dev);
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ struct ahci_host_priv *hpriv = host->private_data;
-+ int rc;
-+
-+ rc = ahci_platform_suspend_host(dev);
- if (rc)
- return rc;
-
-@@ -487,8 +556,22 @@ static int ahci_suspend(struct device *dev)
-
- return 0;
- }
-+EXPORT_SYMBOL_GPL(ahci_platform_suspend);
-
--static int ahci_resume(struct device *dev)
-+/**
-+ * ahci_platform_resume - Resume an ahci-platform device
-+ * @dev: the platform device to resume
-+ *
-+ * This function enables all the resources of the device followed by
-+ * resuming the host associated with the device.
-+ *
-+ * LOCKING:
-+ * None.
-+ *
-+ * RETURNS:
-+ * 0 on success otherwise a negative error code
-+ */
-+int ahci_platform_resume(struct device *dev)
- {
- struct ahci_platform_data *pdata = dev_get_platdata(dev);
- struct ata_host *host = dev_get_drvdata(dev);
-@@ -505,15 +588,9 @@ static int ahci_resume(struct device *dev)
- goto disable_resources;
- }
-
-- if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
-- rc = ahci_reset_controller(host);
-- if (rc)
-- goto disable_resources;
--
-- ahci_init_controller(host);
-- }
--
-- ata_host_resume(host);
-+ rc = ahci_platform_resume_host(dev);
-+ if (rc)
-+ goto disable_resources;
-
- return 0;
-
-@@ -522,9 +599,11 @@ static int ahci_resume(struct device *dev)
-
- return rc;
- }
-+EXPORT_SYMBOL_GPL(ahci_platform_resume);
- #endif
-
--static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
-+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
-+ ahci_platform_resume);
-
- static const struct of_device_id ahci_of_match[] = {
- { .compatible = "snps,spear-ahci", },
-diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
-index b80c51c..542f268 100644
---- a/include/linux/ahci_platform.h
-+++ b/include/linux/ahci_platform.h
-@@ -50,4 +50,9 @@ int ahci_platform_init_host(struct platform_device *pdev,
- unsigned int force_port_map,
- unsigned int mask_port_map);
-
-+int ahci_platform_suspend_host(struct device *dev);
-+int ahci_platform_resume_host(struct device *dev);
-+int ahci_platform_suspend(struct device *dev);
-+int ahci_platform_resume(struct device *dev);
-+
- #endif /* _AHCI_PLATFORM_H */
---
-1.8.5.5
-
+++ /dev/null
-From 93dd2c512a24c552f1146d746aac112da7677430 Mon Sep 17 00:00:00 2001
-From: Olliver Schinagl <oliver@schinagl.nl>
-Date: Sat, 18 Jan 2014 15:00:45 +0100
-Subject: [PATCH] ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to
- ahci_platform
-
-This patch adds support for the ahci sata controler found on Allwinner A10
-and A20 SoCs to the ahci_platform driver.
-
-Orignally written by Olliver Schinagl using the approach of having a platform
-device which probe method creates a new child platform device which gets
-driven by ahci_platform.c, as done by ahci_imx.c .
-
-Refactored by Hans de Goede to add most of the non sunxi specific functionality
-to ahci_platform.c and use a platform_data pointer from of_device_id for the
-sunxi specific bits.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/ata/ahci-platform.txt | 15 +-
- drivers/ata/Kconfig | 9 +
- drivers/ata/Makefile | 1 +
- drivers/ata/ahci_sunxi.c | 249 +++++++++++++++++++++
- 4 files changed, 271 insertions(+), 3 deletions(-)
- create mode 100644 drivers/ata/ahci_sunxi.c
-
-diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-index 1ac807f..499bfed 100644
---- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
-+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
-@@ -4,7 +4,9 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
- Each SATA controller should have its own node.
-
- Required properties:
--- compatible : compatible list, contains "snps,spear-ahci"
-+- compatible : compatible list, one of "snps,spear-ahci",
-+ "snps,exynos5440-ahci", "ibm,476gtr-ahci", or
-+ "allwinner,sun4i-a10-ahci"
- - interrupts : <interrupt mapping for SATA IRQ>
- - reg : <registers mapping>
-
-@@ -13,10 +15,17 @@ Optional properties:
- - clocks : a list of phandle + clock specifier pairs
- - target-supply : regulator for SATA target power
-
--Example:
-+Examples:
- sata@ffe08000 {
- compatible = "snps,spear-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
--
- };
-+
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <56>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ target-supply = <®_ahci_5v>;
-+ };
-diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
-index 4e73772..cc67cc0 100644
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -106,6 +106,15 @@ config AHCI_IMX
-
- If unsure, say N.
-
-+config AHCI_SUNXI
-+ tristate "Allwinner sunxi AHCI SATA support"
-+ depends on ARCH_SUNXI && SATA_AHCI_PLATFORM
-+ help
-+ This option enables support for the Allwinner sunxi SoC's
-+ onboard AHCI SATA.
-+
-+ If unsure, say N.
-+
- config SATA_FSL
- tristate "Freescale 3.0Gbps SATA support"
- depends on FSL_SOC
-diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
-index 46518c6..246050b 100644
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
- obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
- obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
- obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
-+obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o
-
- # SFF w/ custom DMA
- obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
-diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
-new file mode 100644
-index 0000000..001f7dfc
---- /dev/null
-+++ b/drivers/ata/ahci_sunxi.c
-@@ -0,0 +1,249 @@
-+/*
-+ * Allwinner sunxi AHCI SATA platform driver
-+ * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
-+ * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
-+ * Daniel Wang <danielwang@allwinnertech.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ */
-+
-+#include <linux/ahci_platform.h>
-+#include <linux/clk.h>
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include "ahci.h"
-+
-+#define AHCI_BISTAFR 0x00a0
-+#define AHCI_BISTCR 0x00a4
-+#define AHCI_BISTFCTR 0x00a8
-+#define AHCI_BISTSR 0x00ac
-+#define AHCI_BISTDECR 0x00b0
-+#define AHCI_DIAGNR0 0x00b4
-+#define AHCI_DIAGNR1 0x00b8
-+#define AHCI_OOBR 0x00bc
-+#define AHCI_PHYCS0R 0x00c0
-+#define AHCI_PHYCS1R 0x00c4
-+#define AHCI_PHYCS2R 0x00c8
-+#define AHCI_TIMER1MS 0x00e0
-+#define AHCI_GPARAM1R 0x00e8
-+#define AHCI_GPARAM2R 0x00ec
-+#define AHCI_PPARAMR 0x00f0
-+#define AHCI_TESTR 0x00f4
-+#define AHCI_VERSIONR 0x00f8
-+#define AHCI_IDR 0x00fc
-+#define AHCI_RWCR 0x00fc
-+#define AHCI_P0DMACR 0x0170
-+#define AHCI_P0PHYCR 0x0178
-+#define AHCI_P0PHYSR 0x017c
-+
-+static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val &= ~(clr_val);
-+ writel(reg_val, reg);
-+}
-+
-+static void sunxi_setbits(void __iomem *reg, u32 set_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val |= set_val;
-+ writel(reg_val, reg);
-+}
-+
-+static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-+{
-+ u32 reg_val;
-+
-+ reg_val = readl(reg);
-+ reg_val &= ~(clr_val);
-+ reg_val |= set_val;
-+ writel(reg_val, reg);
-+}
-+
-+static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
-+{
-+ return (readl(reg) >> shift) & mask;
-+}
-+
-+static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-+{
-+ u32 reg_val;
-+ int timeout;
-+
-+ /* This magic is from the original code */
-+ writel(0, reg_base + AHCI_RWCR);
-+ mdelay(5);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-+ (0x7 << 24),
-+ (0x5 << 24) | BIT(23) | BIT(18));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
-+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
-+ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
-+ sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-+ (0x7 << 20), (0x3 << 20));
-+ sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
-+ (0x1f << 5), (0x19 << 5));
-+ mdelay(5);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-+
-+ timeout = 250; /* Power up takes aprox 50 us */
-+ do {
-+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
-+ if (reg_val == 0x02)
-+ break;
-+
-+ if (--timeout == 0) {
-+ dev_err(dev, "PHY power up failed.\n");
-+ return -EIO;
-+ }
-+ udelay(1);
-+ } while (1);
-+
-+ sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-+
-+ timeout = 100; /* Calibration takes aprox 10 us */
-+ do {
-+ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
-+ if (reg_val == 0x00)
-+ break;
-+
-+ if (--timeout == 0) {
-+ dev_err(dev, "PHY calibration failed.\n");
-+ return -EIO;
-+ }
-+ udelay(1);
-+ } while (1);
-+
-+ mdelay(15);
-+
-+ writel(0x7, reg_base + AHCI_RWCR);
-+
-+ return 0;
-+}
-+
-+static void ahci_sunxi_start_engine(struct ata_port *ap)
-+{
-+ void __iomem *port_mmio = ahci_port_base(ap);
-+ struct ahci_host_priv *hpriv = ap->host->private_data;
-+
-+ /* Setup DMA before DMA start */
-+ sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
-+
-+ /* Start DMA */
-+ sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
-+}
-+
-+static const struct ata_port_info ahci_sunxi_port_info = {
-+ AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
-+ AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
-+ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
-+ .pio_mask = ATA_PIO4,
-+ .udma_mask = ATA_UDMA6,
-+ .port_ops = &ahci_platform_ops,
-+};
-+
-+static int ahci_sunxi_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ahci_host_priv *hpriv;
-+ int rc;
-+
-+ hpriv = ahci_platform_get_resources(pdev);
-+ if (IS_ERR(hpriv))
-+ return PTR_ERR(hpriv);
-+
-+ hpriv->start_engine = ahci_sunxi_start_engine;
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+
-+ rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 0, 0);
-+ if (rc)
-+ goto disable_resources;
-+
-+ return 0;
-+
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-+ return rc;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+int ahci_sunxi_resume(struct device *dev)
-+{
-+ struct ata_host *host = dev_get_drvdata(dev);
-+ struct ahci_host_priv *hpriv = host->private_data;
-+ int rc;
-+
-+ rc = ahci_platform_enable_resources(hpriv);
-+ if (rc)
-+ return rc;
-+
-+ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
-+ if (rc)
-+ goto disable_resources;
-+
-+ rc = ahci_platform_resume_host(dev);
-+ if (rc)
-+ goto disable_resources;
-+
-+ return 0;
-+
-+disable_resources:
-+ ahci_platform_disable_resources(hpriv);
-+ return rc;
-+}
-+#endif
-+
-+static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
-+ ahci_sunxi_resume);
-+
-+static const struct of_device_id ahci_sunxi_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-ahci", },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
-+
-+static struct platform_driver ahci_sunxi_driver = {
-+ .probe = ahci_sunxi_probe,
-+ .remove = ata_platform_remove_one,
-+ .driver = {
-+ .name = "ahci-sunxi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = ahci_sunxi_of_match,
-+ .pm = &ahci_sunxi_pm_ops,
-+ },
-+};
-+module_platform_driver(ahci_sunxi_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
-+MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 90189e2c18e983da0ce22e44cd610f9ce2db69b1 Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Mon, 20 Jan 2014 16:32:33 +0200
-Subject: [PATCH] ata: ahci_platform: Add DT compatible for Synopsis DWC AHCI
- controller
-
-Add compatible string "snps,dwc-ahci", which should be used
-for Synopsis Designware SATA cores. e.g. on TI OMAP5 and DRA7 platforms.
-
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_platform.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index bdadec1..d7e55ba 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -609,6 +609,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
- { .compatible = "snps,spear-ahci", },
- { .compatible = "snps,exynos5440-ahci", },
- { .compatible = "ibm,476gtr-ahci", },
-+ { .compatible = "snps,dwc-ahci", },
- {},
- };
- MODULE_DEVICE_TABLE(of, ahci_of_match);
---
-1.8.5.5
-
+++ /dev/null
-From 154a670a945c54300749d5ba008f30bbd6089017 Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Mon, 27 Jan 2014 16:41:18 +0200
-Subject: [PATCH] ata: ahci_platform: Manage SATA PHY
-
-Some platforms have a PHY hooked up to the
-SATA controller. The PHY needs to be initialized
-and powered up for SATA to work. We do that
-using the PHY framework.
-
-CC: Balaji T K <balajitk@ti.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.h | 2 ++
- drivers/ata/ahci_platform.c | 47 +++++++++++++++++++++++++++++++++++++++++++--
- 2 files changed, 47 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index bf8100c..3ab7ac9 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -37,6 +37,7 @@
-
- #include <linux/clk.h>
- #include <linux/libata.h>
-+#include <linux/phy/phy.h>
- #include <linux/regulator/consumer.h>
-
- /* Enclosure Management Control */
-@@ -325,6 +326,7 @@ struct ahci_host_priv {
- u32 em_msg_type; /* EM message type */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- struct regulator *target_pwr; /* Optional */
-+ struct phy *phy; /* If platform uses phy */
- void *plat_data; /* Other platform data */
- /*
- * Optional ahci_start_engine override, if not set this gets set to the
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index d7e55ba..99d38c1 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -23,6 +23,7 @@
- #include <linux/platform_device.h>
- #include <linux/libata.h>
- #include <linux/ahci_platform.h>
-+#include <linux/phy/phy.h>
- #include "ahci.h"
-
- static void ahci_host_stop(struct ata_host *host);
-@@ -147,6 +148,7 @@ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
- * the following order:
- * 1) Regulator
- * 2) Clocks (through ahci_platform_enable_clks)
-+ * 3) Phy
- *
- * If resource enabling fails at any point the previous enabled
- * resources are disabled in reverse order.
-@@ -171,8 +173,23 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
- if (rc)
- goto disable_regulator;
-
-+ if (hpriv->phy) {
-+ rc = phy_init(hpriv->phy);
-+ if (rc)
-+ goto disable_clks;
-+
-+ rc = phy_power_on(hpriv->phy);
-+ if (rc) {
-+ phy_exit(hpriv->phy);
-+ goto disable_clks;
-+ }
-+ }
-+
- return 0;
-
-+disable_clks:
-+ ahci_platform_disable_clks(hpriv);
-+
- disable_regulator:
- if (hpriv->target_pwr)
- regulator_disable(hpriv->target_pwr);
-@@ -186,14 +203,20 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
- *
- * This function disables all ahci_platform managed resources in
- * the following order:
-- * 1) Clocks (through ahci_platform_disable_clks)
-- * 2) Regulator
-+ * 1) Phy
-+ * 2) Clocks (through ahci_platform_disable_clks)
-+ * 3) Regulator
- *
- * LOCKING:
- * None.
- */
- void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
- {
-+ if (hpriv->phy) {
-+ phy_power_off(hpriv->phy);
-+ phy_exit(hpriv->phy);
-+ }
-+
- ahci_platform_disable_clks(hpriv);
-
- if (hpriv->target_pwr)
-@@ -222,6 +245,7 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
- * 2) regulator for controlling the targets power (optional)
- * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
- * or for non devicetree enabled platforms a single clock
-+ * 4) phy (optional)
- *
- * LOCKING:
- * None.
-@@ -283,6 +307,25 @@ struct ahci_host_priv *ahci_platform_get_resources(
- hpriv->clks[i] = clk;
- }
-
-+ hpriv->phy = devm_phy_get(dev, "sata-phy");
-+ if (IS_ERR(hpriv->phy)) {
-+ rc = PTR_ERR(hpriv->phy);
-+ switch (rc) {
-+ case -ENODEV:
-+ case -ENOSYS:
-+ /* continue normally */
-+ hpriv->phy = NULL;
-+ break;
-+
-+ case -EPROBE_DEFER:
-+ goto err_out;
-+
-+ default:
-+ dev_err(dev, "couldn't get sata-phy\n");
-+ goto err_out;
-+ }
-+ }
-+
- devres_remove_group(dev, NULL);
- return hpriv;
-
---
-1.8.5.5
-
+++ /dev/null
-From 48379fed3987d587a25a48e155872e9d3125490d Mon Sep 17 00:00:00 2001
-From: Roger Quadros <rogerq@ti.com>
-Date: Wed, 9 Oct 2013 15:08:59 +0300
-Subject: [PATCH] ata: ahci_platform: runtime resume the device before use
-
-On OMAP platforms the device needs to be runtime resumed before
-it can be accessed. The OMAP HWMOD framework takes care of
-enabling the module and its resources based on the
-device's runtime PM state.
-
-In this patch we runtime resume during .probe() and runtime suspend
-after .remove().
-
-We also update the runtime PM state during .resume().
-
-CC: Balaji T K <balajitk@ti.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci.h | 1 +
- drivers/ata/ahci_platform.c | 15 +++++++++++++++
- 2 files changed, 16 insertions(+)
-
-diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
-index 3ab7ac9..51af275b 100644
---- a/drivers/ata/ahci.h
-+++ b/drivers/ata/ahci.h
-@@ -324,6 +324,7 @@ struct ahci_host_priv {
- u32 em_loc; /* enclosure management location */
- u32 em_buf_sz; /* EM buffer size in byte */
- u32 em_msg_type; /* EM message type */
-+ bool got_runtime_pm; /* Did we do pm_runtime_get? */
- struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
- struct regulator *target_pwr; /* Optional */
- struct phy *phy; /* If platform uses phy */
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 99d38c1..75698a4 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -24,6 +24,7 @@
- #include <linux/libata.h>
- #include <linux/ahci_platform.h>
- #include <linux/phy/phy.h>
-+#include <linux/pm_runtime.h>
- #include "ahci.h"
-
- static void ahci_host_stop(struct ata_host *host);
-@@ -229,6 +230,11 @@ static void ahci_platform_put_resources(struct device *dev, void *res)
- struct ahci_host_priv *hpriv = res;
- int c;
-
-+ if (hpriv->got_runtime_pm) {
-+ pm_runtime_put_sync(dev);
-+ pm_runtime_disable(dev);
-+ }
-+
- for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
- clk_put(hpriv->clks[c]);
- }
-@@ -326,6 +332,10 @@ struct ahci_host_priv *ahci_platform_get_resources(
- }
- }
-
-+ pm_runtime_enable(dev);
-+ pm_runtime_get_sync(dev);
-+ hpriv->got_runtime_pm = true;
-+
- devres_remove_group(dev, NULL);
- return hpriv;
-
-@@ -635,6 +645,11 @@ int ahci_platform_resume(struct device *dev)
- if (rc)
- goto disable_resources;
-
-+ /* We resumed so update PM runtime state */
-+ pm_runtime_disable(dev);
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+
- return 0;
-
- disable_resources:
---
-1.8.5.5
-
+++ /dev/null
-From 09de09bc2c236dccb0ed5ed38015e829550a5c28 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 23 Feb 2014 11:37:17 +0100
-Subject: [PATCH] ahci_sunxi: Use msleep instead of mdelay
-
-ahci_sunxi_phy_init is called from the probe and resume code paths, and
-sleeping is safe in both, so use msleep instead of mdelay.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/ata/ahci_sunxi.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
-index 001f7dfc..d1bf3f7 100644
---- a/drivers/ata/ahci_sunxi.c
-+++ b/drivers/ata/ahci_sunxi.c
-@@ -90,7 +90,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
-
- /* This magic is from the original code */
- writel(0, reg_base + AHCI_RWCR);
-- mdelay(5);
-+ msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
-@@ -105,7 +105,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
- (0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
- (0x1f << 5), (0x19 << 5));
-- mdelay(5);
-+ msleep(5);
-
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
-@@ -137,7 +137,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
- udelay(1);
- } while (1);
-
-- mdelay(15);
-+ msleep(15);
-
- writel(0x7, reg_base + AHCI_RWCR);
-
---
-1.8.5.5
-
+++ /dev/null
-From 3cae1df0e62432a80db86c80e261eb9bbed326ee Mon Sep 17 00:00:00 2001
-From: Oliver Schinagl <oliver@schinagl.nl>
-Date: Tue, 3 Dec 2013 12:10:11 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add ahci / sata support
-
-This patch adds sunxi sata support to A10 boards that have such a connector.
-Some boards also feature a regulator via a GPIO and support for this is also
-added.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ++++
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 +++++
- arch/arm/boot/dts/sun4i-a10.dtsi | 8 +++++++
- arch/arm/boot/dts/sunxi-ahci-reg.dtsi | 36 ++++++++++++++++++++++++++++++
- 4 files changed, 54 insertions(+)
- create mode 100644 arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index cbd2e13..d6ec839 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -35,6 +35,10 @@
- };
- };
-
-+ ahci: sata@01c18000 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- emac_power_pin_a1000: emac_power_pin@0 {
- allwinner,pins = "PH15";
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index b139ee6..6df237d8 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -12,6 +12,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard";
-@@ -33,6 +34,11 @@
- };
- };
-
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 336dbec..454077a 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -338,6 +338,14 @@
- #size-cells = <0>;
- };
-
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <56>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-diff --git a/arch/arm/boot/dts/sunxi-ahci-reg.dtsi b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-new file mode 100644
-index 0000000..7072af1
---- /dev/null
-+++ b/arch/arm/boot/dts/sunxi-ahci-reg.dtsi
-@@ -0,0 +1,36 @@
-+/*
-+ * sunxi boards sata target power supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
-+ allwinner,pins = "PB8";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_ahci_5v: ahci-5v {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ahci_pwr_pin_a>;
-+ regulator-name = "ahci-5v";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 1 8 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From c7b99b7afc3882c1b38a15da8d1625dd448c6fee Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 3 Jan 2014 10:27:51 +0100
-Subject: [PATCH] ARM: sun7i: dt: Add ahci / sata support
-
-This patch adds sunxi sata support to A20 boards that have such a connector.
-Some boards also feature a regulator via a GPIO and support for this is also
-added.
-
-Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 18 ++++++++++++++++++
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 6 ++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
- 4 files changed, 38 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 7bf4935..07823c2 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -13,12 +13,18 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard2";
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index 025ce52..403bd2e 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -13,13 +13,26 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Cubietech Cubietruck";
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
-+ allwinner,pins = "PH12";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
- led_pins_cubietruck: led_pins@0 {
- allwinner,pins = "PH7", "PH11", "PH20", "PH21";
- allwinner,function = "gpio_out";
-@@ -90,4 +103,10 @@
- gpios = <&pio 7 7 0>;
- };
- };
-+
-+ reg_ahci_5v: ahci-5v {
-+ pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
-+ gpio = <&pio 7 12 0>;
-+ status = "okay";
-+ };
- };
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index b02a796..d5c6799 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -13,12 +13,18 @@
-
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-
- / {
- model = "Olimex A20-Olinuxino Micro";
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index daaafd0..3385994 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -392,6 +392,14 @@
- #size-cells = <0>;
- };
-
-+ ahci: sata@01c18000 {
-+ compatible = "allwinner,sun4i-a10-ahci";
-+ reg = <0x01c18000 0x1000>;
-+ interrupts = <0 56 4>;
-+ clocks = <&pll6 0>, <&ahb_gates 25>;
-+ status = "disabled";
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 00f082cbfe43bd45ddcff3572875ee9fbeafdfdd Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 16:37:33 +0100
-Subject: [PATCH] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner
- sunxi SoCs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is based on the driver Allwinner ships in their Android kernel sources.
-
-Initial porting to upstream kernels done by David Lanzendörfer, additional
-fixes and cleanups by Hans de Goede.
-
-It uses dma in bus-master mode using a built-in designware idmac controller,
-which is identical to the one found in the mmc-dw hosts.
-The rest of the host is not identical to mmc-dw.
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/Kconfig | 7 +
- drivers/mmc/host/Makefile | 2 +
- drivers/mmc/host/sunxi-mmc.c | 876 +++++++++++++++++++++++++++++++++++++++++++
- drivers/mmc/host/sunxi-mmc.h | 239 ++++++++++++
- 4 files changed, 1124 insertions(+)
- create mode 100644 drivers/mmc/host/sunxi-mmc.c
- create mode 100644 drivers/mmc/host/sunxi-mmc.h
-
-diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index 1384f67..7caf266 100644
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -689,3 +689,10 @@ config MMC_REALTEK_PCI
- help
- Say Y here to include driver code to support SD/MMC card interface
- of Realtek PCI-E card reader
-+
-+config MMC_SUNXI
-+ tristate "Allwinner sunxi SD/MMC Host Controller support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the SD/MMC Host Controller on
-+ Allwinner sunxi SoCs.
-diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
-index 3483b6b..f3c7c243 100644
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -54,6 +54,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
-
- obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
-
-+obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
-+
- obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
- obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
- obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-new file mode 100644
-index 0000000..2dc446c
---- /dev/null
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -0,0 +1,876 @@
-+/*
-+ * Driver for sunxi SD/MMC host controllers
-+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
-+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
-+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
-+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+
-+#include <linux/clk.h>
-+#include <linux/clk-private.h>
-+#include <linux/clk/sunxi.h>
-+
-+#include <linux/gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+#include <linux/scatterlist.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+
-+#include <linux/of_address.h>
-+#include <linux/of_gpio.h>
-+#include <linux/of_platform.h>
-+
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/mmc/sdio.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/core.h>
-+#include <linux/mmc/card.h>
-+#include <linux/mmc/slot-gpio.h>
-+
-+#include "sunxi-mmc.h"
-+
-+static int sunxi_mmc_init_host(struct mmc_host *mmc)
-+{
-+ u32 rval;
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ int ret;
-+
-+ ret = clk_prepare_enable(smc_host->clk_ahb);
-+ if (ret) {
-+ dev_err(mmc_dev(smc_host->mmc), "AHB clk err %d\n", ret);
-+ return ret;
-+ }
-+ ret = clk_prepare_enable(smc_host->clk_mod);
-+ if (ret) {
-+ dev_err(mmc_dev(smc_host->mmc), "MOD clk err %d\n", ret);
-+ clk_disable_unprepare(smc_host->clk_ahb);
-+ return ret;
-+ }
-+
-+ /* reset controller */
-+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HARDWARE_RESET;
-+ mci_writel(smc_host, REG_GCTRL, rval);
-+
-+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
-+ mci_writel(smc_host, REG_TMOUT, 0xffffffff);
-+ mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
-+ mci_writel(smc_host, REG_RINTR, 0xffffffff);
-+ mci_writel(smc_host, REG_DBGC, 0xdeb);
-+ mci_writel(smc_host, REG_FUNS, 0xceaa0000);
-+ mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
-+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTERRUPT_ENABLE_BIT;
-+ rval &= ~SDXC_ACCESS_DONE_DIRECT;
-+ mci_writel(smc_host, REG_GCTRL, rval);
-+
-+ return 0;
-+}
-+
-+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
-+{
-+ mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
-+ clk_disable_unprepare(smc_host->clk_ahb);
-+ clk_disable_unprepare(smc_host->clk_mod);
-+}
-+
-+/* /\* UHS-I Operation Modes */
-+/* * DS 25MHz 12.5MB/s 3.3V */
-+/* * HS 50MHz 25MB/s 3.3V */
-+/* * SDR12 25MHz 12.5MB/s 1.8V */
-+/* * SDR25 50MHz 25MB/s 1.8V */
-+/* * SDR50 100MHz 50MB/s 1.8V */
-+/* * SDR104 208MHz 104MB/s 1.8V */
-+/* * DDR50 50MHz 50MB/s 1.8V */
-+/* * MMC Operation Modes */
-+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
-+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
-+/* * HSDDR 52MHz 104MB/s 3/1.8/1.2V */
-+/* * HS200 200MHz 200MB/s 1.8/1.2V */
-+/* * */
-+/* * Spec. Timing */
-+/* * SD3.0 */
-+/* * Fcclk Tcclk Fsclk Tsclk Tis Tih odly RTis RTih */
-+/* * 400K 2.5us 24M 41ns 5ns 5ns 1 2209ns 41ns */
-+/* * 25M 40ns 600M 1.67ns 5ns 5ns 3 14.99ns 5.01ns */
-+/* * 50M 20ns 600M 1.67ns 6ns 2ns 3 14.99ns 5.01ns */
-+/* * 50MDDR 20ns 600M 1.67ns 6ns 0.8ns 2 6.67ns 3.33ns */
-+/* * 104M 9.6ns 600M 1.67ns 3ns 0.8ns 1 7.93ns 1.67ns */
-+/* * 208M 4.8ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
-+
-+/* * 25M 40ns 300M 3.33ns 5ns 5ns 2 13.34ns 6.66ns */
-+/* * 50M 20ns 300M 3.33ns 6ns 2ns 2 13.34ns 6.66ns */
-+/* * 50MDDR 20ns 300M 3.33ns 6ns 0.8ns 1 6.67ns 3.33ns */
-+/* * 104M 9.6ns 300M 3.33ns 3ns 0.8ns 0 7.93ns 1.67ns */
-+/* * 208M 4.8ns 300M 3.33ns 1.4ns 0.8ns 0 3.13ns 1.67ns */
-+
-+/* * eMMC4.5 */
-+/* * 400K 2.5us 24M 41ns 3ns 3ns 1 2209ns 41ns */
-+/* * 25M 40ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
-+/* * 50M 20ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
-+/* * 50MDDR 20ns 600M 1.67ns 2.5ns 2.5ns 2 6.67ns 3.33ns */
-+/* * 200M 5ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
-+/* *\/ */
-+
-+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
-+ struct mmc_data *data)
-+{
-+ struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
-+ struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
-+ int i, max_len = (1 << host->idma_des_size_bits);
-+
-+ for (i = 0; i < data->sg_len; i++) {
-+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
-+ SDXC_IDMAC_DES0_DIC;
-+
-+ if (data->sg[i].length == max_len)
-+ pdes[i].buf_size = 0; /* 0 == max_len */
-+ else
-+ pdes[i].buf_size = data->sg[i].length;
-+
-+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
-+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
-+ }
-+
-+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
-+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
-+
-+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
-+}
-+
-+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
-+{
-+ if (data->flags & MMC_DATA_WRITE)
-+ return DMA_TO_DEVICE;
-+ else
-+ return DMA_FROM_DEVICE;
-+}
-+
-+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
-+ struct mmc_data *data)
-+{
-+ u32 dma_len;
-+ u32 i;
-+ u32 temp;
-+ struct scatterlist *sg;
-+
-+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
-+ sunxi_mmc_get_dma_dir(data));
-+ if (dma_len == 0) {
-+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ for_each_sg(data->sg, sg, data->sg_len, i) {
-+ if (sg->offset & 3 || sg->length & 3) {
-+ dev_err(mmc_dev(smc_host->mmc),
-+ "unaligned scatterlist: os %x length %d\n",
-+ sg->offset, sg->length);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ sunxi_mmc_init_idma_des(smc_host, data);
-+
-+ temp = mci_readl(smc_host, REG_GCTRL);
-+ temp |= SDXC_DMA_ENABLE_BIT;
-+ mci_writel(smc_host, REG_GCTRL, temp);
-+ temp |= SDXC_DMA_RESET;
-+ mci_writel(smc_host, REG_GCTRL, temp);
-+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
-+
-+ if (!(data->flags & MMC_DATA_WRITE))
-+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
-+
-+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
-+
-+ return 0;
-+}
-+
-+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
-+ struct mmc_request *req)
-+{
-+ u32 cmd_val = SDXC_START | SDXC_RESPONSE_EXPIRE | SDXC_STOP_ABORT_CMD
-+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
-+ u32 ri = 0;
-+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
-+
-+ mci_writel(host, REG_CARG, 0);
-+ mci_writel(host, REG_CMDR, cmd_val);
-+
-+ do {
-+ ri = mci_readl(host, REG_RINTR);
-+ } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
-+ time_before(jiffies, expire));
-+
-+ if (ri & SDXC_INTERRUPT_ERROR_BIT) {
-+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
-+ if (req->stop)
-+ req->stop->resp[0] = -ETIMEDOUT;
-+ } else {
-+ if (req->stop)
-+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
-+ }
-+
-+ mci_writel(host, REG_RINTR, 0xffff);
-+}
-+
-+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
-+{
-+ struct mmc_command *cmd = smc_host->mrq->cmd;
-+ struct mmc_data *data = smc_host->mrq->data;
-+
-+ /* For some cmds timeout is normal with sd/mmc cards */
-+ if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESPONSE_TIMEOUT &&
-+ (cmd->opcode == SD_IO_SEND_OP_COND || cmd->opcode == SD_IO_RW_DIRECT))
-+ return;
-+
-+ dev_err(mmc_dev(smc_host->mmc),
-+ "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
-+ smc_host->mmc->index, cmd->opcode,
-+ data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
-+ smc_host->int_sum & SDXC_RESPONSE_ERROR ? " RE" : "",
-+ smc_host->int_sum & SDXC_RESPONSE_CRC_ERROR ? " RCE" : "",
-+ smc_host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
-+ smc_host->int_sum & SDXC_RESPONSE_TIMEOUT ? " RTO" : "",
-+ smc_host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
-+ smc_host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
-+ smc_host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
-+ smc_host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
-+ smc_host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
-+ );
-+}
-+
-+static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
-+{
-+ struct mmc_request *mrq;
-+ unsigned long iflags;
-+
-+ spin_lock_irqsave(&host->lock, iflags);
-+
-+ mrq = host->mrq;
-+ if (!mrq) {
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+ dev_err(mmc_dev(host->mmc), "no request to finalize\n");
-+ return;
-+ }
-+
-+ if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
-+ sunxi_mmc_dump_errinfo(host);
-+ mrq->cmd->error = -ETIMEDOUT;
-+ if (mrq->data)
-+ mrq->data->error = -ETIMEDOUT;
-+ if (mrq->stop)
-+ mrq->stop->error = -ETIMEDOUT;
-+ } else {
-+ if (mrq->cmd->flags & MMC_RSP_136) {
-+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
-+ mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
-+ mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
-+ mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
-+ } else {
-+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
-+ }
-+ if (mrq->data)
-+ mrq->data->bytes_xfered =
-+ mrq->data->blocks * mrq->data->blksz;
-+ }
-+
-+ if (mrq->data) {
-+ struct mmc_data *data = mrq->data;
-+ u32 temp;
-+
-+ mci_writel(host, REG_IDST, 0x337);
-+ mci_writel(host, REG_DMAC, 0);
-+ temp = mci_readl(host, REG_GCTRL);
-+ mci_writel(host, REG_GCTRL, temp|SDXC_DMA_RESET);
-+ temp &= ~SDXC_DMA_ENABLE_BIT;
-+ mci_writel(host, REG_GCTRL, temp);
-+ temp |= SDXC_FIFO_RESET;
-+ mci_writel(host, REG_GCTRL, temp);
-+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
-+ sunxi_mmc_get_dma_dir(data));
-+ }
-+
-+ mci_writel(host, REG_RINTR, 0xffff);
-+
-+ dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
-+ mrq->cmd->resp[0], mrq->cmd->resp[1],
-+ mrq->cmd->resp[2], mrq->cmd->resp[3]);
-+
-+ host->mrq = NULL;
-+ host->int_sum = 0;
-+ host->wait_dma = 0;
-+
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+
-+ if (mrq->data && mrq->data->error) {
-+ dev_err(mmc_dev(host->mmc),
-+ "data error, sending stop command\n");
-+ sunxi_mmc_send_manual_stop(host, mrq);
-+ }
-+
-+ mmc_request_done(host->mmc, mrq);
-+}
-+
-+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
-+{
-+ struct sunxi_mmc_host *host = dev_id;
-+ u32 finalize = 0;
-+ u32 sdio_int = 0;
-+ u32 msk_int;
-+ u32 idma_int;
-+
-+ spin_lock(&host->lock);
-+
-+ idma_int = mci_readl(host, REG_IDST);
-+ msk_int = mci_readl(host, REG_MISTA);
-+
-+ dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
-+ host->mrq, msk_int, idma_int);
-+
-+ if (host->mrq) {
-+ if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
-+ host->wait_dma = 0;
-+
-+ host->int_sum |= msk_int;
-+
-+ /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finishing the req */
-+ if ((host->int_sum & SDXC_RESPONSE_TIMEOUT) &&
-+ !(host->int_sum & SDXC_COMMAND_DONE))
-+ mci_writel(host, REG_IMASK,
-+ host->sdio_imask | SDXC_COMMAND_DONE);
-+ else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
-+ finalize = 1; /* Don't wait for dma on error */
-+ else if (host->int_sum & SDXC_INTERRUPT_DONE_BIT && !host->wait_dma)
-+ finalize = 1; /* Done */
-+
-+ if (finalize) {
-+ mci_writel(host, REG_IMASK, host->sdio_imask);
-+ mci_writel(host, REG_IDIE, 0);
-+ }
-+ }
-+
-+ if (msk_int & SDXC_SDIO_INTERRUPT)
-+ sdio_int = 1;
-+
-+ mci_writel(host, REG_RINTR, msk_int);
-+ mci_writel(host, REG_IDST, idma_int);
-+
-+ spin_unlock(&host->lock);
-+
-+ if (finalize)
-+ tasklet_schedule(&host->tasklet);
-+
-+ if (sdio_int)
-+ mmc_signal_sdio_irq(host->mmc);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void sunxi_mmc_tasklet(unsigned long data)
-+{
-+ struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
-+ sunxi_mmc_finalize_request(smc_host);
-+}
-+
-+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
-+{
-+ unsigned long expire = jiffies + msecs_to_jiffies(2000);
-+ u32 rval;
-+
-+ rval = mci_readl(host, REG_CLKCR);
-+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
-+
-+ if (oclk_en)
-+ rval |= SDXC_CARD_CLOCK_ON;
-+
-+ if (!host->io_flag)
-+ rval |= SDXC_LOW_POWER_ON;
-+
-+ mci_writel(host, REG_CLKCR, rval);
-+
-+ rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
-+ if (host->voltage_switching)
-+ rval |= SDXC_VOLTAGE_SWITCH;
-+ mci_writel(host, REG_CMDR, rval);
-+
-+ do {
-+ rval = mci_readl(host, REG_CMDR);
-+ } while (time_before(jiffies, expire) && (rval & SDXC_START));
-+
-+ if (rval & SDXC_START) {
-+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
-+ host->ferror = 1;
-+ }
-+}
-+
-+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
-+ u32 oclk_dly, u32 sclk_dly)
-+{
-+ unsigned long iflags;
-+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
-+
-+ spin_lock_irqsave(&smc_host->lock, iflags);
-+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
-+ spin_unlock_irqrestore(&smc_host->lock, iflags);
-+}
-+
-+struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
-+ { MMC_CLK_400K, 0, 7 },
-+ { MMC_CLK_25M, 0, 5 },
-+ { MMC_CLK_50M, 3, 5 },
-+ { MMC_CLK_50MDDR, 2, 4 },
-+ { MMC_CLK_50MDDR_8BIT, 2, 4 },
-+ { MMC_CLK_100M, 1, 4 },
-+ { MMC_CLK_200M, 1, 4 },
-+};
-+
-+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
-+ unsigned int rate)
-+{
-+ u32 newrate;
-+ u32 src_clk;
-+ u32 oclk_dly;
-+ u32 sclk_dly;
-+ u32 temp;
-+ struct sunxi_mmc_clk_dly *dly = NULL;
-+
-+ newrate = clk_round_rate(smc_host->clk_mod, rate);
-+ if (smc_host->clk_mod_rate == newrate) {
-+ dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
-+ rate, newrate);
-+ return;
-+ }
-+
-+ dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
-+ rate, newrate);
-+
-+ /* setting clock rate */
-+ clk_disable(smc_host->clk_mod);
-+ clk_set_rate(smc_host->clk_mod, newrate);
-+ clk_enable(smc_host->clk_mod);
-+ smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
-+ dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
-+
-+ sunxi_mmc_oclk_onoff(smc_host, 0);
-+ /* clear internal divider */
-+ temp = mci_readl(smc_host, REG_CLKCR);
-+ temp &= ~0xff;
-+ mci_writel(smc_host, REG_CLKCR, temp);
-+
-+ /* determine delays */
-+ if (rate <= 400000) {
-+ dly = &mmc_clk_dly[MMC_CLK_400K];
-+ } else if (rate <= 25000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_25M];
-+ } else if (rate <= 50000000) {
-+ if (smc_host->ddr) {
-+ if (smc_host->bus_width == 8)
-+ dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
-+ else
-+ dly = &mmc_clk_dly[MMC_CLK_50MDDR];
-+ } else {
-+ dly = &mmc_clk_dly[MMC_CLK_50M];
-+ }
-+ } else if (rate <= 104000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_100M];
-+ } else if (rate <= 208000000) {
-+ dly = &mmc_clk_dly[MMC_CLK_200M];
-+ } else {
-+ dly = &mmc_clk_dly[MMC_CLK_50M];
-+ }
-+
-+ oclk_dly = dly->oclk_dly;
-+ sclk_dly = dly->sclk_dly;
-+
-+ src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
-+
-+ if (src_clk >= 300000000 && src_clk <= 400000000) {
-+ if (oclk_dly)
-+ oclk_dly--;
-+ if (sclk_dly)
-+ sclk_dly--;
-+ }
-+
-+ sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
-+ sunxi_mmc_oclk_onoff(smc_host, 1);
-+
-+ /* oclk_onoff sets various irq status bits, clear these */
-+ mci_writel(smc_host, REG_RINTR,
-+ mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
-+}
-+
-+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+ u32 temp;
-+ s32 err;
-+
-+ /* Set the power state */
-+ switch (ios->power_mode) {
-+ case MMC_POWER_ON:
-+ break;
-+
-+ case MMC_POWER_UP:
-+ if (!IS_ERR(host->vmmc)) {
-+ mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
-+ udelay(200);
-+ }
-+
-+ err = sunxi_mmc_init_host(mmc);
-+ if (err) {
-+ host->ferror = 1;
-+ return;
-+ }
-+ enable_irq(host->irq);
-+
-+ dev_dbg(mmc_dev(host->mmc), "power on!\n");
-+ host->ferror = 0;
-+ break;
-+
-+ case MMC_POWER_OFF:
-+ dev_dbg(mmc_dev(host->mmc), "power off!\n");
-+ disable_irq(host->irq);
-+ sunxi_mmc_exit_host(host);
-+ if (!IS_ERR(host->vmmc))
-+ mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
-+ host->ferror = 0;
-+ break;
-+ }
-+
-+ /* set bus width */
-+ switch (ios->bus_width) {
-+ case MMC_BUS_WIDTH_1:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
-+ host->bus_width = 1;
-+ break;
-+ case MMC_BUS_WIDTH_4:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
-+ host->bus_width = 4;
-+ break;
-+ case MMC_BUS_WIDTH_8:
-+ mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
-+ host->bus_width = 8;
-+ break;
-+ }
-+
-+ /* set ddr mode */
-+ temp = mci_readl(host, REG_GCTRL);
-+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
-+ temp |= SDXC_DDR_MODE;
-+ host->ddr = 1;
-+ } else {
-+ temp &= ~SDXC_DDR_MODE;
-+ host->ddr = 0;
-+ }
-+ mci_writel(host, REG_GCTRL, temp);
-+
-+ /* set up clock */
-+ if (ios->clock && ios->power_mode) {
-+ dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
-+ sunxi_mmc_clk_set_rate(host, ios->clock);
-+ usleep_range(50000, 55000);
-+ }
-+}
-+
-+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ unsigned long flags;
-+ int ret;
-+ u32 imask;
-+
-+ spin_lock_irqsave(&smc_host->lock, flags);
-+
-+ /* Make sure the controller is in a sane state before enabling irqs */
-+ ret = sunxi_mmc_init_host(host->mmc);
-+ if (ret) {
-+ spin_unlock_irqrestore(&smc_host->lock, flags);
-+ return ret;
-+ }
-+
-+ imask = mci_readl(smc_host, REG_IMASK);
-+ if (enable) {
-+ smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
-+ imask |= SDXC_SDIO_INTERRUPT;
-+ } else {
-+ smc_host->sdio_imask = 0;
-+ imask &= ~SDXC_SDIO_INTERRUPT;
-+ }
-+ mci_writel(smc_host, REG_IMASK, imask);
-+ spin_unlock_irqrestore(&smc_host->lock, flags);
-+}
-+
-+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
-+{
-+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
-+ mci_writel(smc_host, REG_HWRST, 0);
-+ udelay(10);
-+ mci_writel(smc_host, REG_HWRST, 1);
-+ udelay(300);
-+}
-+
-+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+ struct mmc_command *cmd = mrq->cmd;
-+ struct mmc_data *data = mrq->data;
-+ unsigned long iflags;
-+ u32 imask = SDXC_INTERRUPT_ERROR_BIT;
-+ u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
-+ u32 byte_cnt = 0;
-+ int ret;
-+
-+ if (!mmc_gpio_get_cd(mmc) || host->ferror) {
-+ dev_dbg(mmc_dev(host->mmc), "no medium present\n");
-+ mrq->cmd->error = -ENOMEDIUM;
-+ mmc_request_done(mmc, mrq);
-+ return;
-+ }
-+
-+ if (data) {
-+ byte_cnt = data->blksz * data->blocks;
-+ mci_writel(host, REG_BLKSZ, data->blksz);
-+ mci_writel(host, REG_BCNTR, byte_cnt);
-+ ret = sunxi_mmc_prepare_dma(host, data);
-+ if (ret < 0) {
-+ dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
-+ cmd->error = ret;
-+ cmd->data->error = ret;
-+ mmc_request_done(host->mmc, mrq);
-+ return;
-+ }
-+ }
-+
-+ if (cmd->opcode == MMC_GO_IDLE_STATE) {
-+ cmd_val |= SDXC_SEND_INIT_SEQUENCE;
-+ imask |= SDXC_COMMAND_DONE;
-+ }
-+
-+ if (cmd->opcode == SD_SWITCH_VOLTAGE) {
-+ cmd_val |= SDXC_VOLTAGE_SWITCH;
-+ imask |= SDXC_VOLTAGE_CHANGE_DONE;
-+ host->voltage_switching = 1;
-+ sunxi_mmc_oclk_onoff(host, 1);
-+ }
-+
-+ if (cmd->flags & MMC_RSP_PRESENT) {
-+ cmd_val |= SDXC_RESPONSE_EXPIRE;
-+ if (cmd->flags & MMC_RSP_136)
-+ cmd_val |= SDXC_LONG_RESPONSE;
-+ if (cmd->flags & MMC_RSP_CRC)
-+ cmd_val |= SDXC_CHECK_RESPONSE_CRC;
-+
-+ if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
-+ cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
-+ if (cmd->data->flags & MMC_DATA_STREAM) {
-+ imask |= SDXC_AUTO_COMMAND_DONE;
-+ cmd_val |= SDXC_SEQUENCE_MODE | SDXC_SEND_AUTO_STOP;
-+ }
-+ if (cmd->data->stop) {
-+ imask |= SDXC_AUTO_COMMAND_DONE;
-+ cmd_val |= SDXC_SEND_AUTO_STOP;
-+ } else
-+ imask |= SDXC_DATA_OVER;
-+
-+ if (cmd->data->flags & MMC_DATA_WRITE)
-+ cmd_val |= SDXC_WRITE;
-+ else
-+ host->wait_dma = 1;
-+ } else
-+ imask |= SDXC_COMMAND_DONE;
-+ } else
-+ imask |= SDXC_COMMAND_DONE;
-+
-+ dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
-+ cmd_val & 0x3f, cmd_val, cmd->arg, imask,
-+ mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
-+
-+ spin_lock_irqsave(&host->lock, iflags);
-+ host->mrq = mrq;
-+ mci_writel(host, REG_IMASK, host->sdio_imask | imask);
-+ spin_unlock_irqrestore(&host->lock, iflags);
-+
-+ mci_writel(host, REG_CARG, cmd->arg);
-+ mci_writel(host, REG_CMDR, cmd_val);
-+}
-+
-+static const struct of_device_id sunxi_mmc_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-mmc", },
-+ { .compatible = "allwinner,sun5i-a13-mmc", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
-+
-+static struct mmc_host_ops sunxi_mmc_ops = {
-+ .request = sunxi_mmc_request,
-+ .set_ios = sunxi_mmc_set_ios,
-+ .get_ro = mmc_gpio_get_ro,
-+ .get_cd = mmc_gpio_get_cd,
-+ .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
-+ .hw_reset = sunxi_mmc_hw_reset,
-+};
-+
-+static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-+ struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ int ret;
-+
-+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
-+ host->idma_des_size_bits = 13;
-+ else
-+ host->idma_des_size_bits = 16;
-+
-+ host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
-+ if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+
-+ host->reg_base = devm_ioremap_resource(&pdev->dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(host->reg_base))
-+ return PTR_ERR(host->reg_base);
-+
-+ host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(host->clk_ahb)) {
-+ dev_err(&pdev->dev, "Could not get ahb clock\n");
-+ return PTR_ERR(host->clk_ahb);
-+ }
-+
-+ host->clk_mod = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(host->clk_mod)) {
-+ dev_err(&pdev->dev, "Could not get mod clock\n");
-+ return PTR_ERR(host->clk_mod);
-+ }
-+
-+ /* Make sure the controller is in a sane state before enabling irqs */
-+ ret = sunxi_mmc_init_host(host->mmc);
-+ if (ret)
-+ return ret;
-+
-+ host->irq = platform_get_irq(pdev, 0);
-+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
-+ "sunxi-mmc", host);
-+ if (ret == 0)
-+ disable_irq(host->irq);
-+
-+ /* And put it back in reset */
-+ sunxi_mmc_exit_host(host);
-+
-+ return ret;
-+}
-+
-+static int sunxi_mmc_probe(struct platform_device *pdev)
-+{
-+ struct sunxi_mmc_host *host;
-+ struct mmc_host *mmc;
-+ int ret;
-+
-+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
-+ if (!mmc) {
-+ dev_err(&pdev->dev, "mmc alloc host failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ ret = mmc_of_parse(mmc);
-+ if (ret)
-+ goto error_free_host;
-+
-+ host = mmc_priv(mmc);
-+ host->mmc = mmc;
-+ spin_lock_init(&host->lock);
-+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
-+
-+ ret = sunxi_mmc_resource_request(host, pdev);
-+ if (ret)
-+ goto error_free_host;
-+
-+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
-+ &host->sg_dma, GFP_KERNEL);
-+ if (!host->sg_cpu) {
-+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
-+ ret = -ENOMEM;
-+ goto error_free_host;
-+ }
-+
-+ mmc->ops = &sunxi_mmc_ops;
-+ mmc->max_blk_count = 8192;
-+ mmc->max_blk_size = 4096;
-+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
-+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
-+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
-+ /* 400kHz ~ 50MHz */
-+ mmc->f_min = 400000;
-+ mmc->f_max = 50000000;
-+ /* available voltages */
-+ if (!IS_ERR(host->vmmc))
-+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
-+ else
-+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
-+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
-+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-+
-+ ret = mmc_add_host(mmc);
-+
-+ if (ret)
-+ goto error_free_dma;
-+
-+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
-+ platform_set_drvdata(pdev, mmc);
-+ return 0;
-+
-+error_free_dma:
-+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-+error_free_host:
-+ mmc_free_host(mmc);
-+ return ret;
-+}
-+
-+static int sunxi_mmc_remove(struct platform_device *pdev)
-+{
-+ struct mmc_host *mmc = platform_get_drvdata(pdev);
-+ struct sunxi_mmc_host *host = mmc_priv(mmc);
-+
-+ mmc_remove_host(mmc);
-+ sunxi_mmc_exit_host(host);
-+ tasklet_disable(&host->tasklet);
-+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
-+ mmc_free_host(mmc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sunxi_mmc_driver = {
-+ .driver = {
-+ .name = "sunxi-mmc",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
-+ },
-+ .probe = sunxi_mmc_probe,
-+ .remove = sunxi_mmc_remove,
-+};
-+module_platform_driver(sunxi_mmc_driver);
-+
-+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
-+MODULE_ALIAS("platform:sunxi-mmc");
-diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
-new file mode 100644
-index 0000000..cbd6d49
---- /dev/null
-+++ b/drivers/mmc/host/sunxi-mmc.h
-@@ -0,0 +1,239 @@
-+/*
-+ * Driver for sunxi SD/MMC host controllers
-+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
-+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh@reuuimllatech.com>
-+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
-+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#ifndef __SUNXI_MCI_H__
-+#define __SUNXI_MCI_H__
-+
-+/* register offset define */
-+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
-+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
-+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
-+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
-+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
-+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
-+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
-+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
-+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
-+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
-+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
-+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
-+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
-+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
-+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
-+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
-+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
-+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
-+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
-+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
-+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
-+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
-+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
-+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
-+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
-+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
-+#define SDXC_REG_CHDA (0x90)
-+#define SDXC_REG_CBDA (0x94)
-+
-+#define mci_readl(host, reg) \
-+ readl((host)->reg_base + SDXC_##reg)
-+#define mci_writel(host, reg, value) \
-+ writel((value), (host)->reg_base + SDXC_##reg)
-+
-+/* global control register bits */
-+#define SDXC_SOFT_RESET BIT(0)
-+#define SDXC_FIFO_RESET BIT(1)
-+#define SDXC_DMA_RESET BIT(2)
-+#define SDXC_HARDWARE_RESET (SDXC_SOFT_RESET|SDXC_FIFO_RESET|SDXC_DMA_RESET)
-+#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
-+#define SDXC_DMA_ENABLE_BIT BIT(5)
-+#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
-+#define SDXC_POSEDGE_LATCH_DATA BIT(9)
-+#define SDXC_DDR_MODE BIT(10)
-+#define SDXC_MEMORY_ACCESS_DONE BIT(29)
-+#define SDXC_ACCESS_DONE_DIRECT BIT(30)
-+#define SDXC_ACCESS_BY_AHB BIT(31)
-+#define SDXC_ACCESS_BY_DMA (0U << 31)
-+/* clock control bits */
-+#define SDXC_CARD_CLOCK_ON BIT(16)
-+#define SDXC_LOW_POWER_ON BIT(17)
-+/* bus width */
-+#define SDXC_WIDTH1 (0)
-+#define SDXC_WIDTH4 (1)
-+#define SDXC_WIDTH8 (2)
-+/* smc command bits */
-+#define SDXC_RESPONSE_EXPIRE BIT(6)
-+#define SDXC_LONG_RESPONSE BIT(7)
-+#define SDXC_CHECK_RESPONSE_CRC BIT(8)
-+#define SDXC_DATA_EXPIRE BIT(9)
-+#define SDXC_WRITE BIT(10)
-+#define SDXC_SEQUENCE_MODE BIT(11)
-+#define SDXC_SEND_AUTO_STOP BIT(12)
-+#define SDXC_WAIT_PRE_OVER BIT(13)
-+#define SDXC_STOP_ABORT_CMD BIT(14)
-+#define SDXC_SEND_INIT_SEQUENCE BIT(15)
-+#define SDXC_UPCLK_ONLY BIT(21)
-+#define SDXC_READ_CEATA_DEV BIT(22)
-+#define SDXC_CCS_EXPIRE BIT(23)
-+#define SDXC_ENABLE_BIT_BOOT BIT(24)
-+#define SDXC_ALT_BOOT_OPTIONS BIT(25)
-+#define SDXC_BOOT_ACK_EXPIRE BIT(26)
-+#define SDXC_BOOT_ABORT BIT(27)
-+#define SDXC_VOLTAGE_SWITCH BIT(28)
-+#define SDXC_USE_HOLD_REGISTER BIT(29)
-+#define SDXC_START BIT(31)
-+/* interrupt bits */
-+#define SDXC_RESPONSE_ERROR BIT(1)
-+#define SDXC_COMMAND_DONE BIT(2)
-+#define SDXC_DATA_OVER BIT(3)
-+#define SDXC_TX_DATA_REQUEST BIT(4)
-+#define SDXC_RX_DATA_REQUEST BIT(5)
-+#define SDXC_RESPONSE_CRC_ERROR BIT(6)
-+#define SDXC_DATA_CRC_ERROR BIT(7)
-+#define SDXC_RESPONSE_TIMEOUT BIT(8)
-+#define SDXC_DATA_TIMEOUT BIT(9)
-+#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
-+#define SDXC_FIFO_RUN_ERROR BIT(11)
-+#define SDXC_HARD_WARE_LOCKED BIT(12)
-+#define SDXC_START_BIT_ERROR BIT(13)
-+#define SDXC_AUTO_COMMAND_DONE BIT(14)
-+#define SDXC_END_BIT_ERROR BIT(15)
-+#define SDXC_SDIO_INTERRUPT BIT(16)
-+#define SDXC_CARD_INSERT BIT(30)
-+#define SDXC_CARD_REMOVE BIT(31)
-+#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESPONSE_ERROR | SDXC_RESPONSE_CRC_ERROR | \
-+ SDXC_DATA_CRC_ERROR | SDXC_RESPONSE_TIMEOUT | \
-+ SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
-+ SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | \
-+ SDXC_END_BIT_ERROR) /* 0xbbc2 */
-+#define SDXC_INTERRUPT_DONE_BIT (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
-+ SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
-+/* status */
-+#define SDXC_RXWL_FLAG BIT(0)
-+#define SDXC_TXWL_FLAG BIT(1)
-+#define SDXC_FIFO_EMPTY BIT(2)
-+#define SDXC_FIFO_FULL BIT(3)
-+#define SDXC_CARD_PRESENT BIT(8)
-+#define SDXC_CARD_DATA_BUSY BIT(9)
-+#define SDXC_DATA_FSM_BUSY BIT(10)
-+#define SDXC_DMA_REQUEST BIT(31)
-+#define SDXC_FIFO_SIZE (16)
-+/* Function select */
-+#define SDXC_CEATA_ON (0xceaaU << 16)
-+#define SDXC_SEND_IRQ_RESPONSE BIT(0)
-+#define SDXC_SDIO_READ_WAIT BIT(1)
-+#define SDXC_ABORT_READ_DATA BIT(2)
-+#define SDXC_SEND_CCSD BIT(8)
-+#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
-+#define SDXC_CEATA_DEV_INTERRUPT_ENABLE_BIT BIT(10)
-+/* IDMA controller bus mod bit field */
-+#define SDXC_IDMAC_SOFT_RESET BIT(0)
-+#define SDXC_IDMAC_FIX_BURST BIT(1)
-+#define SDXC_IDMAC_IDMA_ON BIT(7)
-+#define SDXC_IDMAC_REFETCH_DES BIT(31)
-+/* IDMA status bit field */
-+#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
-+#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
-+#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
-+#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
-+#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
-+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
-+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
-+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_TX BIT(10)
-+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_RX BIT(10)
-+#define SDXC_IDMAC_IDLE (0U << 13)
-+#define SDXC_IDMAC_SUSPEND (1U << 13)
-+#define SDXC_IDMAC_DESC_READ (2U << 13)
-+#define SDXC_IDMAC_DESC_CHECK (3U << 13)
-+#define SDXC_IDMAC_READ_REQUEST_WAIT (4U << 13)
-+#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5U << 13)
-+#define SDXC_IDMAC_READ (6U << 13)
-+#define SDXC_IDMAC_WRITE (7U << 13)
-+#define SDXC_IDMAC_DESC_CLOSE (8U << 13)
-+
-+/*
-+* If the idma-des-size-bits of property is ie 13, bufsize bits are:
-+* Bits 0-12: buf1 size
-+* Bits 13-25: buf2 size
-+* Bits 26-31: not used
-+* Since we only ever set buf1 size, we can simply store it directly.
-+*/
-+#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
-+#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
-+#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
-+#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
-+#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
-+#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
-+#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
-+
-+struct sunxi_idma_des {
-+ u32 config;
-+ u32 buf_size;
-+ u32 buf_addr_ptr1;
-+ u32 buf_addr_ptr2;
-+};
-+
-+struct sunxi_mmc_host {
-+ struct mmc_host *mmc;
-+ struct regulator *vmmc;
-+
-+ /* IO mapping base */
-+ void __iomem *reg_base;
-+
-+ spinlock_t lock;
-+ struct tasklet_struct tasklet;
-+
-+ /* clock management */
-+ struct clk *clk_ahb;
-+ struct clk *clk_mod;
-+
-+ /* ios information */
-+ u32 clk_mod_rate;
-+ u32 bus_width;
-+ u32 idma_des_size_bits;
-+ u32 ddr;
-+ u32 voltage_switching;
-+
-+ /* irq */
-+ int irq;
-+ u32 int_sum;
-+ u32 sdio_imask;
-+
-+ /* flags */
-+ u32 power_on:1;
-+ u32 io_flag:1;
-+ u32 wait_dma:1;
-+
-+ dma_addr_t sg_dma;
-+ void *sg_cpu;
-+
-+ struct mmc_request *mrq;
-+ u32 ferror;
-+};
-+
-+#define MMC_CLK_400K 0
-+#define MMC_CLK_25M 1
-+#define MMC_CLK_50M 2
-+#define MMC_CLK_50MDDR 3
-+#define MMC_CLK_50MDDR_8BIT 4
-+#define MMC_CLK_100M 5
-+#define MMC_CLK_200M 6
-+#define MMC_CLK_MOD_NUM 7
-+
-+struct sunxi_mmc_clk_dly {
-+ u32 mode;
-+ u32 oclk_dly;
-+ u32 sclk_dly;
-+};
-+
-+#endif
---
-1.8.5.5
-
+++ /dev/null
-From 40889884d53094fe9987a45f9df99fdf1f311910 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 16 Feb 2014 10:47:51 +0100
-Subject: [PATCH] sunxi-mmc: Simplify clk delay setting
-
-clk_sunxi_mmc_phase_control() does its own locking, so there is no need to
-lock at the host. Without the locking having a separate sunxi_mmc_set_clk_dly()
-makes no sense, so simply call clk_sunxi_mmc_phase_control() directly.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 14 ++------------
- 1 file changed, 2 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index f33bc30..f4bfaf0 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -420,17 +420,6 @@ static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
- }
- }
-
--static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
-- u32 oclk_dly, u32 sclk_dly)
--{
-- unsigned long iflags;
-- struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
--
-- spin_lock_irqsave(&smc_host->lock, iflags);
-- clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
-- spin_unlock_irqrestore(&smc_host->lock, iflags);
--}
--
- struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
- { MMC_CLK_400K, 0, 7 },
- { MMC_CLK_25M, 0, 5 },
-@@ -450,6 +439,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
- u32 sclk_dly;
- u32 temp;
- struct sunxi_mmc_clk_dly *dly = NULL;
-+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
-
- newrate = clk_round_rate(smc_host->clk_mod, rate);
- if (smc_host->clk_mod_rate == newrate) {
-@@ -508,7 +498,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
- sclk_dly--;
- }
-
-- sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
-+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
- sunxi_mmc_oclk_onoff(smc_host, 1);
-
- /* oclk_onoff sets various irq status bits, clear these */
---
-1.8.5.5
-
+++ /dev/null
-From 0a6ec6db90c73b037428bf3a94a6281754007c25 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 16:55:54 +0100
-Subject: [PATCH] sunxi-mmc: Don't set mmc clk in low power mode
-
-The android driver uses an io-flag to descern whether a controller is
-hooked up to a sdcard slot, or to an onboard sdio dev. And for sdcard slots
-it sets the clock in a low-power mode.
-
-This is causing transmission errors when talking to the sdio-wifi on the
-cubietruck, and this may be the cause of problems with some type sdcards
-too. This patch fixes things by simply never setting the clk in low power
-mode.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 3 ---
- drivers/mmc/host/sunxi-mmc.h | 1 -
- 2 files changed, 4 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index f4bfaf0..c1a9d8a 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -400,9 +400,6 @@ static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
- if (oclk_en)
- rval |= SDXC_CARD_CLOCK_ON;
-
-- if (!host->io_flag)
-- rval |= SDXC_LOW_POWER_ON;
--
- mci_writel(host, REG_CLKCR, rval);
-
- rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
-diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
-index cbd6d49..a738850 100644
---- a/drivers/mmc/host/sunxi-mmc.h
-+++ b/drivers/mmc/host/sunxi-mmc.h
-@@ -211,7 +211,6 @@ struct sunxi_mmc_host {
-
- /* flags */
- u32 power_on:1;
-- u32 io_flag:1;
- u32 wait_dma:1;
-
- dma_addr_t sg_dma;
---
-1.8.5.5
-
+++ /dev/null
-From 3ec947a9717509e204c7f09609717951beb7ef04 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:11:58 +0100
-Subject: [PATCH] sunxi-mmc: Stop claiming UHS modes
-
-UHS requires a regulator to set the signaling voltage, as well as special
-code to handle the signal voltage switching. We've never added the code
-for this from the android driver to the upstream driver, so stop claiming
-support for this.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index c1a9d8a..2eaed10 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -803,8 +803,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-
- mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-- MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
-- MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
-+ MMC_CAP_SDIO_IRQ;
- mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-
- ret = mmc_add_host(mmc);
---
-1.8.5.5
-
+++ /dev/null
-From dffb4d4d1fe3a6ba93102756152ec4518dbeac00 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:13:19 +0100
-Subject: [PATCH] sunxi-mmc: Or in caps, rather then overriding them
-
-Now that we use mmc_of_parse() there are already some caps set by mmc_of_parse,
-so or in our driver caps, rather then using an assignment. This fixes the
-card running only in 1 bit mode instead of 4 bit mode problem we've had
-since we switched to using mmc_of_parse().
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index 2eaed10..d5e8ff9 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -802,9 +802,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- else
- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-
-- mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-+ mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
- MMC_CAP_SDIO_IRQ;
-- mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
-+ mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
-
- ret = mmc_add_host(mmc);
-
---
-1.8.5.5
-
+++ /dev/null
-From 73797537f3904fec60a647b3b209bf7add092ad5 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 21:59:08 +0100
-Subject: [PATCH] sunxi-mmc: Don't call mmc_of_parse until we're ready to
-
-mmc_of_parse registers an irq handler for the gpio pins for cd, this irq
-handler will reference host->ops, so don't call mmc_of_parse until we're
-done setting everything up.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 9 ++++-----
- 1 file changed, 4 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index d5e8ff9..cceae68 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -766,10 +766,6 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- return -ENOMEM;
- }
-
-- ret = mmc_of_parse(mmc);
-- if (ret)
-- goto error_free_host;
--
- host = mmc_priv(mmc);
- host->mmc = mmc;
- spin_lock_init(&host->lock);
-@@ -806,8 +802,11 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
- MMC_CAP_SDIO_IRQ;
- mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
-
-- ret = mmc_add_host(mmc);
-+ ret = mmc_of_parse(mmc);
-+ if (ret)
-+ goto error_free_dma;
-
-+ ret = mmc_add_host(mmc);
- if (ret)
- goto error_free_dma;
-
---
-1.8.5.5
-
+++ /dev/null
-From 7bd0d82ef525e8949425fe271fb86eacf3822821 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 15 Dec 2013 19:44:01 +0100
-Subject: [PATCH] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
- create mode 100644 include/linux/clk/sunxi.h
-
-diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
-new file mode 100644
-index 0000000..1ef5c89
---- /dev/null
-+++ b/include/linux/clk/sunxi.h
-@@ -0,0 +1,22 @@
-+/*
-+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __LINUX_CLK_SUNXI_H_
-+#define __LINUX_CLK_SUNXI_H_
-+
-+#include <linux/clk.h>
-+
-+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
-+
-+#endif
---
-1.8.5.5
-
+++ /dev/null
-From fcba369ee1af8657353bb1e37807aa492c462263 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 20:29:17 -0300
-Subject: [PATCH] clk: sunxi: Implement MMC phase control
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 3283179..46a38b4 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -500,6 +500,41 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
-
-
- /**
-+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
-+ */
-+
-+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
-+{
-+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
-+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-+
-+ struct clk_composite *composite = to_clk_composite(hw);
-+ struct clk_hw *rate_hw = composite->rate_hw;
-+ struct clk_factors *factors = to_clk_factors(rate_hw);
-+ unsigned long flags = 0;
-+ u32 reg;
-+
-+ if (factors->lock)
-+ spin_lock_irqsave(factors->lock, flags);
-+
-+ reg = readl(factors->reg);
-+
-+ /* set sample clock phase control */
-+ reg &= ~(0x7 << 20);
-+ reg |= ((sample & 0x7) << 20);
-+
-+ /* set output clock phase control */
-+ reg &= ~(0x7 << 8);
-+ reg |= ((output & 0x7) << 8);
-+
-+ writel(reg, factors->reg);
-+
-+ if (factors->lock)
-+ spin_unlock_irqrestore(factors->lock, flags);
-+}
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
---
-1.8.5.5
-
+++ /dev/null
-From 0483aa124d32bdcafc84623a31141a49e71cc72d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 16 Feb 2014 08:54:20 +0100
-Subject: [PATCH] sunxi-mmc: fixup: revert "add host initialization for when
- the sdio irq is enabled"
-
-This is not necessary since when the host is not initialized at this point
-yet the irq line from the mmc controller is not enabled, so writing the
-host controller interrupt mask cannot cause interrupts at this point.
-
-More over doing this is wrong, as it leads to unbalanced calling of
-clk_prepare_enable and regulator_power_on.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/mmc/host/sunxi-mmc.c | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
-index 2dc446c..f33bc30 100644
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -593,18 +593,9 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
- {
- struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
- unsigned long flags;
-- int ret;
- u32 imask;
-
- spin_lock_irqsave(&smc_host->lock, flags);
--
-- /* Make sure the controller is in a sane state before enabling irqs */
-- ret = sunxi_mmc_init_host(host->mmc);
-- if (ret) {
-- spin_unlock_irqrestore(&smc_host->lock, flags);
-- return ret;
-- }
--
- imask = mci_readl(smc_host, REG_IMASK);
- if (enable) {
- smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
---
-1.8.5.5
-
+++ /dev/null
-From 85f17a0d652853455ac633fc965cea8431038518 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 14 Dec 2013 17:20:13 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix sun5i-a13 port F multiplexing
-
-The correct value for selecting the mmc0 function on port F pins is 2 not 4,
-as per the data-sheet:
-http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/pinctrl/pinctrl-sunxi-pins.h | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
-index 6fd8d4d..3d60669 100644
---- a/drivers/pinctrl/pinctrl-sunxi-pins.h
-+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
-@@ -1932,27 +1932,27 @@
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
-- SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
-+ SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
- /* Hole */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
- SUNXI_FUNCTION(0x0, "gpio_in"),
---
-1.8.5.5
-
+++ /dev/null
-From 9d506cbf0e7b0e017d78f244e2b4c0fc71206c6c Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 15 Feb 2014 12:56:42 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix masking when setting irq type
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/pinctrl/pinctrl-sunxi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
-index cc9bd1b..917af0a 100644
---- a/drivers/pinctrl/pinctrl-sunxi.c
-+++ b/drivers/pinctrl/pinctrl-sunxi.c
-@@ -583,7 +583,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
- spin_lock_irqsave(&pctl->lock, flags);
-
- regval = readl(pctl->membase + reg);
-- regval &= ~IRQ_CFG_IRQ_MASK;
-+ regval &= ~(IRQ_CFG_IRQ_MASK << index);
- writel(regval | (mode << index), pctl->membase + reg);
-
- spin_unlock_irqrestore(&pctl->lock, flags);
---
-1.8.5.5
-
+++ /dev/null
-From a5f3d2672d5b9efe93be0bf66d69156bf806220b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 22:04:20 +0100
-Subject: [PATCH] pinctrl-sunxi: Fix interrupt register offset calculation
-
-This fixing setting the interrupt type for eints >= 8.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/pinctrl/pinctrl-sunxi.h | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
-index 01c494f..552b0e9 100644
---- a/drivers/pinctrl/pinctrl-sunxi.h
-+++ b/drivers/pinctrl/pinctrl-sunxi.h
-@@ -511,7 +511,7 @@ static inline u32 sunxi_pull_offset(u16 pin)
-
- static inline u32 sunxi_irq_cfg_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
- return reg + IRQ_CFG_REG;
- }
-
-@@ -523,7 +523,7 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
-
- static inline u32 sunxi_irq_ctrl_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
- return reg + IRQ_CTRL_REG;
- }
-
-@@ -535,7 +535,7 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
-
- static inline u32 sunxi_irq_status_reg(u16 irq)
- {
-- u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
-+ u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
- return reg + IRQ_STATUS_REG;
- }
-
---
-1.8.5.5
-
+++ /dev/null
-From 6c6bc98f6a2b1f91071564efdb77c90307610018 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:51 +0100
-Subject: [PATCH] ARM: dts: sun4i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 8 +++++
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8 +++++
- arch/arm/boot/dts/sun4i-a10.dtsi | 54 ++++++++++++++++++++++++++++++
- 3 files changed, 70 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index d6ec839..4b2a694 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -35,6 +35,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- status = "okay";
- };
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index 6df237d8..ef85b8e 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -34,6 +34,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 454077a..a8e0df3 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -338,6 +338,50 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ compatible = "allwinner,sun4i-a10-mmc";
-+ reg = <0x01c12000 0x1000>;
-+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <35>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ cd-inverted;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -416,6 +456,20 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <2>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
-+ allwinner,pins = "PH1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 5bfbb46a8685de4c67f084aea983fc9a50c882ad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:29 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 ++++++++++++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 44 ++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15 ++++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 37 ++++++++++++++++++++
- 5 files changed, 141 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-index 3c9f8b3..5c7b454 100644
---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-@@ -34,7 +34,37 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxino_micro>;
-+ cd-gpios = <&pio 6 1 0>; /* PG1 */
-+ status = "okay";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc1_pins_a>;
-+ pinctrl-1 = <&mmc1_cd_pin_olinuxino_micro>;
-+ cd-gpios = <&pio 6 13 0>; /* PG13 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
-+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
-+ allwinner,pins = "PG13";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PE3";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 3a9b33d..3a7039e 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -299,6 +299,36 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-@@ -369,6 +399,20 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc1_pins_a: mmc1@0 {
-+ allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
-+ allwinner,function = "mmc1";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-index fe2ce0a..2f08bb2 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
-@@ -20,7 +20,22 @@
- compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxinom>;
-+ cd-gpios = <&pio 6 0 0>; /* PG0 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG0";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxinom: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index a4ba5ff..a7280f5 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -19,7 +19,22 @@
- compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_olinuxino>;
-+ cd-gpios = <&pio 6 0 0>; /* PG0 */
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
-+ mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
-+ allwinner,pins = "PG0";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PG9";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 9612c52..63a35b8 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -281,6 +281,36 @@
- #size-cells = <1>;
- ranges;
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <32>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <33>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <34>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-@@ -333,6 +363,13 @@
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From a3bddfdd19c49f0bde7aa2ff496773c575763d07 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <david.lanzendoerfer@o2s.ch>
-Date: Sat, 15 Feb 2014 14:02:01 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add support for mmc
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 ++++
- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 ++++
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 ++++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++++
- 4 files changed, 100 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index 07823c2..a8186f5 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -20,6 +20,14 @@
- compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index 403bd2e..6cd7cca 100644
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index d5c6799..d4e2355 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -20,12 +20,35 @@
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc3_pins_a>;
-+ pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
-+ cd-gpios = <&pio 7 11 0>; /* PH11 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
- pinctrl@01c20800 {
-+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
-+ allwinner,pins = "PH11";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
- led_pins_olinuxino: led_pins@0 {
- allwinner,pins = "PH2";
- allwinner,function = "gpio_out";
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-index cb25d3c..66bb3ef 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
-@@ -20,6 +20,14 @@
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 3385994..3bc6ac5 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -392,6 +392,46 @@
- #size-cells = <0>;
- };
-
-+ mmc0: mmc@01c0f000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c0f000 0x1000>;
-+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 32 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc1: mmc@01c10000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c10000 0x1000>;
-+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 33 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc2: mmc@01c11000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c11000 0x1000>;
-+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 34 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ mmc3: mmc@01c12000 {
-+ compatible = "allwinner,sun5i-a13-mmc";
-+ reg = <0x01c12000 0x1000>;
-+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
-+ clock-names = "ahb", "mod";
-+ interrupts = <0 35 4>;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -510,6 +550,27 @@
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-+
-+ mmc0_pins_a: mmc0@0 {
-+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
-+ allwinner,function = "mmc0";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
-+ allwinner,pins = "PH1";
-+ allwinner,function = "gpio_in";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <1>;
-+ };
-+
-+ mmc3_pins_a: mmc3@0 {
-+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
-+ allwinner,function = "mmc3";
-+ allwinner,drive = <3>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 1fa41bc5a6659e453ca19086f195b02a23dc3bbe Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:25:54 +0100
-Subject: [PATCH] ARM: sun5i: dt: Fixup mmc bindings
-
-1) Now that we're no longer overriding the caps set by mmc_of_parse we need
-to set cd-inverted for our card detection to work.
-
-2) Now that we no longer claim UHS modes support we will never use any DDR
-modes, so drive-strength 2 is enough for the mmc data pins.
-
-3) mmc1 on the A13 is not routed to any pins, and thus unusable, remove it
-from the dtsi
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++--
- arch/arm/boot/dts/sun5i-a13.dtsi | 14 +++-----------
- 2 files changed, 8 insertions(+), 13 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 3a7039e..15dfa9a 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -306,6 +306,7 @@
- clock-names = "ahb", "mod";
- interrupts = <32>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -316,6 +317,7 @@
- clock-names = "ahb", "mod";
- interrupts = <33>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -326,6 +328,7 @@
- clock-names = "ahb", "mod";
- interrupts = <34>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -403,14 +406,14 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-
- mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
- allwinner,function = "mmc1";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 63a35b8..14a99d0 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -288,16 +288,7 @@
- clock-names = "ahb", "mod";
- interrupts = <32>;
- bus-width = <4>;
-- status = "disabled";
-- };
--
-- mmc1: mmc@01c10000 {
-- compatible = "allwinner,sun5i-a13-mmc";
-- reg = <0x01c10000 0x1000>;
-- clocks = <&ahb_gates 9>, <&mmc1_clk>;
-- clock-names = "ahb", "mod";
-- interrupts = <33>;
-- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -308,6 +299,7 @@
- clock-names = "ahb", "mod";
- interrupts = <34>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -367,7 +359,7 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
---
-1.8.5.5
-
+++ /dev/null
-From e48e7ba7f97e883a24036df04cb474cf7cd22574 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 17:16:08 +0100
-Subject: [PATCH] ARM: sun7i: dt: Fixup mmc bindings
-
-1) Now that we're no longer overriding the caps set by mmc_of_parse we need
-to set cd-inverted for our card detection to work.
-
-2) Now that we no longer claim UHS modes support we will never use any DDR
-modes, so drive-strength 2 is enough for the mmc data pins.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 3bc6ac5..f4ecd79 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -399,6 +399,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 32 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -409,6 +410,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 33 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -419,6 +421,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 34 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -429,6 +432,7 @@
- clock-names = "ahb", "mod";
- interrupts = <0 35 4>;
- bus-width = <4>;
-+ cd-inverted;
- status = "disabled";
- };
-
-@@ -554,7 +558,7 @@
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-
-@@ -568,7 +572,7 @@
- mmc3_pins_a: mmc3@0 {
- allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
- allwinner,function = "mmc3";
-- allwinner,drive = <3>;
-+ allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
- };
---
-1.8.5.5
-
+++ /dev/null
-From 14cf22b1db1b6e6b7333e8a7245055966f5497e3 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:44:49 +0100
-Subject: [PATCH] input: Add new sun4i-lradc-keys driver
-
-Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
-specifically designed to have various (tablet) keys (ie home, back, search,
-etc). attached to it using a resistor network. This adds a driver for this.
-
-There are 2 channels, currently this driver only supports chan0 since there
-are no boards known to use chan1. The devicetree properties are already
-prefixed with chan0 as preparation for chan1 support in the future.
-
-This has been tested on an olimex a10s-olinuxino-micro, a13-olinuxino, and
-a20-olinuxino-micro.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/input/sun4i-lradc-keys.txt | 22 ++
- drivers/input/keyboard/Kconfig | 10 +
- drivers/input/keyboard/Makefile | 1 +
- drivers/input/keyboard/sun4i-lradc-keys.c | 243 +++++++++++++++++++++
- 4 files changed, 276 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
- create mode 100644 drivers/input/keyboard/sun4i-lradc-keys.c
-
-diff --git a/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-new file mode 100644
-index 0000000..7801264
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/sun4i-lradc-keys.txt
-@@ -0,0 +1,22 @@
-+Allwinner sun4i low res adc attached tablet keys
-+------------------------------------------------
-+
-+Required properties:
-+ - compatible: "allwinner,sun4i-lradc-keys"
-+ - reg: mmio address range of the chip
-+ - interrupts: interrupt to which the chip is connected
-+ - allwinner,chan0-step: step in mV between keys must be 150 or 200
-+ - linux,chan0-keycodes: array of dt-bindings/input/input.h KEY_ codes
-+
-+Example:
-+
-+#include <dt-bindings/input/input.h>
-+
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ };
-diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
-index a673c9f..d8a51cd 100644
---- a/drivers/input/keyboard/Kconfig
-+++ b/drivers/input/keyboard/Kconfig
-@@ -544,6 +544,16 @@ config KEYBOARD_STMPE
- To compile this driver as a module, choose M here: the module will be
- called stmpe-keypad.
-
-+config KEYBOARD_SUN4I_LRADC
-+ tristate "Allwinner sun4i low res adc attached tablet keys support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the Allwinner low res adc attached tablet
-+ keys found on Allwinner sunxi SoCs.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called sun4i-lradc-keys.
-+
- config KEYBOARD_DAVINCI
- tristate "TI DaVinci Key Scan"
- depends on ARCH_DAVINCI_DM365
-diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
-index a699b61..f3265bd 100644
---- a/drivers/input/keyboard/Makefile
-+++ b/drivers/input/keyboard/Makefile
-@@ -50,6 +50,7 @@ obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o
- obj-$(CONFIG_KEYBOARD_SPEAR) += spear-keyboard.o
- obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o
- obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o
-+obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
- obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
- obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
- obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
-diff --git a/drivers/input/keyboard/sun4i-lradc-keys.c b/drivers/input/keyboard/sun4i-lradc-keys.c
-new file mode 100644
-index 0000000..5c55e17
---- /dev/null
-+++ b/drivers/input/keyboard/sun4i-lradc-keys.c
-@@ -0,0 +1,243 @@
-+/*
-+ * Allwinner sun4i low res adc attached tablet keys driver
-+ *
-+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * Allwinnner sunxi SoCs have a lradc which is specifically designed to have
-+ * various (tablet) keys (ie home, back, search, etc). attached to it using
-+ * a resistor network. This driver is for the keys on such boards.
-+ *
-+ * There are 2 channels, currently this driver only supports chan0 since there
-+ * are no boards known to use chan1. The devicetree properties are already
-+ * prefixed with chan0 as preparation for chan1 support in the future.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#define LRADC_CTRL 0x00
-+#define LRADC_INTC 0x04
-+#define LRADC_INTS 0x08
-+#define LRADC_DATA0 0x0c
-+#define LRADC_DATA1 0x10
-+
-+/* LRADC_CTRL bits */
-+#define FIRST_CONVERT_DLY(x) ((x) << 24) /* 8 bits */
-+#define CHAN_SELECT(x) ((x) << 22) /* 2 bits */
-+#define CONTINUE_TIME_SEL(x) ((x) << 16) /* 4 bits */
-+#define KEY_MODE_SEL(x) ((x) << 12) /* 2 bits */
-+#define LEVELA_B_CNT(x) ((x) << 8) /* 4 bits */
-+#define HOLD_EN(x) ((x) << 6)
-+#define LEVELB_VOL(x) ((x) << 4) /* 2 bits */
-+#define SAMPLE_RATE(x) ((x) << 2) /* 2 bits */
-+#define ENABLE(x) ((x) << 0)
-+
-+/* LRADC_INTC and LRADC_INTS bits */
-+#define CHAN1_KEYUP_IRQ BIT(12)
-+#define CHAN1_ALRDY_HOLD_IRQ BIT(11)
-+#define CHAN1_HOLD_IRQ BIT(10)
-+#define CHAN1_KEYDOWN_IRQ BIT(9)
-+#define CHAN1_DATA_IRQ BIT(8)
-+#define CHAN0_KEYUP_IRQ BIT(4)
-+#define CHAN0_ALRDY_HOLD_IRQ BIT(3)
-+#define CHAN0_HOLD_IRQ BIT(2)
-+#define CHAN0_KEYDOWN_IRQ BIT(1)
-+#define CHAN0_DATA_IRQ BIT(0)
-+
-+#define MAX_KEYS 13
-+
-+/* Lookup table to map the adc val to a keycode index for 150 mv step size */
-+static const u8 adc_val_to_key_index_step150[64] = {
-+ 0, 0, 0,
-+ 1, 1, 1, 1, 1,
-+ 2, 2, 2, 2, 2,
-+ 3, 3, 3, 3,
-+ 4, 4, 4, 4, 4,
-+ 5, 5, 5, 5, 5,
-+ 6, 6, 6, 6, 6,
-+ 7, 7, 7, 7,
-+ 8, 8, 8, 8, 8,
-+ 9, 9, 9, 9, 9,
-+ 10, 10, 10, 10,
-+ 11, 11, 11, 11,
-+ 12, 12, 12, 12, 12, 12, 12, 12, 12, 12
-+};
-+
-+/* Lookup table to map the adc val to a keycode index for 200 mv step size */
-+static const u8 adc_val_to_key_index_step200[64] = {
-+ 0, 0, 0, 0, 0, 0, 0, 0,
-+ 1, 1, 1, 1, 1, 1, 1,
-+ 2, 2, 2, 2, 2, 2, 2,
-+ 3, 3, 3, 3, 3, 3,
-+ 4, 4, 4, 4, 4, 4,
-+ 5, 5, 5, 5, 5, 5,
-+ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
-+ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
-+};
-+
-+struct sun4i_lradc_data {
-+ struct device *dev;
-+ struct input_dev *input;
-+ void __iomem *base;
-+ u32 chan0_step;
-+ u32 chan0_keycode;
-+ u32 chan0_keycodes[MAX_KEYS];
-+};
-+
-+static irqreturn_t sun4i_lradc_irq(int irq, void *dev_id)
-+{
-+ struct sun4i_lradc_data *lradc = dev_id;
-+ u32 ints, val;
-+
-+ ints = readl(lradc->base + LRADC_INTS);
-+
-+ /*
-+ * lradc supports only one keypress at a time, release does not give
-+ * any info as to which key was released, so we cache the keycode.
-+ */
-+ if ((ints & CHAN0_KEYDOWN_IRQ) && lradc->chan0_keycode == 0) {
-+ val = readl(lradc->base + LRADC_DATA0);
-+ if (lradc->chan0_step == 150)
-+ val = adc_val_to_key_index_step150[val];
-+ else
-+ val = adc_val_to_key_index_step200[val];
-+
-+ lradc->chan0_keycode = lradc->chan0_keycodes[val];
-+ input_report_key(lradc->input, lradc->chan0_keycode, 1);
-+ }
-+
-+ if (ints & CHAN0_KEYUP_IRQ) {
-+ input_report_key(lradc->input, lradc->chan0_keycode, 0);
-+ lradc->chan0_keycode = 0;
-+ }
-+
-+ input_sync(lradc->input);
-+
-+ writel(ints, lradc->base + LRADC_INTS);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int sun4i_lradc_open(struct input_dev *dev)
-+{
-+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+
-+ /*
-+ * Set sample time to 16 ms / 62.5 Hz. Wait 2 * 16 ms for key to
-+ * stabilize on press, wait (1 + 1) * 16 ms for key release
-+ */
-+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+ SAMPLE_RATE(2) | ENABLE(1), lradc->base + LRADC_CTRL);
-+
-+ writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC);
-+
-+ return 0;
-+}
-+
-+static void sun4i_lradc_close(struct input_dev *dev)
-+{
-+ struct sun4i_lradc_data *lradc = input_get_drvdata(dev);
-+
-+ /* Disable lradc, leave other settings unchanged */
-+ writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
-+ SAMPLE_RATE(2), lradc->base + LRADC_CTRL);
-+ writel(0, lradc->base + LRADC_INTC);
-+}
-+
-+static int sun4i_lradc_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_lradc_data *lradc;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ int i, ret;
-+
-+ lradc = devm_kzalloc(dev, sizeof(struct sun4i_lradc_data), GFP_KERNEL);
-+ if (!lradc)
-+ return -ENOMEM;
-+
-+ ret = of_property_read_u32(np, "allwinner,chan0-step",
-+ &lradc->chan0_step);
-+ if (ret || (lradc->chan0_step != 150 && lradc->chan0_step != 200)) {
-+ dev_err(dev, "Invalid allwinner,chan0-step dt-property\n");
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < MAX_KEYS; i++)
-+ of_property_read_u32_index(np, "linux,chan0-keycodes",
-+ i, &lradc->chan0_keycodes[i]);
-+
-+ lradc->dev = dev;
-+ lradc->input = devm_input_allocate_device(dev);
-+ if (!lradc->input)
-+ return -ENOMEM;
-+
-+ lradc->input->name = pdev->name;
-+ lradc->input->phys = "sun4i_lradc/input0";
-+ lradc->input->open = sun4i_lradc_open;
-+ lradc->input->close = sun4i_lradc_close;
-+ lradc->input->id.bustype = BUS_HOST;
-+ lradc->input->id.vendor = 0x0001;
-+ lradc->input->id.product = 0x0001;
-+ lradc->input->id.version = 0x0100;
-+ lradc->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY);
-+ for (i = 0; i < MAX_KEYS; i++)
-+ set_bit(lradc->chan0_keycodes[i], lradc->input->keybit);
-+ input_set_drvdata(lradc->input, lradc);
-+
-+ lradc->base = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(lradc->base))
-+ return PTR_ERR(lradc->base);
-+
-+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), sun4i_lradc_irq,
-+ 0, "sun4i-lradc-keys", lradc);
-+ if (ret)
-+ return ret;
-+
-+ ret = input_register_device(lradc->input);
-+ if (ret)
-+ return ret;
-+
-+ platform_set_drvdata(pdev, lradc);
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_lradc_of_match[] = {
-+ { .compatible = "allwinner,sun4i-lradc-keys", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match);
-+
-+static struct platform_driver sun4i_lradc_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "sun4i-lradc-keys",
-+ .of_match_table = of_match_ptr(sun4i_lradc_of_match),
-+ },
-+ .probe = sun4i_lradc_probe,
-+};
-+
-+module_platform_driver(sun4i_lradc_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i low res adc attached tablet keys driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 0b35a283be3dcd9495bb7c0e13ef2cd58a5d2afc Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 20:26:21 +0100
-Subject: [PATCH] ARM: dts: sun7i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 9 +++++++++
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 2 files changed, 16 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index d4e2355..aef289f 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A20-Olinuxino Micro";
-@@ -57,6 +58,14 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_SEARCH KEY_HOME
-+ KEY_ESC KEY_ENTER>;
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index fa2ef07..b58ce25 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -608,6 +608,13 @@
- interrupts = <0 24 1>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <0 31 4>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun7i-a20-sid";
- reg = <0x01c23800 0x200>;
---
-1.8.5.5
-
+++ /dev/null
-From 7d6d16c0c9b96695cd0f5e5845ac192209f0811d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:51:36 +0100
-Subject: [PATCH] ARM: dts: sun4i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index ba05e6e..1a9ab7e 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -494,6 +494,13 @@
- interrupts = <24>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---
-1.8.5.5
-
+++ /dev/null
-From 23f834fe6efd9f97e9b336cc53d902e6a0158cc5 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Wed, 1 Jan 2014 19:50:33 +0100
-Subject: [PATCH] ARM: dts: sun5i: Add lradc node
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 8 ++++++++
- arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 8 ++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
- 4 files changed, 30 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-index 5c7b454..2cbca7b 100644
---- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a10s.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A10s-Olinuxino Micro";
-@@ -73,6 +74,13 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 15dfa9a..95cb245 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -430,6 +430,13 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index a7280f5..ba32a41 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a13.dtsi"
-+#include <dt-bindings/input/input.h>
-
- / {
- model = "Olimex A13-Olinuxino";
-@@ -43,6 +44,13 @@
- };
- };
-
-+ lradc: lradc@01c22800 {
-+ allwinner,chan0-step = <200>;
-+ linux,chan0-keycodes = <KEY_VOLUMEUP KEY_VOLUMEDOWN
-+ KEY_MENU KEY_ENTER KEY_HOME>;
-+ status = "okay";
-+ };
-+
- uart1: serial@01c28400 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 14a99d0..bae0f5f 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -376,6 +376,13 @@
- reg = <0x01c20c90 0x10>;
- };
-
-+ lradc: lradc@01c22800 {
-+ compatible = "allwinner,sun4i-lradc-keys";
-+ reg = <0x01c22800 0x100>;
-+ interrupts = <31>;
-+ status = "disabled";
-+ };
-+
- sid: eeprom@01c23800 {
- compatible = "allwinner,sun4i-sid";
- reg = <0x01c23800 0x10>;
---
-1.8.5.5
-
+++ /dev/null
-From 3c9740a117d40a74412775b5d3fe2b88a7635a0e Mon Sep 17 00:00:00 2001
-From: Peter Chen <peter.chen@freescale.com>
-Date: Tue, 5 Nov 2013 10:46:02 +0800
-Subject: [PATCH] usb: hcd: move controller wakeup setting initialization to
- individual driver
-
-Individual controller driver has different requirement for wakeup
-setting, so move it from core to itself. In order to align with
-current etting the default wakeup setting is enabled (except for
-chipidea host).
-
-Pass compile test with below commands:
- make O=outout/all allmodconfig
- make -j$CPU_NUM O=outout/all drivers/usb
-
-Signed-off-by: Peter Chen <peter.chen@freescale.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/dwc2/hcd.c | 2 ++
- drivers/staging/octeon-usb/octeon-hcd.c | 1 +
- drivers/staging/ozwpan/ozhcd.c | 2 ++
- drivers/usb/c67x00/c67x00-hcd.c | 2 ++
- drivers/usb/core/hcd-pci.c | 1 +
- drivers/usb/core/hcd.c | 6 ------
- drivers/usb/host/ehci-atmel.c | 1 +
- drivers/usb/host/ehci-exynos.c | 1 +
- drivers/usb/host/ehci-fsl.c | 1 +
- drivers/usb/host/ehci-grlib.c | 1 +
- drivers/usb/host/ehci-mv.c | 1 +
- drivers/usb/host/ehci-mxc.c | 1 +
- drivers/usb/host/ehci-octeon.c | 1 +
- drivers/usb/host/ehci-omap.c | 1 +
- drivers/usb/host/ehci-orion.c | 1 +
- drivers/usb/host/ehci-platform.c | 1 +
- drivers/usb/host/ehci-pmcmsp.c | 4 +++-
- drivers/usb/host/ehci-ppc-of.c | 1 +
- drivers/usb/host/ehci-ps3.c | 1 +
- drivers/usb/host/ehci-sead3.c | 1 +
- drivers/usb/host/ehci-sh.c | 1 +
- drivers/usb/host/ehci-spear.c | 1 +
- drivers/usb/host/ehci-tegra.c | 1 +
- drivers/usb/host/ehci-tilegx.c | 1 +
- drivers/usb/host/ehci-w90x900.c | 1 +
- drivers/usb/host/ehci-xilinx-of.c | 4 +++-
- drivers/usb/host/fhci-hcd.c | 2 ++
- drivers/usb/host/fotg210-hcd.c | 1 +
- drivers/usb/host/fusbh200-hcd.c | 1 +
- drivers/usb/host/hwa-hc.c | 1 +
- drivers/usb/host/imx21-hcd.c | 1 +
- drivers/usb/host/isp116x-hcd.c | 2 ++
- drivers/usb/host/isp1362-hcd.c | 2 ++
- drivers/usb/host/isp1760-hcd.c | 1 +
- drivers/usb/host/ohci-at91.c | 4 +++-
- drivers/usb/host/ohci-da8xx.c | 2 ++
- drivers/usb/host/ohci-exynos.c | 1 +
- drivers/usb/host/ohci-jz4740.c | 1 +
- drivers/usb/host/ohci-nxp.c | 4 +++-
- drivers/usb/host/ohci-octeon.c | 2 ++
- drivers/usb/host/ohci-omap.c | 1 +
- drivers/usb/host/ohci-omap3.c | 1 +
- drivers/usb/host/ohci-platform.c | 2 ++
- drivers/usb/host/ohci-ppc-of.c | 4 +++-
- drivers/usb/host/ohci-ps3.c | 1 +
- drivers/usb/host/ohci-pxa27x.c | 4 +++-
- drivers/usb/host/ohci-s3c2410.c | 1 +
- drivers/usb/host/ohci-sa1111.c | 4 +++-
- drivers/usb/host/ohci-sm501.c | 1 +
- drivers/usb/host/ohci-spear.c | 4 +++-
- drivers/usb/host/ohci-tilegx.c | 1 +
- drivers/usb/host/ohci-tmio.c | 1 +
- drivers/usb/host/oxu210hp-hcd.c | 1 +
- drivers/usb/host/r8a66597-hcd.c | 1 +
- drivers/usb/host/sl811-hcd.c | 2 ++
- drivers/usb/host/u132-hcd.c | 1 +
- drivers/usb/host/uhci-grlib.c | 1 +
- drivers/usb/host/uhci-platform.c | 1 +
- drivers/usb/host/whci/hcd.c | 1 +
- drivers/usb/host/xhci-plat.c | 1 +
- drivers/usb/musb/musb_host.c | 1 +
- drivers/usb/phy/phy-msm-usb.c | 1 +
- drivers/usb/phy/phy-mv-usb.c | 6 ++++--
- drivers/usb/renesas_usbhs/mod_host.c | 1 +
- 64 files changed, 92 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/staging/dwc2/hcd.c b/drivers/staging/dwc2/hcd.c
-index 3cfd2d5..078cd91 100644
---- a/drivers/staging/dwc2/hcd.c
-+++ b/drivers/staging/dwc2/hcd.c
-@@ -2921,6 +2921,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
- if (retval < 0)
- goto error3;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- dwc2_hcd_dump_state(hsotg);
-
- dwc2_enable_global_interrupts(hsotg);
-diff --git a/drivers/staging/octeon-usb/octeon-hcd.c b/drivers/staging/octeon-usb/octeon-hcd.c
-index d118952..47e0a91 100644
---- a/drivers/staging/octeon-usb/octeon-hcd.c
-+++ b/drivers/staging/octeon-usb/octeon-hcd.c
-@@ -3498,6 +3498,7 @@ static int octeon_usb_driver_probe(struct device *dev)
- kfree(hcd);
- return -1;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- dev_dbg(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
-
-diff --git a/drivers/staging/ozwpan/ozhcd.c b/drivers/staging/ozwpan/ozhcd.c
-index d9c43c3..efaf26f 100644
---- a/drivers/staging/ozwpan/ozhcd.c
-+++ b/drivers/staging/ozwpan/ozhcd.c
-@@ -2270,6 +2270,8 @@ static int oz_plat_probe(struct platform_device *dev)
- usb_put_hcd(hcd);
- return -1;
- }
-+ device_wakeup_enable(hcd->self.controller);
-+
- spin_lock_bh(&g_hcdlock);
- g_ozhcd = ozhcd;
- spin_unlock_bh(&g_hcdlock);
-diff --git a/drivers/usb/c67x00/c67x00-hcd.c b/drivers/usb/c67x00/c67x00-hcd.c
-index 75e47b8..20ec4ee 100644
---- a/drivers/usb/c67x00/c67x00-hcd.c
-+++ b/drivers/usb/c67x00/c67x00-hcd.c
-@@ -384,6 +384,8 @@ int c67x00_hcd_probe(struct c67x00_sie *sie)
- goto err2;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- spin_lock_irqsave(&sie->lock, flags);
- sie->private_data = c67x00;
- sie->irq = c67x00_hcd_irq;
-diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
-index dfe9d0f..d59d993 100644
---- a/drivers/usb/core/hcd-pci.c
-+++ b/drivers/usb/core/hcd-pci.c
-@@ -282,6 +282,7 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
-
- if (retval != 0)
- goto unmap_registers;
-+ device_wakeup_enable(hcd->self.controller);
-
- if (pci_dev_run_wake(dev))
- pm_runtime_put_noidle(&dev->dev);
-diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
-index d3a9bcd..6297c9e 100644
---- a/drivers/usb/core/hcd.c
-+++ b/drivers/usb/core/hcd.c
-@@ -2712,12 +2712,6 @@ int usb_add_hcd(struct usb_hcd *hcd,
- if (hcd->uses_new_polling && HCD_POLL_RH(hcd))
- usb_hcd_poll_rh_status(hcd);
-
-- /*
-- * Host controllers don't generate their own wakeup requests;
-- * they only forward requests from the root hub. Therefore
-- * controllers should always be enabled for remote wakeup.
-- */
-- device_wakeup_enable(hcd->self.controller);
- return retval;
-
- error_create_attr_group:
-diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
-index 284f841..ec9f7b7 100644
---- a/drivers/usb/host/ehci-atmel.c
-+++ b/drivers/usb/host/ehci-atmel.c
-@@ -153,6 +153,7 @@ static int ehci_atmel_drv_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval)
- goto fail_add_hcd;
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
-index e97c198..d1d8c47 100644
---- a/drivers/usb/host/ehci-exynos.c
-+++ b/drivers/usb/host/ehci-exynos.c
-@@ -166,6 +166,7 @@ static int exynos_ehci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- platform_set_drvdata(pdev, hcd);
-
-diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
-index 87a7426..854a68f 100644
---- a/drivers/usb/host/ehci-fsl.c
-+++ b/drivers/usb/host/ehci-fsl.c
-@@ -138,6 +138,7 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval != 0)
- goto err4;
-+ device_wakeup_enable(hcd->self.controller);
-
- #ifdef CONFIG_USB_OTG
- if (pdata->operating_mode == FSL_USB2_DR_OTG) {
-diff --git a/drivers/usb/host/ehci-grlib.c b/drivers/usb/host/ehci-grlib.c
-index b52a66c..054792c 100644
---- a/drivers/usb/host/ehci-grlib.c
-+++ b/drivers/usb/host/ehci-grlib.c
-@@ -140,6 +140,7 @@ static int ehci_hcd_grlib_probe(struct platform_device *op)
- if (rv)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ehci-mv.c b/drivers/usb/host/ehci-mv.c
-index 6e8afca..bd61612 100644
---- a/drivers/usb/host/ehci-mv.c
-+++ b/drivers/usb/host/ehci-mv.c
-@@ -257,6 +257,7 @@ static int mv_ehci_probe(struct platform_device *pdev)
- "failed to add hcd with err %d\n", retval);
- goto err_set_vbus;
- }
-+ device_wakeup_enable(hcd->self.controller);
- }
-
- if (pdata->private_init)
-diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
-index 0528dc4..dbe5e4e 100644
---- a/drivers/usb/host/ehci-mxc.c
-+++ b/drivers/usb/host/ehci-mxc.c
-@@ -155,6 +155,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
- if (ret)
- goto err_add;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_add:
-diff --git a/drivers/usb/host/ehci-octeon.c b/drivers/usb/host/ehci-octeon.c
-index 4c528b2..c4ad7ed 100644
---- a/drivers/usb/host/ehci-octeon.c
-+++ b/drivers/usb/host/ehci-octeon.c
-@@ -158,6 +158,7 @@ static int ehci_octeon_drv_probe(struct platform_device *pdev)
- dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
- goto err3;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- platform_set_drvdata(pdev, hcd);
-
-diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
-index 6fa82d6..a24720b 100644
---- a/drivers/usb/host/ehci-omap.c
-+++ b/drivers/usb/host/ehci-omap.c
-@@ -215,6 +215,7 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", ret);
- goto err_pm_runtime;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- /*
- * Bring PHYs out of reset for non PHY modes.
-diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
-index 2ba7673..aa8b92b 100644
---- a/drivers/usb/host/ehci-orion.c
-+++ b/drivers/usb/host/ehci-orion.c
-@@ -252,6 +252,7 @@ static int ehci_orion_drv_probe(struct platform_device *pdev)
- if (err)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err4:
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 7f30b71..01536cf 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -132,6 +132,7 @@ static int ehci_platform_probe(struct platform_device *dev)
- if (err)
- goto err_put_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
- platform_set_drvdata(dev, hcd);
-
- return err;
-diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c
-index 893b707f..af3974a 100644
---- a/drivers/usb/host/ehci-pmcmsp.c
-+++ b/drivers/usb/host/ehci-pmcmsp.c
-@@ -210,8 +210,10 @@ int usb_hcd_msp_probe(const struct hc_driver *driver,
-
-
- retval = usb_add_hcd(hcd, res->start, IRQF_SHARED);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- usb_remove_hcd(hcd);
- err3:
-diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
-index 875d2fc..b0965eb 100644
---- a/drivers/usb/host/ehci-ppc-of.c
-+++ b/drivers/usb/host/ehci-ppc-of.c
-@@ -169,6 +169,7 @@ static int ehci_hcd_ppc_of_probe(struct platform_device *op)
- if (rv)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
-index 8188542..7934ff9 100644
---- a/drivers/usb/host/ehci-ps3.c
-+++ b/drivers/usb/host/ehci-ps3.c
-@@ -189,6 +189,7 @@ static int ps3_ehci_probe(struct ps3_system_bus_device *dev)
- goto fail_add_hcd;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
- return result;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ehci-sead3.c b/drivers/usb/host/ehci-sead3.c
-index 8a73449..cf12676 100644
---- a/drivers/usb/host/ehci-sead3.c
-+++ b/drivers/usb/host/ehci-sead3.c
-@@ -126,6 +126,7 @@ static int ehci_hcd_sead3_drv_probe(struct platform_device *pdev)
- IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c
-index dc899eb..9b9b9f5 100644
---- a/drivers/usb/host/ehci-sh.c
-+++ b/drivers/usb/host/ehci-sh.c
-@@ -151,6 +151,7 @@ static int ehci_hcd_sh_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- priv->hcd = hcd;
- platform_set_drvdata(pdev, priv);
-diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
-index ee6f9ff..8bd915b 100644
---- a/drivers/usb/host/ehci-spear.c
-+++ b/drivers/usb/host/ehci-spear.c
-@@ -130,6 +130,7 @@ static int spear_ehci_hcd_drv_probe(struct platform_device *pdev)
- if (retval)
- goto err_stop_ehci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-
- err_stop_ehci:
-diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
-index b9fd039..a8f4471 100644
---- a/drivers/usb/host/ehci-tegra.c
-+++ b/drivers/usb/host/ehci-tegra.c
-@@ -455,6 +455,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto cleanup_otg_set_host;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return err;
-
-diff --git a/drivers/usb/host/ehci-tilegx.c b/drivers/usb/host/ehci-tilegx.c
-index 67026ff..f3713d3 100644
---- a/drivers/usb/host/ehci-tilegx.c
-+++ b/drivers/usb/host/ehci-tilegx.c
-@@ -170,6 +170,7 @@ static int ehci_hcd_tilegx_drv_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ehci-w90x900.c b/drivers/usb/host/ehci-w90x900.c
-index cdad843..12c1a56 100644
---- a/drivers/usb/host/ehci-w90x900.c
-+++ b/drivers/usb/host/ehci-w90x900.c
-@@ -94,6 +94,7 @@ static int usb_w90x900_probe(const struct hc_driver *driver,
- if (retval != 0)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
- err4:
- iounmap(hcd->regs);
-diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c
-index 95979f9..3cd2efa 100644
---- a/drivers/usb/host/ehci-xilinx-of.c
-+++ b/drivers/usb/host/ehci-xilinx-of.c
-@@ -191,8 +191,10 @@ static int ehci_hcd_xilinx_of_probe(struct platform_device *op)
- ehci->caps = hcd->regs + 0x100;
-
- rv = usb_add_hcd(hcd, irq, 0);
-- if (rv == 0)
-+ if (rv == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- err_irq:
- usb_put_hcd(hcd);
-diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c
-index 0551c0a..1cf68ea 100644
---- a/drivers/usb/host/fhci-hcd.c
-+++ b/drivers/usb/host/fhci-hcd.c
-@@ -754,6 +754,8 @@ static int of_fhci_probe(struct platform_device *ofdev)
- if (ret < 0)
- goto err_add_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- fhci_dfs_create(fhci);
-
- return 0;
-diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c
-index 97d6939..98a89d1 100644
---- a/drivers/usb/host/fotg210-hcd.c
-+++ b/drivers/usb/host/fotg210-hcd.c
-@@ -5889,6 +5889,7 @@ static int fotg210_hcd_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", retval);
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/fusbh200-hcd.c b/drivers/usb/host/fusbh200-hcd.c
-index 9ea85b6..ba94990 100644
---- a/drivers/usb/host/fusbh200-hcd.c
-+++ b/drivers/usb/host/fusbh200-hcd.c
-@@ -5798,6 +5798,7 @@ static int fusbh200_hcd_probe(struct platform_device *pdev)
- dev_err(dev, "failed to add hcd with err %d\n", retval);
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return retval;
-
-diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c
-index a4ec9e6..7fd3f9b 100644
---- a/drivers/usb/host/hwa-hc.c
-+++ b/drivers/usb/host/hwa-hc.c
-@@ -791,6 +791,7 @@ static int hwahc_probe(struct usb_interface *usb_iface,
- dev_err(dev, "Cannot add HCD: %d\n", result);
- goto error_add_hcd;
- }
-+ device_wakeup_enable(usb_hcd->self.controller);
- result = wusbhc_b_create(&hwahc->wusbhc);
- if (result < 0) {
- dev_err(dev, "Cannot setup phase B of WUSBHC: %d\n", result);
-diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
-index 0122624..207bad9 100644
---- a/drivers/usb/host/imx21-hcd.c
-+++ b/drivers/usb/host/imx21-hcd.c
-@@ -1910,6 +1910,7 @@ static int imx21_probe(struct platform_device *pdev)
- dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
- goto failed_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
-index 7722ec6..2740f65 100644
---- a/drivers/usb/host/isp116x-hcd.c
-+++ b/drivers/usb/host/isp116x-hcd.c
-@@ -1645,6 +1645,8 @@ static int isp116x_probe(struct platform_device *pdev)
- if (ret)
- goto err6;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- ret = create_debug_file(isp116x);
- if (ret) {
- ERR("Couldn't create debugfs entry\n");
-diff --git a/drivers/usb/host/isp1362-hcd.c b/drivers/usb/host/isp1362-hcd.c
-index cd94b10..34645ae 100644
---- a/drivers/usb/host/isp1362-hcd.c
-+++ b/drivers/usb/host/isp1362-hcd.c
-@@ -2746,6 +2746,8 @@ static int isp1362_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, irq_flags | IRQF_SHARED);
- if (retval != 0)
- goto err6;
-+ device_wakeup_enable(hcd->self.controller);
-+
- pr_info("%s, irq %d\n", hcd->product_desc, irq);
-
- create_debug_file(isp1362_hcd);
-diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
-index 2facee5..51a0ae9 100644
---- a/drivers/usb/host/isp1760-hcd.c
-+++ b/drivers/usb/host/isp1760-hcd.c
-@@ -2250,6 +2250,7 @@ struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
- ret = usb_add_hcd(hcd, irq, irqflags);
- if (ret)
- goto err_unmap;
-+ device_wakeup_enable(hcd->self.controller);
-
- return hcd;
-
-diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
-index cc9462f..29d2093 100644
-diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
-index 71dbd85..f0fe0d2 100644
---- a/drivers/usb/host/ohci-da8xx.c
-+++ b/drivers/usb/host/ohci-da8xx.c
-@@ -348,6 +348,8 @@ static int usb_hcd_da8xx_probe(const struct hc_driver *driver,
- if (error)
- goto err4;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- if (hub->ocic_notify) {
- error = hub->ocic_notify(ohci_da8xx_ocic_handler);
- if (!error)
-diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
-index 9897d70..68588d8 100644
---- a/drivers/usb/host/ohci-exynos.c
-+++ b/drivers/usb/host/ohci-exynos.c
-@@ -146,6 +146,7 @@ static int exynos_ohci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add USB HCD\n");
- goto fail_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c
-index d4ef539..efe31f3 100644
---- a/drivers/usb/host/ohci-jz4740.c
-+++ b/drivers/usb/host/ohci-jz4740.c
-@@ -217,6 +217,7 @@ static int jz4740_ohci_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd: %d\n", ret);
- goto err_disable;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
-index e99db8a..719f28e 100644
---- a/drivers/usb/host/ohci-nxp.c
-+++ b/drivers/usb/host/ohci-nxp.c
-@@ -274,8 +274,10 @@ static int ohci_hcd_nxp_probe(struct platform_device *pdev)
-
- dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
- ret = usb_add_hcd(hcd, irq, 0);
-- if (ret == 0)
-+ if (ret == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
-+ }
-
- ohci_nxp_stop_hc();
- fail_resource:
-diff --git a/drivers/usb/host/ohci-octeon.c b/drivers/usb/host/ohci-octeon.c
-index 6c16dce..49b220d 100644
---- a/drivers/usb/host/ohci-octeon.c
-+++ b/drivers/usb/host/ohci-octeon.c
-@@ -171,6 +171,8 @@ static int ohci_octeon_drv_probe(struct platform_device *pdev)
- goto err3;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- platform_set_drvdata(pdev, hcd);
-
- return 0;
-diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
-index f253214..a44a4fe 100644
---- a/drivers/usb/host/ohci-omap.c
-+++ b/drivers/usb/host/ohci-omap.c
-@@ -367,6 +367,7 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
- if (retval)
- goto err3;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
- err3:
- iounmap(hcd->regs);
-diff --git a/drivers/usb/host/ohci-omap3.c b/drivers/usb/host/ohci-omap3.c
-index 2145741..ec15aeb 100644
---- a/drivers/usb/host/ohci-omap3.c
-+++ b/drivers/usb/host/ohci-omap3.c
-@@ -130,6 +130,7 @@ static int ohci_hcd_omap3_probe(struct platform_device *pdev)
- dev_dbg(dev, "failed to add hcd with err %d\n", ret);
- goto err_add_hcd;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index f351ff5..68f674c 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -108,6 +108,8 @@ static int ohci_platform_probe(struct platform_device *dev)
- if (err)
- goto err_put_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- platform_set_drvdata(dev, hcd);
-
- return err;
-diff --git a/drivers/usb/host/ohci-ppc-of.c b/drivers/usb/host/ohci-ppc-of.c
-index 81f3eba..83e33d4 100644
---- a/drivers/usb/host/ohci-ppc-of.c
-+++ b/drivers/usb/host/ohci-ppc-of.c
-@@ -147,8 +147,10 @@ static int ohci_hcd_ppc_of_probe(struct platform_device *op)
- ohci_hcd_init(ohci);
-
- rv = usb_add_hcd(hcd, irq, 0);
-- if (rv == 0)
-+ if (rv == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-+ }
-
- /* by now, 440epx is known to show usb_23 erratum */
- np = of_find_compatible_node(NULL, NULL, "ibm,usb-ehci-440epx");
-diff --git a/drivers/usb/host/ohci-ps3.c b/drivers/usb/host/ohci-ps3.c
-index 7d35cd9..71d8bc4 100644
---- a/drivers/usb/host/ohci-ps3.c
-+++ b/drivers/usb/host/ohci-ps3.c
-@@ -173,6 +173,7 @@ static int ps3_ohci_probe(struct ps3_system_bus_device *dev)
- goto fail_add_hcd;
- }
-
-+ device_wakeup_enable(hcd->self.controller);
- return result;
-
- fail_add_hcd:
-diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
-index e89ac4d..5343ecf 100644
---- a/drivers/usb/host/ohci-pxa27x.c
-+++ b/drivers/usb/host/ohci-pxa27x.c
-@@ -442,8 +442,10 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
- ohci->num_ports = 3;
-
- retval = usb_add_hcd(hcd, irq, 0);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-+ }
-
- pxa27x_stop_hc(pxa_ohci, &pdev->dev);
- err3:
-diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
-index 83cd1dc..ff7c8f1 100644
---- a/drivers/usb/host/ohci-s3c2410.c
-+++ b/drivers/usb/host/ohci-s3c2410.c
-@@ -395,6 +395,7 @@ static int usb_hcd_s3c2410_probe(const struct hc_driver *driver,
- if (retval != 0)
- goto err_ioremap;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_ioremap:
-diff --git a/drivers/usb/host/ohci-sa1111.c b/drivers/usb/host/ohci-sa1111.c
-index aa9e127..2ac266d 100644
---- a/drivers/usb/host/ohci-sa1111.c
-+++ b/drivers/usb/host/ohci-sa1111.c
-@@ -211,8 +211,10 @@ static int ohci_hcd_sa1111_probe(struct sa1111_dev *dev)
- goto err2;
-
- ret = usb_add_hcd(hcd, dev->irq[1], 0);
-- if (ret == 0)
-+ if (ret == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
-+ }
-
- sa1111_stop_hc(dev);
- err2:
-diff --git a/drivers/usb/host/ohci-sm501.c b/drivers/usb/host/ohci-sm501.c
-index 2a5de5f..4e81c80 100644
---- a/drivers/usb/host/ohci-sm501.c
-+++ b/drivers/usb/host/ohci-sm501.c
-@@ -168,6 +168,7 @@ static int ohci_hcd_sm501_drv_probe(struct platform_device *pdev)
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval)
- goto err5;
-+ device_wakeup_enable(hcd->self.controller);
-
- /* enable power and unmask interrupts */
-
-diff --git a/drivers/usb/host/ohci-spear.c b/drivers/usb/host/ohci-spear.c
-index e418c19..4cb98ab 100644
---- a/drivers/usb/host/ohci-spear.c
-+++ b/drivers/usb/host/ohci-spear.c
-@@ -103,8 +103,10 @@ static int spear_ohci_hcd_drv_probe(struct platform_device *pdev)
- ohci = hcd_to_ohci(hcd);
-
- retval = usb_add_hcd(hcd, platform_get_irq(pdev, 0), 0);
-- if (retval == 0)
-+ if (retval == 0) {
-+ device_wakeup_enable(hcd->self.controller);
- return retval;
-+ }
-
- clk_disable_unprepare(sohci_p->clk);
- err_put_hcd:
-diff --git a/drivers/usb/host/ohci-tilegx.c b/drivers/usb/host/ohci-tilegx.c
-index 22540ab..0b183e0 100644
---- a/drivers/usb/host/ohci-tilegx.c
-+++ b/drivers/usb/host/ohci-tilegx.c
-@@ -159,6 +159,7 @@ static int ohci_hcd_tilegx_drv_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, pdata->irq, IRQF_SHARED);
- if (ret == 0) {
- platform_set_drvdata(pdev, hcd);
-+ device_wakeup_enable(hcd->self.controller);
- return ret;
- }
-
-diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c
-index ecb09a5..9c44093 100644
---- a/drivers/usb/host/ohci-tmio.c
-+++ b/drivers/usb/host/ohci-tmio.c
-@@ -250,6 +250,7 @@ static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
- if (ret)
- goto err_add_hcd;
-
-+ device_wakeup_enable(hcd->self.controller);
- if (ret == 0)
- return ret;
-
-diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
-index 4a05148..778eeaf 100644
---- a/drivers/usb/host/oxu210hp-hcd.c
-+++ b/drivers/usb/host/oxu210hp-hcd.c
-@@ -3751,6 +3751,7 @@ static struct usb_hcd *oxu_create(struct platform_device *pdev,
- if (ret < 0)
- return ERR_PTR(ret);
-
-+ device_wakeup_enable(hcd->self.controller);
- return hcd;
- }
-
-diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
-index 3bddfcf..47b1322 100644
---- a/drivers/usb/host/r8a66597-hcd.c
-+++ b/drivers/usb/host/r8a66597-hcd.c
-@@ -2514,6 +2514,7 @@ static int r8a66597_probe(struct platform_device *pdev)
- dev_err(&pdev->dev, "Failed to add hcd\n");
- goto clean_up3;
- }
-+ device_wakeup_enable(hcd->self.controller);
-
- return 0;
-
-diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
-index 79620c3..0115e7f 100644
---- a/drivers/usb/host/sl811-hcd.c
-+++ b/drivers/usb/host/sl811-hcd.c
-@@ -1732,6 +1732,8 @@ static void remove_debug_file(struct sl811 *sl811)
- if (retval != 0)
- goto err6;
-
-+ device_wakeup_enable(hcd->self.controller);
-+
- create_debug_file(sl811);
- return retval;
-
-diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
-index 46236e9..c067175 100644
---- a/drivers/usb/host/u132-hcd.c
-+++ b/drivers/usb/host/u132-hcd.c
-@@ -3133,6 +3133,7 @@ static int u132_probe(struct platform_device *pdev)
- u132_u132_put_kref(u132);
- return retval;
- } else {
-+ device_wakeup_enable(hcd->self.controller);
- u132_monitor_queue_work(u132, 100);
- return 0;
- }
-diff --git a/drivers/usb/host/uhci-grlib.c b/drivers/usb/host/uhci-grlib.c
-index 53c23ff..ab25dc3 100644
---- a/drivers/usb/host/uhci-grlib.c
-+++ b/drivers/usb/host/uhci-grlib.c
-@@ -141,6 +141,7 @@ static int uhci_hcd_grlib_probe(struct platform_device *op)
- if (rv)
- goto err_uhci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_uhci:
-diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
-index 3003fef..44e6c9d 100644
---- a/drivers/usb/host/uhci-platform.c
-+++ b/drivers/usb/host/uhci-platform.c
-@@ -108,6 +108,7 @@ static int uhci_hcd_platform_probe(struct platform_device *pdev)
- if (ret)
- goto err_uhci;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
-
- err_uhci:
-diff --git a/drivers/usb/host/whci/hcd.c b/drivers/usb/host/whci/hcd.c
-index 1b0888f..d7b363a 100644
---- a/drivers/usb/host/whci/hcd.c
-+++ b/drivers/usb/host/whci/hcd.c
-@@ -293,6 +293,7 @@ static int whc_probe(struct umc_dev *umc)
- dev_err(dev, "cannot add HCD: %d\n", ret);
- goto error_usb_add_hcd;
- }
-+ device_wakeup_enable(usb_hcd->self.controller);
-
- ret = wusbhc_b_create(wusbhc);
- if (ret) {
-diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
-index d9c169f..9d29aa1 100644
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -139,6 +139,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
- ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (ret)
- goto unmap_registers;
-+ device_wakeup_enable(hcd->self.controller);
-
- /* USB 2.0 roothub is stored in the platform_device now. */
- hcd = platform_get_drvdata(pdev);
-diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
-index 6582a20..e208375 100644
---- a/drivers/usb/musb/musb_host.c
-+++ b/drivers/usb/musb/musb_host.c
-@@ -2657,6 +2657,7 @@ int musb_host_setup(struct musb *musb, int power_budget)
- if (ret < 0)
- return ret;
-
-+ device_wakeup_enable(hcd->self.controller);
- return 0;
- }
-
-diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
-index e9d4cd9..3775283 100644
---- a/drivers/usb/phy/phy-msm-usb.c
-+++ b/drivers/usb/phy/phy-msm-usb.c
-@@ -669,6 +669,7 @@ static void msm_otg_start_host(struct usb_phy *phy, int on)
- pdata->setup_gpio(OTG_STATE_A_HOST);
- #ifdef CONFIG_USB
- usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
-+ device_wakeup_enable(hcd->self.controller);
- #endif
- } else {
- dev_dbg(phy->dev, "host off\n");
-diff --git a/drivers/usb/phy/phy-mv-usb.c b/drivers/usb/phy/phy-mv-usb.c
-index 98f6ac6..44f316e 100644
---- a/drivers/usb/phy/phy-mv-usb.c
-+++ b/drivers/usb/phy/phy-mv-usb.c
-@@ -213,10 +213,12 @@ static void mv_otg_start_host(struct mv_otg *mvotg, int on)
-
- hcd = bus_to_hcd(otg->host);
-
-- if (on)
-+ if (on) {
- usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
-- else
-+ device_wakeup_enable(hcd->self.controller);
-+ } else {
- usb_remove_hcd(hcd);
-+ }
- #endif /* CONFIG_USB */
- }
-
-diff --git a/drivers/usb/renesas_usbhs/mod_host.c b/drivers/usb/renesas_usbhs/mod_host.c
-index e40f565..10e1ded 100644
---- a/drivers/usb/renesas_usbhs/mod_host.c
-+++ b/drivers/usb/renesas_usbhs/mod_host.c
-@@ -1469,6 +1469,7 @@ static int usbhsh_start(struct usbhs_priv *priv)
- ret = usb_add_hcd(hcd, 0, 0);
- if (ret < 0)
- return 0;
-+ device_wakeup_enable(hcd->self.controller);
-
- /*
- * pipe initialize and enable DCP
---
-1.8.5.5
-
+++ /dev/null
-From 6b63b9b2093258541dd79a3ed311cd1d0412b846 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 14:42:39 +0100
-Subject: [PATCH] ohci-platform: Add support for devicetree instantiation
-
-Add support for ohci-platform instantiation from devicetree, including
-optionally getting clks and a phy from devicetree, and enabling / disabling
-those on power_on / off.
-
-This should allow using ohci-platform from devicetree in various cases.
-Specifically after this commit it can be used for the ohci controller found
-on Allwinner sunxi SoCs.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 22 +++
- drivers/usb/host/ohci-platform.c | 162 ++++++++++++++++++---
- 2 files changed, 162 insertions(+), 22 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/usb/usb-ohci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-new file mode 100644
-index 0000000..6ba38d9
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -0,0 +1,22 @@
-+USB OHCI controllers
-+
-+Required properties:
-+- compatible : "usb-ohci"
-+- reg : ohci controller register range (address and length)
-+- interrupts : ohci controller interrupt
-+
-+Optional properties:
-+- clocks : a list of phandle + clock specifier pairs
-+- phys : phandle + phy specifier pair
-+- phy-names : "usb"
-+
-+Example:
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "usb-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <64>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ };
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index 68f674c..49304dd 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -3,6 +3,7 @@
- *
- * Copyright 2007 Michael Buesch <m@bues.ch>
- * Copyright 2011-2012 Hauke Mehrtens <hauke@hauke-m.de>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Derived from the OCHI-SSB driver
- * Derived from the OHCI-PCI driver
-@@ -14,11 +15,14 @@
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
- #include <linux/hrtimer.h>
- #include <linux/io.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/err.h>
-+#include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/usb/ohci_pdriver.h>
- #include <linux/usb.h>
-@@ -27,6 +31,13 @@
- #include "ohci.h"
-
- #define DRIVER_DESC "OHCI generic platform driver"
-+#define OHCI_MAX_CLKS 3
-+#define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
-+
-+struct ohci_platform_priv {
-+ struct clk *clks[OHCI_MAX_CLKS];
-+ struct phy *phy;
-+};
-
- static const char hcd_name[] = "ohci-platform";
-
-@@ -48,11 +59,67 @@ static int ohci_platform_reset(struct usb_hcd *hcd)
- return ohci_setup(hcd);
- }
-
-+static int ohci_platform_power_on(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk, ret;
-+
-+ for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) {
-+ ret = clk_prepare_enable(priv->clks[clk]);
-+ if (ret)
-+ goto err_disable_clks;
-+ }
-+
-+ if (priv->phy) {
-+ ret = phy_init(priv->phy);
-+ if (ret)
-+ goto err_disable_clks;
-+
-+ ret = phy_power_on(priv->phy);
-+ if (ret)
-+ goto err_exit_phy;
-+ }
-+
-+ return 0;
-+
-+err_exit_phy:
-+ phy_exit(priv->phy);
-+err_disable_clks:
-+ while (--clk >= 0)
-+ clk_disable_unprepare(priv->clks[clk]);
-+
-+ return ret;
-+}
-+
-+static void ohci_platform_power_off(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk;
-+
-+ if (priv->phy) {
-+ phy_power_off(priv->phy);
-+ phy_exit(priv->phy);
-+ }
-+
-+ for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--)
-+ if (priv->clks[clk])
-+ clk_disable_unprepare(priv->clks[clk]);
-+}
-+
- static struct hc_driver __read_mostly ohci_platform_hc_driver;
-
- static const struct ohci_driver_overrides platform_overrides __initconst = {
-- .product_desc = "Generic Platform OHCI controller",
-- .reset = ohci_platform_reset,
-+ .product_desc = "Generic Platform OHCI controller",
-+ .reset = ohci_platform_reset,
-+ .extra_priv_size = sizeof(struct ohci_platform_priv),
-+};
-+
-+static struct usb_ohci_pdata ohci_platform_defaults = {
-+ .power_on = ohci_platform_power_on,
-+ .power_suspend = ohci_platform_power_off,
-+ .power_off = ohci_platform_power_off,
- };
-
- static int ohci_platform_probe(struct platform_device *dev)
-@@ -60,17 +127,23 @@ static int ohci_platform_probe(struct platform_device *dev)
- struct usb_hcd *hcd;
- struct resource *res_mem;
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
-- int irq;
-- int err = -ENOMEM;
--
-- if (!pdata) {
-- WARN_ON(1);
-- return -ENODEV;
-- }
-+ struct ohci_platform_priv *priv;
-+ int err, irq, clk = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
-+ /*
-+ * Use reasonable defaults so platforms don't have to provide these
-+ * with DT probing on ARM.
-+ */
-+ if (!pdata)
-+ pdata = &ohci_platform_defaults;
-+
-+ err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
-+ if (err)
-+ return err;
-+
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- dev_err(&dev->dev, "no irq provided");
-@@ -83,17 +156,40 @@ static int ohci_platform_probe(struct platform_device *dev)
- return -ENXIO;
- }
-
-+ hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev,
-+ dev_name(&dev->dev));
-+ if (!hcd)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(dev, hcd);
-+ dev->dev.platform_data = pdata;
-+ priv = hcd_to_ohci_priv(hcd);
-+
-+ if (pdata == &ohci_platform_defaults && dev->dev.of_node) {
-+ priv->phy = devm_phy_get(&dev->dev, "usb");
-+ if (IS_ERR(priv->phy)) {
-+ err = PTR_ERR(priv->phy);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_hcd;
-+ priv->phy = NULL;
-+ }
-+
-+ for (clk = 0; clk < OHCI_MAX_CLKS; clk++) {
-+ priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
-+ if (IS_ERR(priv->clks[clk])) {
-+ err = PTR_ERR(priv->clks[clk]);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_clks;
-+ priv->clks[clk] = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
- if (pdata->power_on) {
- err = pdata->power_on(dev);
- if (err < 0)
-- return err;
-- }
--
-- hcd = usb_create_hcd(&ohci_platform_hc_driver, &dev->dev,
-- dev_name(&dev->dev));
-- if (!hcd) {
-- err = -ENOMEM;
-- goto err_power;
-+ goto err_put_clks;
- }
-
- hcd->rsrc_start = res_mem->start;
-@@ -102,11 +198,11 @@ static int ohci_platform_probe(struct platform_device *dev)
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-- goto err_put_hcd;
-+ goto err_power;
- }
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
-- goto err_put_hcd;
-+ goto err_power;
-
- device_wakeup_enable(hcd->self.controller);
-
-@@ -114,11 +210,17 @@ static int ohci_platform_probe(struct platform_device *dev)
-
- return err;
-
--err_put_hcd:
-- usb_put_hcd(hcd);
- err_power:
- if (pdata->power_off)
- pdata->power_off(dev);
-+err_put_clks:
-+ while (--clk >= 0)
-+ clk_put(priv->clks[clk]);
-+err_put_hcd:
-+ if (pdata == &ohci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
-+ usb_put_hcd(hcd);
-
- return err;
- }
-@@ -127,13 +229,22 @@ static int ohci_platform_remove(struct platform_device *dev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(dev);
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ohci_platform_priv *priv = hcd_to_ohci_priv(hcd);
-+ int clk;
-
- usb_remove_hcd(hcd);
-- usb_put_hcd(hcd);
-
- if (pdata->power_off)
- pdata->power_off(dev);
-
-+ for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++)
-+ clk_put(priv->clks[clk]);
-+
-+ usb_put_hcd(hcd);
-+
-+ if (pdata == &ohci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
- return 0;
- }
-
-@@ -180,6 +291,12 @@ static int ohci_platform_resume(struct device *dev)
- #define ohci_platform_resume NULL
- #endif /* CONFIG_PM */
-
-+static const struct of_device_id ohci_platform_ids[] = {
-+ { .compatible = "usb-ohci", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, ohci_platform_ids);
-+
- static const struct platform_device_id ohci_platform_table[] = {
- { "ohci-platform", 0 },
- { }
-@@ -200,6 +317,7 @@ static int ohci_platform_resume(struct device *dev)
- .owner = THIS_MODULE,
- .name = "ohci-platform",
- .pm = &ohci_platform_pm_ops,
-+ .of_match_table = ohci_platform_ids,
- }
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 543824fa2a8a592a6eec0e0053063284980dc378 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 5 Jan 2014 00:04:02 +0100
-Subject: [PATCH] ehci-platform: Add support for clks and phy passed through
- devicetree
-
-Currently ehci-platform is only used in combination with devicetree when used
-with some Via socs. By extending it to (optionally) get clks and a phy from
-devicetree, and enabling / disabling those on power_on / off, it can be used
-more generically. Specifically after this commit it can be used for the
-ehci controller on Allwinner sunxi SoCs.
-
-Since ehci-platform is intended to handle any generic enough non pci ehci
-device, add a "usb-ehci" compatibility string.
-
-There already is a usb-ehci device-tree bindings document, update this
-with clks and phy bindings info.
-
-Although actually quite generic so far the via,vt8500 compatibilty string
-had its own bindings document. Somehow we even ended up with 2 of them. Since
-these provide no extra information over the generic usb-ehci documentation,
-this patch removes them.
-
-The ehci-ppc-of.c driver also claims the usb-ehci compatibility string,
-even though it mostly is ibm,usb-ehci-440epx specific. ehci-platform.c is
-not needed on ppc platforms, so add a !PPC_OF dependency to it to avoid
-2 drivers claiming the same compatibility string getting build on ppc.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Acked-by: Alan Stern <stern@rowland.harvard.edu>
----
- Documentation/devicetree/bindings/usb/usb-ehci.txt | 25 +++-
- .../devicetree/bindings/usb/via,vt8500-ehci.txt | 15 ---
- .../devicetree/bindings/usb/vt8500-ehci.txt | 12 --
- drivers/usb/host/Kconfig | 1 +
- drivers/usb/host/ehci-platform.c | 147 +++++++++++++++++----
- 5 files changed, 142 insertions(+), 58 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
- delete mode 100644 Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-index fa18612..2c1aeeb 100644
---- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-@@ -7,13 +7,14 @@ Required properties:
- (debug-port or other) can be also specified here, but only after
- definition of standard EHCI registers.
- - interrupts : one EHCI interrupt should be described here.
--If device registers are implemented in big endian mode, the device
--node should have "big-endian-regs" property.
--If controller implementation operates with big endian descriptors,
--"big-endian-desc" property should be specified.
--If both big endian registers and descriptors are used by the controller
--implementation, "big-endian" property can be specified instead of having
--both "big-endian-regs" and "big-endian-desc".
-+
-+Optional properties:
-+ - big-endian-regs : boolean, set this for hcds with big-endian registers
-+ - big-endian-desc : boolean, set this for hcds with big-endian descriptors
-+ - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
-+ - clocks : a list of phandle + clock specifier pairs
-+ - phys : phandle + phy specifier pair
-+ - phy-names : "usb"
-
- Example (Sequoia 440EPx):
- ehci@e0000300 {
-@@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
- reg = <0 e0000300 90 0 e0000390 70>;
- big-endian;
- };
-+
-+Example (Allwinner sun4i A10 SoC):
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ };
-diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
-deleted file mode 100644
-index 17b3ad1..0000000
---- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
-+++ /dev/null
-@@ -1,15 +0,0 @@
--VIA/Wondermedia VT8500 EHCI Controller
-------------------------------------------------------
--
--Required properties:
--- compatible : "via,vt8500-ehci"
--- reg : Should contain 1 register ranges(address and length)
--- interrupts : ehci controller interrupt
--
--Example:
--
-- ehci@d8007900 {
-- compatible = "via,vt8500-ehci";
-- reg = <0xd8007900 0x200>;
-- interrupts = <43>;
-- };
-diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-deleted file mode 100644
-index 5fb8fd6..0000000
---- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
-+++ /dev/null
-@@ -1,12 +0,0 @@
--VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
--
--Required properties:
-- - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
-- - reg: Address range of the ehci registers. size should be 0x200
-- - interrupts: Should contain the ehci interrupt.
--
--usb: ehci@D8007100 {
-- compatible = "wm,prizm-ehci", "usb-ehci";
-- reg = <0xD8007100 0x200>;
-- interrupts = <1>;
--};
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index a9707da..e28cbe0 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -255,6 +255,7 @@ config USB_EHCI_ATH79
-
- config USB_EHCI_HCD_PLATFORM
- tristate "Generic EHCI driver for a platform device"
-+ depends on !PPC_OF
- default n
- ---help---
- Adds an EHCI host driver for a generic platform device, which
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 01536cf..5ebd0b7 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -3,6 +3,7 @@
- *
- * Copyright 2007 Steven Brown <sbrown@cortland.com>
- * Copyright 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
-+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * Derived from the ohci-ssb driver
- * Copyright 2007 Michael Buesch <m@bues.ch>
-@@ -18,6 +19,7 @@
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-+#include <linux/clk.h>
- #include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/kernel.h>
-@@ -25,6 +27,7 @@
- #include <linux/io.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/usb.h>
- #include <linux/usb/hcd.h>
-@@ -33,6 +36,13 @@
- #include "ehci.h"
-
- #define DRIVER_DESC "EHCI generic platform driver"
-+#define EHCI_MAX_CLKS 3
-+#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
-+
-+struct ehci_platform_priv {
-+ struct clk *clks[EHCI_MAX_CLKS];
-+ struct phy *phy;
-+};
-
- static const char hcd_name[] = "ehci-platform";
-
-@@ -64,38 +74,90 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
- return 0;
- }
-
-+static int ehci_platform_power_on(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk, ret;
-+
-+ for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
-+ ret = clk_prepare_enable(priv->clks[clk]);
-+ if (ret)
-+ goto err_disable_clks;
-+ }
-+
-+ if (priv->phy) {
-+ ret = phy_init(priv->phy);
-+ if (ret)
-+ goto err_disable_clks;
-+
-+ ret = phy_power_on(priv->phy);
-+ if (ret)
-+ goto err_exit_phy;
-+ }
-+
-+ return 0;
-+
-+err_exit_phy:
-+ phy_exit(priv->phy);
-+err_disable_clks:
-+ while (--clk >= 0)
-+ clk_disable_unprepare(priv->clks[clk]);
-+
-+ return ret;
-+}
-+
-+static void ehci_platform_power_off(struct platform_device *dev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk;
-+
-+ if (priv->phy) {
-+ phy_power_off(priv->phy);
-+ phy_exit(priv->phy);
-+ }
-+
-+ for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
-+ if (priv->clks[clk])
-+ clk_disable_unprepare(priv->clks[clk]);
-+}
-+
- static struct hc_driver __read_mostly ehci_platform_hc_driver;
-
- static const struct ehci_driver_overrides platform_overrides __initconst = {
-- .reset = ehci_platform_reset,
-+ .reset = ehci_platform_reset,
-+ .extra_priv_size = sizeof(struct ehci_platform_priv),
- };
-
--static struct usb_ehci_pdata ehci_platform_defaults;
-+static struct usb_ehci_pdata ehci_platform_defaults = {
-+ .power_on = ehci_platform_power_on,
-+ .power_suspend = ehci_platform_power_off,
-+ .power_off = ehci_platform_power_off,
-+};
-
- static int ehci_platform_probe(struct platform_device *dev)
- {
- struct usb_hcd *hcd;
- struct resource *res_mem;
-- struct usb_ehci_pdata *pdata;
-- int irq;
-- int err;
-+ struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ehci_platform_priv *priv;
-+ int err, irq, clk = 0;
-
- if (usb_disabled())
- return -ENODEV;
-
- /*
-- * use reasonable defaults so platforms don't have to provide these.
-- * with DT probing on ARM, none of these are set.
-+ * Use reasonable defaults so platforms don't have to provide these
-+ * with DT probing on ARM.
- */
-- if (!dev_get_platdata(&dev->dev))
-- dev->dev.platform_data = &ehci_platform_defaults;
-+ if (!pdata)
-+ pdata = &ehci_platform_defaults;
-
- err = dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
- if (err)
- return err;
-
-- pdata = dev_get_platdata(&dev->dev);
--
- irq = platform_get_irq(dev, 0);
- if (irq < 0) {
- dev_err(&dev->dev, "no irq provided");
-@@ -107,17 +169,40 @@ static int ehci_platform_probe(struct platform_device *dev)
- return -ENXIO;
- }
-
-+ hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
-+ dev_name(&dev->dev));
-+ if (!hcd)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(dev, hcd);
-+ dev->dev.platform_data = pdata;
-+ priv = hcd_to_ehci_priv(hcd);
-+
-+ if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
-+ priv->phy = devm_phy_get(&dev->dev, "usb");
-+ if (IS_ERR(priv->phy)) {
-+ err = PTR_ERR(priv->phy);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_hcd;
-+ priv->phy = NULL;
-+ }
-+
-+ for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
-+ priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
-+ if (IS_ERR(priv->clks[clk])) {
-+ err = PTR_ERR(priv->clks[clk]);
-+ if (err == -EPROBE_DEFER)
-+ goto err_put_clks;
-+ priv->clks[clk] = NULL;
-+ break;
-+ }
-+ }
-+ }
-+
- if (pdata->power_on) {
- err = pdata->power_on(dev);
- if (err < 0)
-- return err;
-- }
--
-- hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
-- dev_name(&dev->dev));
-- if (!hcd) {
-- err = -ENOMEM;
-- goto err_power;
-+ goto err_put_clks;
- }
-
- hcd->rsrc_start = res_mem->start;
-@@ -126,22 +211,28 @@ static int ehci_platform_probe(struct platform_device *dev)
- hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
- if (IS_ERR(hcd->regs)) {
- err = PTR_ERR(hcd->regs);
-- goto err_put_hcd;
-+ goto err_power;
- }
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
-- goto err_put_hcd;
-+ goto err_power;
-
- device_wakeup_enable(hcd->self.controller);
- platform_set_drvdata(dev, hcd);
-
- return err;
-
--err_put_hcd:
-- usb_put_hcd(hcd);
- err_power:
- if (pdata->power_off)
- pdata->power_off(dev);
-+err_put_clks:
-+ while (--clk >= 0)
-+ clk_put(priv->clks[clk]);
-+err_put_hcd:
-+ if (pdata == &ehci_platform_defaults)
-+ dev->dev.platform_data = NULL;
-+
-+ usb_put_hcd(hcd);
-
- return err;
- }
-@@ -150,13 +241,19 @@ static int ehci_platform_remove(struct platform_device *dev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(dev);
- struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
-+ struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
-+ int clk;
-
- usb_remove_hcd(hcd);
-- usb_put_hcd(hcd);
-
- if (pdata->power_off)
- pdata->power_off(dev);
-
-+ for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
-+ clk_put(priv->clks[clk]);
-+
-+ usb_put_hcd(hcd);
-+
- if (pdata == &ehci_platform_defaults)
- dev->dev.platform_data = NULL;
-
-@@ -207,8 +304,10 @@ static int ehci_platform_resume(struct device *dev)
- static const struct of_device_id vt8500_ehci_ids[] = {
- { .compatible = "via,vt8500-ehci", },
- { .compatible = "wm,prizm-ehci", },
-+ { .compatible = "usb-ehci", },
- {}
- };
-+MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
-
- static const struct platform_device_id ehci_platform_table[] = {
- { "ehci-platform", 0 },
---
-1.8.5.5
-
+++ /dev/null
-From 10d7c018269928db8487057c4c143dbd014d2262 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 21 Jan 2014 16:05:47 +0100
-Subject: [PATCH] ohci-platform: Add support for controllers with big-endian
- regs / descriptors
-
-Note this commit uses the same devicetree booleans for this as the ones
-already existing in the usb-ehci bindings, see:
-Documentation/devicetree/bindings/usb/usb-ehci.txt
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 3 +++
- drivers/usb/host/ohci-platform.c | 27 ++++++++++++++++++++++
- 2 files changed, 30 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-index 6ba38d9..6933b0c 100644
---- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -6,6 +6,9 @@ Required properties:
- - interrupts : ohci controller interrupt
-
- Optional properties:
-+- big-endian-regs : boolean, set this for hcds with big-endian registers
-+- big-endian-desc : boolean, set this for hcds with big-endian descriptors
-+- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
- - clocks : a list of phandle + clock specifier pairs
- - phys : phandle + phy specifier pair
- - phy-names : "usb"
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index 49304dd..e2c28fd 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -128,6 +128,7 @@ static int ohci_platform_probe(struct platform_device *dev)
- struct resource *res_mem;
- struct usb_ohci_pdata *pdata = dev_get_platdata(&dev->dev);
- struct ohci_platform_priv *priv;
-+ struct ohci_hcd *ohci;
- int err, irq, clk = 0;
-
- if (usb_disabled())
-@@ -164,8 +165,34 @@ static int ohci_platform_probe(struct platform_device *dev)
- platform_set_drvdata(dev, hcd);
- dev->dev.platform_data = pdata;
- priv = hcd_to_ohci_priv(hcd);
-+ ohci = hcd_to_ohci(hcd);
-
- if (pdata == &ohci_platform_defaults && dev->dev.of_node) {
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
-+ ohci->flags |= OHCI_QUIRK_BE_MMIO;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-desc"))
-+ ohci->flags |= OHCI_QUIRK_BE_DESC;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian"))
-+ ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC;
-+
-+#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
-+ if (ohci->flags & OHCI_QUIRK_BE_MMIO) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-regs not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
-+#ifndef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
-+ if (ohci->flags & OHCI_QUIRK_BE_DESC) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-desc not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
- priv->phy = devm_phy_get(&dev->dev, "usb");
- if (IS_ERR(priv->phy)) {
- err = PTR_ERR(priv->phy);
---
-1.8.5.5
-
+++ /dev/null
-From 57b5e74a0d7ba5dbf77ee05a2693635faba5fe30 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 21 Jan 2014 16:20:53 +0100
-Subject: [PATCH] ehci-platform: Add support for controllers with big-endian
- regs / descriptors
-
-This uses the already documented devicetree booleans for this, see:
-Documentation/devicetree/bindings/usb/usb-ehci.txt
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/usb/host/ehci-platform.c | 33 +++++++++++++++++++++++++++++++--
- 1 file changed, 31 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 5ebd0b7..8fde649 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -55,8 +55,10 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
-
- hcd->has_tt = pdata->has_tt;
- ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug;
-- ehci->big_endian_desc = pdata->big_endian_desc;
-- ehci->big_endian_mmio = pdata->big_endian_mmio;
-+ if (pdata->big_endian_desc)
-+ ehci->big_endian_desc = 1;
-+ if (pdata->big_endian_mmio)
-+ ehci->big_endian_mmio = 1;
- ehci->ignore_oc = pdata->ignore_oc;
-
- if (pdata->pre_setup) {
-@@ -142,6 +144,7 @@ static int ehci_platform_probe(struct platform_device *dev)
- struct resource *res_mem;
- struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
- struct ehci_platform_priv *priv;
-+ struct ehci_hcd *ehci;
- int err, irq, clk = 0;
-
- if (usb_disabled())
-@@ -177,8 +180,34 @@ static int ehci_platform_probe(struct platform_device *dev)
- platform_set_drvdata(dev, hcd);
- dev->dev.platform_data = pdata;
- priv = hcd_to_ehci_priv(hcd);
-+ ehci = hcd_to_ehci(hcd);
-
- if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
-+ ehci->big_endian_mmio = 1;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian-desc"))
-+ ehci->big_endian_desc = 1;
-+
-+ if (of_property_read_bool(dev->dev.of_node, "big-endian"))
-+ ehci->big_endian_mmio = ehci->big_endian_desc = 1;
-+
-+#ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
-+ if (ehci->big_endian_mmio) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-regs not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
-+#ifndef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
-+ if (ehci->big_endian_desc) {
-+ dev_err(&dev->dev,
-+ "Error big-endian-desc not compiled in\n");
-+ err = -EINVAL;
-+ goto err_put_hcd;
-+ }
-+#endif
- priv->phy = devm_phy_get(&dev->dev, "usb");
- if (IS_ERR(priv->phy)) {
- err = PTR_ERR(priv->phy);
---
-1.8.5.5
-
+++ /dev/null
-From abddd82743cc2c4acdfe66a6d5e63f2085d2269b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 11:27:29 +0100
-Subject: [PATCH] ohci-platform: Change compatible string from usb-ohci to
- generic-ohci
-
-The initial versions of the devicetree enablement patches for ohci-platform
-used "ohci-platform" as compatible string. However this was disliked by various
-reviewers because the platform bus is a Linux invention and devicetree is
-supposed to be OS agnostic. After much discussion I gave up and went with
-the generic usb-ohci as requested.
-
-In retro-spect I should have chosen something different, the dts files for many
-existing boards already claim to be compatible with "usb-ohci", ie they have:
-
- compatible = "ti,ohci-omap3", "usb-ohci";
-
-In theory this should not be a problem since the "ti,ohci-omap3" entry takes
-presedence, but in practice using a conflicting compatible string is an issue,
-because it makes which driver gets used depend on driver registration order.
-
-This patch changes the compatible string claimed by ohci-platform to
-"generic-ohci", avoiding the driver registration / module loading ordering
-problems.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ohci.txt | 4 ++--
- drivers/usb/host/ohci-platform.c | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-index 6933b0c..45f67d9 100644
---- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
-@@ -1,7 +1,7 @@
- USB OHCI controllers
-
- Required properties:
--- compatible : "usb-ohci"
-+- compatible : "generic-ohci"
- - reg : ohci controller register range (address and length)
- - interrupts : ohci controller interrupt
-
-@@ -16,7 +16,7 @@ Optional properties:
- Example:
-
- ohci0: usb@01c14400 {
-- compatible = "allwinner,sun4i-a10-ohci", "usb-ohci";
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
- reg = <0x01c14400 0x100>;
- interrupts = <64>;
- clocks = <&usb_clk 6>, <&ahb_gates 2>;
-diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
-index e2c28fd..b6ca0b2 100644
---- a/drivers/usb/host/ohci-platform.c
-+++ b/drivers/usb/host/ohci-platform.c
-@@ -319,7 +319,7 @@ static int ohci_platform_resume(struct device *dev)
- #endif /* CONFIG_PM */
-
- static const struct of_device_id ohci_platform_ids[] = {
-- { .compatible = "usb-ohci", },
-+ { .compatible = "generic-ohci", },
- { }
- };
- MODULE_DEVICE_TABLE(of, ohci_platform_ids);
---
-1.8.5.5
-
+++ /dev/null
-From 80c544c77beeffee4e9484bf193ab391297688cd Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 11:46:13 +0100
-Subject: [PATCH] ehci-platform: Change compatible string from usb-ehci to
- generic-ehci
-
-The initial versions of the devicetree enablement patches for ehci-platform
-used "ehci-platform" as compatible string. However this was disliked by various
-reviewers because the platform bus is a Linux invention and devicetree is
-supposed to be OS agnostic. After much discussion I gave up, added a:
-"depends on !PPC_OF" to Kconfig to avoid a known conflict with PPC-OF platforms
-and went with the generic usb-ehci as requested.
-
-In retro-spect I should have chosen something different, the dts files for many
-existing boards already claim to be compatible with "usb-ehci", ie they have:
-
- compatible = "ti,ehci-omap", "usb-ehci";
-
-In theory this should not be a problem since the "ti,ehci-omap" entry takes
-presedence, but in practice using a conflicting compatible string is an issue,
-because it makes which driver gets used depend on driver registration order.
-
-This patch changes the compatible string claimed by ehci-platform to
-"generic-ehci", avoiding the driver registration / module loading ordering
-problems, and removes the "depends on !PPC_OF" workaround.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-ehci.txt | 4 ++--
- drivers/usb/host/Kconfig | 1 -
- drivers/usb/host/ehci-platform.c | 2 +-
- 3 files changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-index 2c1aeeb..ff151ec 100644
---- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
-@@ -1,7 +1,7 @@
- USB EHCI controllers
-
- Required properties:
-- - compatible : should be "usb-ehci".
-+ - compatible : should be "generic-ehci".
- - reg : should contain at least address and length of the standard EHCI
- register set for the device. Optional platform-dependent registers
- (debug-port or other) can be also specified here, but only after
-@@ -27,7 +27,7 @@ Example (Sequoia 440EPx):
-
- Example (Allwinner sun4i A10 SoC):
- ehci0: usb@01c14000 {
-- compatible = "allwinner,sun4i-a10-ehci", "usb-ehci";
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
- reg = <0x01c14000 0x100>;
- interrupts = <39>;
- clocks = <&ahb_gates 1>;
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index e28cbe0..a9707da 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -255,7 +255,6 @@ config USB_EHCI_ATH79
-
- config USB_EHCI_HCD_PLATFORM
- tristate "Generic EHCI driver for a platform device"
-- depends on !PPC_OF
- default n
- ---help---
- Adds an EHCI host driver for a generic platform device, which
-diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
-index 8fde649..1178730 100644
---- a/drivers/usb/host/ehci-platform.c
-+++ b/drivers/usb/host/ehci-platform.c
-@@ -333,7 +333,7 @@ static int ehci_platform_resume(struct device *dev)
- static const struct of_device_id vt8500_ehci_ids[] = {
- { .compatible = "via,vt8500-ehci", },
- { .compatible = "wm,prizm-ehci", },
-- { .compatible = "usb-ehci", },
-+ { .compatible = "generic-ehci", },
- {}
- };
- MODULE_DEVICE_TABLE(of, vt8500_ehci_ids);
---
-1.8.5.5
-
+++ /dev/null
-From 3aa1e8b65b7db768fade643e26f8995860596795 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 17:41:48 +0100
-Subject: [PATCH] uhci-platform: Change compatible string from platform-uhci to
- generic-uhci
-
-This brings the uhci-platform bindings in sync with what we've done for
-the ohci- and ehci-platform drivers. As discussed there using platform as a
-prefix is a bit weird as the platform bus is a Linux specific thing and
-the bindings are supposed to be OS agnostic.
-
-Note that the old platform-uhci compatible string is kept around for, well,
-compatibility reasons.
-
-While at it rename the bindings txt file to match the name of all the
-other ?hci-platform bindings docs.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/platform-uhci.txt | 15 ---------------
- Documentation/devicetree/bindings/usb/usb-uhci.txt | 15 +++++++++++++++
- drivers/usb/host/uhci-platform.c | 1 +
- 3 files changed, 16 insertions(+), 15 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/usb/platform-uhci.txt
- create mode 100644 Documentation/devicetree/bindings/usb/usb-uhci.txt
-
-diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
-deleted file mode 100644
-index a4fb071..0000000
---- a/Documentation/devicetree/bindings/usb/platform-uhci.txt
-+++ /dev/null
-@@ -1,15 +0,0 @@
--Generic Platform UHCI Controller
-------------------------------------------------------
--
--Required properties:
--- compatible : "platform-uhci"
--- reg : Should contain 1 register ranges(address and length)
--- interrupts : UHCI controller interrupt
--
--Example:
--
-- uhci@d8007b00 {
-- compatible = "platform-uhci";
-- reg = <0xd8007b00 0x200>;
-- interrupts = <43>;
-- };
-diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt
-new file mode 100644
-index 0000000..2981334
---- /dev/null
-+++ b/Documentation/devicetree/bindings/usb/usb-uhci.txt
-@@ -0,0 +1,15 @@
-+Generic Platform UHCI Controller
-+-----------------------------------------------------
-+
-+Required properties:
-+- compatible : "generic-uhci" (deprecated: "platform-uhci")
-+- reg : Should contain 1 register ranges(address and length)
-+- interrupts : UHCI controller interrupt
-+
-+Example:
-+
-+ uhci@d8007b00 {
-+ compatible = "generic-uhci";
-+ reg = <0xd8007b00 0x200>;
-+ interrupts = <43>;
-+ };
-diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platform.c
-index 44e6c9d..01833ab 100644
---- a/drivers/usb/host/uhci-platform.c
-+++ b/drivers/usb/host/uhci-platform.c
-@@ -148,6 +148,7 @@ static void uhci_hcd_platform_shutdown(struct platform_device *op)
- }
-
- static const struct of_device_id platform_uhci_ids[] = {
-+ { .compatible = "generic-uhci", },
- { .compatible = "platform-uhci", },
- {}
- };
---
-1.8.5.5
-
+++ /dev/null
-From 1f5109503787538c4a5deb3be7da8336951b105b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 11 Feb 2014 17:50:51 +0100
-Subject: [PATCH] xhci-platform: Change compatible string from xhci-platform to
- generic-xhci
-
-This brings the xhci-platform bindings in sync with what we've done for
-the ohci- and ehci-platform drivers. As discussed there using platform as a
-postfix is a bit weird as the platform bus is a Linux specific thing and
-the bindings are supposed to be OS agnostic.
-
-Note that the old xhci-platform compatible string is kept around for, well,
-compatibility reasons.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/usb/usb-xhci.txt | 4 ++--
- drivers/usb/host/xhci-plat.c | 1 +
- 2 files changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-index 5752df0..90f8f60 100644
---- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
-+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
-@@ -1,14 +1,14 @@
- USB xHCI controllers
-
- Required properties:
-- - compatible: should be "xhci-platform".
-+ - compatible: should be "generic-xhci" (deprecated: "xhci-platform").
- - reg: should contain address and length of the standard XHCI
- register set for the device.
- - interrupts: one XHCI interrupt should be described here.
-
- Example:
- usb@f0931000 {
-- compatible = "xhci-platform";
-+ compatible = "generic-xhci";
- reg = <0xf0931000 0x8c8>;
- interrupts = <0x0 0x4e 0x0>;
- };
-diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
-index 8abda5c..8affef9 100644
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -226,6 +226,7 @@ static int xhci_plat_resume(struct device *dev)
-
- #ifdef CONFIG_OF
- static const struct of_device_id usb_xhci_of_match[] = {
-+ { .compatible = "generic-xhci" },
- { .compatible = "xhci-platform" },
- { },
- };
---
-1.8.5.5
-
+++ /dev/null
-From edb7ebba49b6946e80dfac0d13ac15028952aa29 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Thu, 9 Jan 2014 19:33:04 +0100
-Subject: [PATCH] clk: sunxi: Add support for USB clock-register reset bits
-
-The usb-clk register is special in that it not only contains clk gate bits,
-but also has a few reset bits. This commit adds support for this by allowing
-gates type sunxi clks to also register a reset controller.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 71 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 46a38b4..2dbaee7 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -18,6 +18,7 @@
- #include <linux/clkdev.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-+#include <linux/reset-controller.h>
-
- #include "clk-factors.h"
-
-@@ -852,6 +853,59 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
-
- /**
-+ * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
-+ */
-+
-+struct gates_reset_data {
-+ void __iomem *reg;
-+ spinlock_t *lock;
-+ struct reset_controller_dev rcdev;
-+};
-+
-+static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct gates_reset_data *data = container_of(rcdev,
-+ struct gates_reset_data,
-+ rcdev);
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(data->lock, flags);
-+
-+ reg = readl(data->reg);
-+ writel(reg & ~BIT(id), data->reg);
-+
-+ spin_unlock_irqrestore(data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct gates_reset_data *data = container_of(rcdev,
-+ struct gates_reset_data,
-+ rcdev);
-+ unsigned long flags;
-+ u32 reg;
-+
-+ spin_lock_irqsave(data->lock, flags);
-+
-+ reg = readl(data->reg);
-+ writel(reg | BIT(id), data->reg);
-+
-+ spin_unlock_irqrestore(data->lock, flags);
-+
-+ return 0;
-+}
-+
-+static struct reset_control_ops sunxi_gates_reset_ops = {
-+ .assert = sunxi_gates_reset_assert,
-+ .deassert = sunxi_gates_reset_deassert,
-+};
-+
-+/**
- * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
- */
-
-@@ -859,6 +913,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
- struct gates_data {
- DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
-+ u32 reset_mask;
- };
-
- static const struct gates_data sun4i_axi_gates_data __initconst = {
-@@ -929,6 +984,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
- {
- struct clk_onecell_data *clk_data;
-+ struct gates_reset_data *reset_data;
- const char *clk_parent;
- const char *clk_name;
- void *reg;
-@@ -972,6 +1028,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+ /* Register a reset controler for gates with reset bits */
-+ if (data->reset_mask == 0)
-+ return;
-+
-+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
-+ if (!reset_data)
-+ return;
-+
-+ reset_data->reg = reg;
-+ reset_data->lock = &clk_lock;
-+ reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
-+ reset_data->rcdev.ops = &sunxi_gates_reset_ops;
-+ reset_data->rcdev.of_node = node;
-+ reset_controller_register(&reset_data->rcdev);
- }
-
-
---
-1.8.5.5
-
+++ /dev/null
-From a6459be451bc7eb541aca2be3b36b06955d06622 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:59:32 +0200
-Subject: [PATCH] clk: sunxi: Add USB clock register defintions
-
-Add register definitions for the usb-clk register found on sun4i, sun5i and
-sun7i SoCs.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++
- drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index 0da774c..c77a5b8 100644
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 2dbaee7..9daa9b0 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -924,6 +924,16 @@ struct gates_data {
- .mask = {0x7F77FFF, 0x14FB3F},
- };
-
-+static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
-+ .mask = {0x1C0},
-+ .reset_mask = 0x07,
-+};
-+
-+static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
-+ .mask = {0x140},
-+ .reset_mask = 0x03,
-+};
-+
- static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
- };
-@@ -1271,6 +1281,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
-+ {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
-+ {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
- {}
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From c3593cc95c240663bd9c191c1029237e467575af Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 7 Feb 2014 18:08:03 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add sun4i-a10-usb-vbus-reg dts include file
-
-Almost all sun4i and sun7i boards have a gpio controlled vbus for usb1 and
-usb2, using gpio pin PH6 and PH3 as in the reference design. This commit adds
-an include file for this, avoiding the need to copy and paste the exact same
-dts code to almost all sun4i and sun7i dts files.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi | 54 +++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..803be0c
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-usb-vbus-reg.dtsi
-@@ -0,0 +1,54 @@
-+/*
-+ * sun4i boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
-+ allwinner,pins = "PH6";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
-+ allwinner,pins = "PH3";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb1_vbus_pin_a>;
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 7 6 0>;
-+ };
-+
-+ reg_usb2_vbus: usb2-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb2_vbus_pin_a>;
-+ regulator-name = "usb2-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 7 3 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From d11b47592e6af40fff595900c2af30774ee0b88e Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sun, 9 Feb 2014 14:17:28 +0100
-Subject: [PATCH] ARM: sun5i: dt: Add sun5i-a1*-usb-vbus-reg dts include files
-
-Almost all sun5i-a10s boards have a gpio controlled vbus for usb1 using gpio
-pin PB10 as in the reference design. This commit adds an include file for this,
-avoiding the need to copy and paste the dts code.
-
-For sun5i-a13 based board the reference design uses a gpio on the pmic, which
-we don't support yet. Still for consistency with all the other dts files also
-add a sun5i-a13-usb-vbus-reg.dtsi files, without a gpio reference for now.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi | 36 ++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi | 23 ++++++++++++++++
- 2 files changed, 59 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
- create mode 100644 arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..bb1a693
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a10s-usb-vbus-reg.dtsi
-@@ -0,0 +1,36 @@
-+/*
-+ * sun5i a10s boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ soc@01c00000 {
-+ pio: pinctrl@01c20800 {
-+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
-+ allwinner,pins = "PB10";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+ };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb1_vbus_pin_a>;
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ gpio = <&pio 1 10 0>;
-+ };
-+};
-diff --git a/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi b/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-new file mode 100644
-index 0000000..4d70b9a
---- /dev/null
-+++ b/arch/arm/boot/dts/sun5i-a13-usb-vbus-reg.dtsi
-@@ -0,0 +1,23 @@
-+/*
-+ * sun5i a13 boards usb vbus supply common code
-+ *
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/ {
-+ reg_usb1_vbus: usb1-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ enable-active-high;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From ac74dd1167924c412498a651edda63df49941f10 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 4 Jan 2014 23:56:17 +0100
-Subject: [PATCH] ARM: sunxi: Add driver for sunxi usb phy
-
-The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
-through a single set of registers. Besides this there are also some other
-phy related bits which need poking, which are per phy, but shared between the
-ohci and ehci controllers, so these are also controlled from this new phy
-driver.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../devicetree/bindings/phy/sun4i-usb-phy.txt | 26 ++
- drivers/phy/Kconfig | 11 +
- drivers/phy/Makefile | 1 +
- drivers/phy/phy-sun4i-usb.c | 329 +++++++++++++++++++++
- 4 files changed, 367 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
- create mode 100644 drivers/phy/phy-sun4i-usb.c
-
-diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
-new file mode 100644
-index 0000000..a82361b
---- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
-@@ -0,0 +1,26 @@
-+Allwinner sun4i USB PHY
-+-----------------------
-+
-+Required properties:
-+- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
-+ "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
-+- reg : a list of offset + length pairs
-+- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
-+- #phy-cells : from the generic phy bindings, must be 1
-+- clocks : phandle + clock specifier for the phy clock
-+- clock-names : "usb_phy"
-+- resets : a list of phandle + reset specifier pairs
-+- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
-+
-+Example:
-+ usbphy: phy@0x01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-phy";
-+ /* phy base regs, phy1 pmu reg, phy2 pmu reg */
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ };
-diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
-index 4ef8755..6e336b4 100644
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -64,4 +64,15 @@ config BCM_KONA_USB2_PHY
- help
- Enable this to support the Broadcom Kona USB 2.0 PHY.
-
-+config PHY_SUN4I_USB
-+ tristate "Allwinner sunxi SoC USB PHY driver"
-+ depends on ARCH_SUNXI
-+ select GENERIC_PHY
-+ help
-+ Enable this to support the transceiver that is part of Allwinner
-+ sunxi SoCs.
-+
-+ This driver controls the entire USB PHY block, both the USB OTG
-+ parts, as well as the 2 regular USB 2 host PHYs.
-+
- endmenu
-diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
-index b57c253..9d4f8bb 100644
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
- obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
- obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
- obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
-+obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
-diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
-new file mode 100644
-index 0000000..31c4611
---- /dev/null
-+++ b/drivers/phy/phy-sun4i-usb.c
-@@ -0,0 +1,329 @@
-+/*
-+ * Allwinner sun4i USB phy driver
-+ *
-+ * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * Based on code from
-+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
-+ *
-+ * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
-+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
-+ * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+
-+#define REG_ISCR 0x00
-+#define REG_PHYCTL 0x04
-+#define REG_PHYBIST 0x08
-+#define REG_PHYTUNE 0x0c
-+
-+#define SUNXI_AHB_ICHR8_EN BIT(10)
-+#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
-+#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
-+#define SUNXI_ULPI_BYPASS_EN BIT(0)
-+
-+/* Common Control Bits for Both PHYs */
-+#define PHY_PLL_BW 0x03
-+#define PHY_RES45_CAL_EN 0x0c
-+
-+/* Private Control Bits for Each PHY */
-+#define PHY_TX_AMPLITUDE_TUNE 0x20
-+#define PHY_TX_SLEWRATE_TUNE 0x22
-+#define PHY_VBUSVALID_TH_SEL 0x25
-+#define PHY_PULLUP_RES_SEL 0x27
-+#define PHY_OTG_FUNC_EN 0x28
-+#define PHY_VBUS_DET_EN 0x29
-+#define PHY_DISCON_TH_SEL 0x2a
-+
-+#define MAX_PHYS 3
-+
-+struct sun4i_usb_phy_data {
-+ struct clk *clk;
-+ void __iomem *base;
-+ struct mutex mutex;
-+ int num_phys;
-+ u32 disc_thresh;
-+ struct sun4i_usb_phy {
-+ struct phy *phy;
-+ void __iomem *pmu;
-+ struct regulator *vbus;
-+ struct reset_control *reset;
-+ int index;
-+ } phys[MAX_PHYS];
-+};
-+
-+#define to_sun4i_usb_phy_data(phy) \
-+ container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
-+
-+static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
-+ int len)
-+{
-+ struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
-+ u32 temp, usbc_bit = BIT(phy->index * 2);
-+ int i;
-+
-+ mutex_lock(&phy_data->mutex);
-+
-+ for (i = 0; i < len; i++) {
-+ temp = readl(phy_data->base + REG_PHYCTL);
-+
-+ /* clear the address portion */
-+ temp &= ~(0xff << 8);
-+
-+ /* set the address */
-+ temp |= ((addr + i) << 8);
-+ writel(temp, phy_data->base + REG_PHYCTL);
-+
-+ /* set the data bit and clear usbc bit*/
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ if (data & 0x1)
-+ temp |= BIT(7);
-+ else
-+ temp &= ~BIT(7);
-+ temp &= ~usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ /* pulse usbc_bit */
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ temp |= usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ temp = readb(phy_data->base + REG_PHYCTL);
-+ temp &= ~usbc_bit;
-+ writeb(temp, phy_data->base + REG_PHYCTL);
-+
-+ data >>= 1;
-+ }
-+ mutex_unlock(&phy_data->mutex);
-+}
-+
-+static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
-+{
-+ u32 bits, reg_value;
-+
-+ if (!phy->pmu)
-+ return;
-+
-+ bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
-+ SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
-+
-+ reg_value = readl(phy->pmu);
-+
-+ if (enable)
-+ reg_value |= bits;
-+ else
-+ reg_value &= ~bits;
-+
-+ writel(reg_value, phy->pmu);
-+}
-+
-+static int sun4i_usb_phy_init(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
-+ int ret;
-+
-+ ret = clk_prepare_enable(data->clk);
-+ if (ret)
-+ return ret;
-+
-+ ret = reset_control_deassert(phy->reset);
-+ if (ret) {
-+ clk_disable_unprepare(data->clk);
-+ return ret;
-+ }
-+
-+ /* Adjust PHY's magnitude and rate */
-+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
-+
-+ /* Disconnect threshold adjustment */
-+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
-+
-+ sun4i_usb_phy_passby(phy, 1);
-+
-+ return 0;
-+}
-+
-+static int sun4i_usb_phy_exit(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
-+
-+ sun4i_usb_phy_passby(phy, 0);
-+ reset_control_assert(phy->reset);
-+ clk_disable_unprepare(data->clk);
-+
-+ return 0;
-+}
-+
-+static int sun4i_usb_phy_power_on(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+ int ret = 0;
-+
-+ if (phy->vbus)
-+ ret = regulator_enable(phy->vbus);
-+
-+ return ret;
-+}
-+
-+static int sun4i_usb_phy_power_off(struct phy *_phy)
-+{
-+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
-+
-+ if (phy->vbus)
-+ regulator_disable(phy->vbus);
-+
-+ return 0;
-+}
-+
-+static struct phy_ops sun4i_usb_phy_ops = {
-+ .init = sun4i_usb_phy_init,
-+ .exit = sun4i_usb_phy_exit,
-+ .power_on = sun4i_usb_phy_power_on,
-+ .power_off = sun4i_usb_phy_power_off,
-+ .owner = THIS_MODULE,
-+};
-+
-+static struct phy *sun4i_usb_phy_xlate(struct device *dev,
-+ struct of_phandle_args *args)
-+{
-+ struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
-+
-+ if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
-+ return ERR_PTR(-ENODEV);
-+
-+ return data->phys[args->args[0]].phy;
-+}
-+
-+static int sun4i_usb_phy_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_usb_phy_data *data;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *np = dev->of_node;
-+ void __iomem *pmu = NULL;
-+ struct phy_provider *phy_provider;
-+ struct reset_control *reset;
-+ struct regulator *vbus;
-+ struct resource *res;
-+ struct phy *phy;
-+ char name[16];
-+ int i;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ mutex_init(&data->mutex);
-+
-+ if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
-+ data->num_phys = 2;
-+ else
-+ data->num_phys = 3;
-+
-+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
-+ data->disc_thresh = 3;
-+ else
-+ data->disc_thresh = 2;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
-+ data->base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(data->base))
-+ return PTR_ERR(data->base);
-+
-+ data->clk = devm_clk_get(dev, "usb_phy");
-+ if (IS_ERR(data->clk)) {
-+ dev_err(dev, "could not get usb_phy clock\n");
-+ return PTR_ERR(data->clk);
-+ }
-+
-+ /* Skip 0, 0 is the phy for otg which is not yet supported. */
-+ for (i = 1; i < data->num_phys; i++) {
-+ snprintf(name, sizeof(name), "usb%d_vbus", i);
-+ vbus = devm_regulator_get_optional(dev, name);
-+ if (IS_ERR(vbus)) {
-+ if (PTR_ERR(vbus) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
-+ vbus = NULL;
-+ }
-+
-+ snprintf(name, sizeof(name), "usb%d_reset", i);
-+ reset = devm_reset_control_get(dev, name);
-+ if (IS_ERR(reset)) {
-+ dev_err(dev, "failed to get reset %s\n", name);
-+ return PTR_ERR(phy);
-+ }
-+
-+ if (i) { /* No pmu for usbc0 */
-+ snprintf(name, sizeof(name), "pmu%d", i);
-+ res = platform_get_resource_byname(pdev,
-+ IORESOURCE_MEM, name);
-+ pmu = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(pmu))
-+ return PTR_ERR(pmu);
-+ }
-+
-+ phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
-+ if (IS_ERR(phy)) {
-+ dev_err(dev, "failed to create PHY %d\n", i);
-+ return PTR_ERR(phy);
-+ }
-+
-+ data->phys[i].phy = phy;
-+ data->phys[i].pmu = pmu;
-+ data->phys[i].vbus = vbus;
-+ data->phys[i].reset = reset;
-+ data->phys[i].index = i;
-+ phy_set_drvdata(phy, &data->phys[i]);
-+ }
-+
-+ dev_set_drvdata(dev, data);
-+ phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
-+ if (IS_ERR(phy_provider))
-+ return PTR_ERR(phy_provider);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_usb_phy_of_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-usb-phy" },
-+ { .compatible = "allwinner,sun5i-a13-usb-phy" },
-+ { .compatible = "allwinner,sun7i-a20-usb-phy" },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
-+
-+static struct platform_driver sun4i_usb_phy_driver = {
-+ .probe = sun4i_usb_phy_probe,
-+ .driver = {
-+ .of_match_table = sun4i_usb_phy_of_match,
-+ .name = "sun4i-usb-phy",
-+ .owner = THIS_MODULE,
-+ }
-+};
-+module_platform_driver(sun4i_usb_phy_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL v2");
---
-1.8.5.5
-
+++ /dev/null
-From a6ff9c88c09c81cb612f2588a5bfbde21bdcbf7b Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:58:47 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 1a9ab7e..7550c4e 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -307,6 +307,15 @@
- clock-output-names = "ir1";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
-+ };
-+
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From f1a981bd49f310775780c221fe92f6861c5e8f3f Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 00:30:04 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 7550c4e..80bbdeb 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -391,6 +391,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <64>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -399,6 +431,26 @@
- status = "disabled";
- };
-
-+ ehci1: usb@01c1c000 {
-+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
-+ reg = <0x01c1c000 0x100>;
-+ interrupts = <40>;
-+ clocks = <&ahb_gates 3>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
-+ reg = <0x01c1c400 0x100>;
-+ interrupts = <65>;
-+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From d2afb2629087ab17d87d605d4b7f49da3a85f1b1 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 22:45:06 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to cubieboard dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index ef85b8e..57d2c9c 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -13,6 +13,7 @@
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard";
-@@ -42,11 +43,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
---
-1.8.5.5
-
+++ /dev/null
-From dee94e49177c0bac675d543b16de0f354b0f476a Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Wed, 18 Sep 2013 00:30:40 +0200
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to Mele A1000 dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index 4b2a694..144b8e6 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Mele A1000";
-@@ -43,10 +44,32 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- emac_power_pin_a1000: emac_power_pin@0 {
- allwinner,pins = "PH15";
---
-1.8.5.5
-
+++ /dev/null
-From ebac8eac9b49c914a975c04a62ea5cfc058d958d Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:24:20 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index b58ce25..ed9b8cc 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -297,6 +297,15 @@
- clock-output-names = "ir1";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun4i-a10-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
-+ };
-+
- spi3_clk: clk@01c200d4 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From bc68c927139d1cac9647c8bcd3e8cea1cac9eaef Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:36:10 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index ed9b8cc..bdfa594 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -453,6 +453,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun7i-a20-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1", "pmu2";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>, <&usb_clk 2>;
-+ reset-names = "usb1_reset", "usb2_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <0 39 4>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <0 64 4>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -461,6 +493,26 @@
- status = "disabled";
- };
-
-+ ehci1: usb@01c1c000 {
-+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
-+ reg = <0x01c1c000 0x100>;
-+ interrupts = <0 40 4>;
-+ clocks = <&ahb_gates 3>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
-+ reg = <0x01c1c400 0x100>;
-+ interrupts = <0 65 4>;
-+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 5b820d3062a436cf36ddf2fecc88524b9adf7b6e Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Thu, 19 Sep 2013 21:29:45 +0200
-Subject: [PATCH] ARM: sun7i: dt: Add USB host nodes to cubieboard2 dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-index a8186f5..9fa1d85 100644
---- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubieboard2";
-@@ -28,11 +29,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- led_pins_cubieboard2: led_pins@0 {
- allwinner,pins = "PH20", "PH21";
---
-1.8.5.5
-
+++ /dev/null
-From 2f2ffd5ea0174434c8214722127e5e977dcecf32 Mon Sep 17 00:00:00 2001
-From: Zalan Blenessy <zalan.blenessy@gmail.com>
-Date: Sun, 22 Dec 2013 17:08:10 +0100
-Subject: [PATCH] ARM: sun7i: dt: Add USB host nodes to a20-olinuxino-micro dts
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index aef289f..824ce0a 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -14,6 +14,7 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
- #include <dt-bindings/input/input.h>
-
- / {
-@@ -37,11 +38,33 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
- allwinner,pins = "PH11";
---
-1.8.5.5
-
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/sun7i-a20-cubietruck.dts new/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
---- old/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-03-18 10:08:24.000000000 +0100
-+++ new/arch/arm/boot/dts/sun7i-a20-cubietruck.dts 2014-03-18 10:27:25.142067751 +0100
-@@ -14,12 +14,35 @@
- /dts-v1/;
- /include/ "sun7i-a20.dtsi"
- /include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "Cubietech Cubietruck";
- compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
-
- soc@01c00000 {
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
+++ /dev/null
-From 84e5402d6755b0563cfbe1b6b930b13b1c10d56c Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:02:39 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add bindings for USB clocks
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 9 +++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 9 +++++++++
- 2 files changed, 18 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 95cb245..0565040 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -268,6 +268,15 @@
- clock-output-names = "ir0";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_phy";
-+ };
-+
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index bae0f5f..785dea5 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -266,6 +266,15 @@
- clock-output-names = "ir0";
- };
-
-+ usb_clk: clk@01c200cc {
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-clk";
-+ reg = <0x01c200cc 0x4>;
-+ clocks = <&pll6 1>;
-+ clock-output-names = "usb_ohci0", "usb_phy";
-+ };
-+
- mbus_clk: clk@01c2015c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-mod0-clk";
---
-1.8.5.5
-
+++ /dev/null
-From 22f661c548042565ffa32e468267f94cadafe144 Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:03:40 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add USB host bindings
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 32 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/sun5i-a13.dtsi | 32 ++++++++++++++++++++++++++++++++
- 2 files changed, 64 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 0565040..a5431ed 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -341,6 +341,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>;
-+ reset-names = "usb1_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <40>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 785dea5..7fe9cdc 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -312,6 +312,38 @@
- status = "disabled";
- };
-
-+ usbphy: phy@01c13400 {
-+ #phy-cells = <1>;
-+ compatible = "allwinner,sun5i-a13-usb-phy";
-+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
-+ reg-names = "phy_ctrl", "pmu1";
-+ clocks = <&usb_clk 8>;
-+ clock-names = "usb_phy";
-+ resets = <&usb_clk 1>;
-+ reset-names = "usb1_reset";
-+ status = "disabled";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
-+ reg = <0x01c14000 0x100>;
-+ interrupts = <39>;
-+ clocks = <&ahb_gates 1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
-+ reg = <0x01c14400 0x100>;
-+ interrupts = <40>;
-+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From 8bf60620f751f93157c81038527b03716c8aeede Mon Sep 17 00:00:00 2001
-From: Roman Byshko <rbyshko@gmail.com>
-Date: Tue, 24 Sep 2013 20:07:53 +0200
-Subject: [PATCH] ARM: sun5i: dt: Add USB host nodes to A13-Olinuxino
-
-Add nodes for the usb-phy and ehci- and ohci-usb-host controllers.
-
-Signed-off-by: Roman Byshko <rbyshko@gmail.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-index ba32a41..39556d1 100644
---- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
-@@ -13,6 +13,7 @@
-
- /dts-v1/;
- /include/ "sun5i-a13.dtsi"
-+/include/ "sun5i-a13-usb-vbus-reg.dtsi"
- #include <dt-bindings/input/input.h>
-
- / {
-@@ -28,6 +29,19 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
- pinctrl@01c20800 {
- mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
-@@ -42,6 +56,13 @@
- allwinner,drive = <1>;
- allwinner,pull = <0>;
- };
-+
-+ usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
-+ allwinner,pins = "PG11";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- lradc: lradc@01c22800 {
-@@ -86,4 +107,9 @@
- default-state = "on";
- };
- };
-+
-+ reg_usb1_vbus: usb1-vbus {
-+ pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
-+ gpio = <&pio 6 11 0>;
-+ };
- };
---
-1.8.5.5
-
+++ /dev/null
-From d46cebc1431948638fe4e6cfd27fb9da48e6c593 Mon Sep 17 00:00:00 2001
-From: Zalan Blenessy <zalan.blenessy@gmail.com>
-Date: Sun, 22 Dec 2013 17:10:06 +0100
-Subject: [PATCH] ARM: sunxi: select ARM_PSCI
-
-This is necessary for SMP on sun7i.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/mach-sunxi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -3,6 +3,7 @@ config ARCH_SUNXI
- select ARCH_HAS_RESET_CONTROLLER
- select ARCH_REQUIRE_GPIOLIB
- select ARM_GIC
-+ select ARM_PSCI
- select CLKSRC_MMIO
- select CLKSRC_OF
- select COMMON_CLK
+++ /dev/null
-From 99489f45debd07f6e1cfa36f5c9890409714518d Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:08 +0100
-Subject: [PATCH] clocksource: sun5i: Add support for reset controller
-
-The Allwinner A31 that uses this timer has the timer IP asserted in reset.
-Add an optional reset property to the DT, and deassert the timer from reset if
-it's there.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt | 4 ++++
- drivers/clocksource/timer-sun5i.c | 6 ++++++
- 2 files changed, 10 insertions(+)
-
---- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-@@ -9,6 +9,9 @@ Required properties:
- one)
- - clocks: phandle to the source clock (usually the AHB clock)
-
-+Optionnal properties:
-+- resets: phandle to a reset controller asserting the timer
-+
- Example:
-
- timer@01c60000 {
-@@ -19,4 +22,5 @@ timer@01c60000 {
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
-+ resets = <&ahb1rst 19>;
- };
---- a/drivers/clocksource/timer-sun5i.c
-+++ b/drivers/clocksource/timer-sun5i.c
-@@ -16,6 +16,7 @@
- #include <linux/interrupt.h>
- #include <linux/irq.h>
- #include <linux/irqreturn.h>
-+#include <linux/reset.h>
- #include <linux/sched_clock.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-@@ -143,6 +144,7 @@ static u32 sun5i_timer_sched_read(void)
-
- static void __init sun5i_timer_init(struct device_node *node)
- {
-+ struct reset_control *rstc;
- unsigned long rate;
- struct clk *clk;
- int ret, irq;
-@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(stru
- clk_prepare_enable(clk);
- rate = clk_get_rate(clk);
-
-+ rstc = of_reset_control_get(node, NULL);
-+ if (!IS_ERR(rstc))
-+ reset_control_deassert(rstc);
-+
- writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
- writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
- timer_base + TIMER_CTL_REG(1));
+++ /dev/null
-From 0325b48d6149e131c90ed6ec77458f4d2df73898 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:07 +0100
-Subject: [PATCH] reset: Add of_reset_control_get
-
-In some cases, you might need to deassert from reset an hardware block that
-doesn't associated to a struct device (CPUs, timers, etc.).
-
-Add a small helper to retrieve the reset controller from the device tree
-without the need to pass a struct device.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/reset/core.c | 39 ++++++++++++++++++++++++++++++---------
- include/linux/reset.h | 4 ++++
- 2 files changed, 34 insertions(+), 9 deletions(-)
-
---- a/drivers/reset/core.c
-+++ b/drivers/reset/core.c
-@@ -127,15 +127,16 @@ int reset_control_deassert(struct reset_
- EXPORT_SYMBOL_GPL(reset_control_deassert);
-
- /**
-- * reset_control_get - Lookup and obtain a reference to a reset controller.
-- * @dev: device to be reset by the controller
-+ * of_reset_control_get - Lookup and obtain a reference to a reset controller.
-+ * @node: device to be reset by the controller
- * @id: reset line name
- *
- * Returns a struct reset_control or IS_ERR() condition containing errno.
- *
- * Use of id names is optional.
- */
--struct reset_control *reset_control_get(struct device *dev, const char *id)
-+struct reset_control *of_reset_control_get(struct device_node *node,
-+ const char *id)
- {
- struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER);
- struct reset_controller_dev *r, *rcdev;
-@@ -144,13 +145,10 @@ struct reset_control *reset_control_get(
- int rstc_id;
- int ret;
-
-- if (!dev)
-- return ERR_PTR(-EINVAL);
--
- if (id)
-- index = of_property_match_string(dev->of_node,
-+ index = of_property_match_string(node,
- "reset-names", id);
-- ret = of_parse_phandle_with_args(dev->of_node, "resets", "#reset-cells",
-+ ret = of_parse_phandle_with_args(node, "resets", "#reset-cells",
- index, &args);
- if (ret)
- return ERR_PTR(ret);
-@@ -185,12 +183,35 @@ struct reset_control *reset_control_get(
- return ERR_PTR(-ENOMEM);
- }
-
-- rstc->dev = dev;
- rstc->rcdev = rcdev;
- rstc->id = rstc_id;
-
- return rstc;
- }
-+EXPORT_SYMBOL_GPL(of_reset_control_get);
-+
-+/**
-+ * reset_control_get - Lookup and obtain a reference to a reset controller.
-+ * @dev: device to be reset by the controller
-+ * @id: reset line name
-+ *
-+ * Returns a struct reset_control or IS_ERR() condition containing errno.
-+ *
-+ * Use of id names is optional.
-+ */
-+struct reset_control *reset_control_get(struct device *dev, const char *id)
-+{
-+ struct reset_control *rstc;
-+
-+ if (!dev)
-+ return ERR_PTR(-EINVAL);
-+
-+ rstc = of_reset_control_get(dev->of_node, id);
-+ if (!IS_ERR(rstc))
-+ rstc->dev = dev;
-+
-+ return rstc;
-+}
- EXPORT_SYMBOL_GPL(reset_control_get);
-
- /**
---- a/include/linux/reset.h
-+++ b/include/linux/reset.h
-@@ -1,6 +1,8 @@
- #ifndef _LINUX_RESET_H_
- #define _LINUX_RESET_H_
-
-+#include <linux/of.h>
-+
- struct device;
- struct reset_control;
-
-@@ -8,6 +10,8 @@ int reset_control_reset(struct reset_con
- int reset_control_assert(struct reset_control *rstc);
- int reset_control_deassert(struct reset_control *rstc);
-
-+struct reset_control *of_reset_control_get(struct device_node *node,
-+ const char *id);
- struct reset_control *reset_control_get(struct device *dev, const char *id);
- void reset_control_put(struct reset_control *rstc);
- struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
+++ /dev/null
-From a1c859ab115c043662c2779d2e965bb09a90b8cb Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Tue, 17 Dec 2013 23:57:24 +0100
-Subject: [PATCH] ARM: sunxi-clock-reset: rename compat property
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++--
- drivers/reset/reset-sunxi.c | 2 +-
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -220,13 +220,13 @@
-
- apb1_rst: reset@01c202d0 {
- #reset-cells = <1>;
-- compatible = "allwinner,sun6i-a31-clock-reset";
-+ compatible = "allwinner,sun4i-clock-reset";
- reg = <0x01c202d0 0x4>;
- };
-
- apb2_rst: reset@01c202d8 {
- #reset-cells = <1>;
-- compatible = "allwinner,sun6i-a31-clock-reset";
-+ compatible = "allwinner,sun4i-clock-reset";
- reg = <0x01c202d8 0x4>;
- };
-
---- a/drivers/reset/reset-sunxi.c
-+++ b/drivers/reset/reset-sunxi.c
-@@ -138,7 +138,7 @@ void __init sun6i_reset_init(void)
- * device model.
- */
- static const struct of_device_id sunxi_reset_dt_ids[] = {
-- { .compatible = "allwinner,sun6i-a31-clock-reset", },
-+ { .compatible = "allwinner,sun4i-clock-reset", },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
+++ /dev/null
-From 5ca9eadcb5f5cd9af6f1650029ad64052a1a0b10 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:17 +0800
-Subject: [PATCH] clk: sunxi: Allwinner A20 output clock support
-
-This patch adds support for the external clock outputs on the
-Allwinner A20 SoC. The clock outputs are similar to "module 0"
-type clocks, with different offsets and widths for clock factors.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
- drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
- 2 files changed, 58 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -37,6 +37,7 @@ Required properties:
- "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
- "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
-+ "allwinner,sun7i-a20-out-clk" - for the external output clocks
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct
-
-
- /**
-+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
-+ * CLK_OUT rate is calculated as follows
-+ * rate = (parent_rate >> p) / (m + 1);
-+ */
-+
-+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div, calcm, calcp;
-+
-+ /* These clocks can only divide, so we will never be able to achieve
-+ * frequencies higher than the parent frequency */
-+ if (*freq > parent_rate)
-+ *freq = parent_rate;
-+
-+ div = parent_rate / *freq;
-+
-+ if (div < 32)
-+ calcp = 0;
-+ else if (div / 2 < 32)
-+ calcp = 1;
-+ else if (div / 4 < 32)
-+ calcp = 2;
-+ else
-+ calcp = 3;
-+
-+ calcm = DIV_ROUND_UP(div, 1 << calcp);
-+
-+ *freq = (parent_rate >> calcp) / calcm;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *m = calcm - 1;
-+ *p = calcp;
-+}
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
-@@ -455,6 +496,14 @@ static struct clk_factors_config sun4i_m
- .pwidth = 2,
- };
-
-+/* user manual says "n" but it's really "p" */
-+static struct clk_factors_config sun7i_a20_out_config = {
-+ .mshift = 8,
-+ .mwidth = 5,
-+ .pshift = 20,
-+ .pwidth = 2,
-+};
-+
- static const struct factors_data sun4i_pll1_data __initconst = {
- .enable = 31,
- .table = &sun4i_pll1_config,
-@@ -491,6 +540,13 @@ static const struct factors_data sun4i_m
- .getter = sun4i_get_mod0_factors,
- };
-
-+static const struct factors_data sun7i_a20_out_data __initconst = {
-+ .enable = 31,
-+ .mux = 24,
-+ .table = &sun7i_a20_out_config,
-+ .getter = sun7i_a20_get_out_factors,
-+};
-+
- static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- const struct factors_data *data)
- {
-@@ -998,6 +1054,7 @@ static const struct of_device_id clk_fac
- {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
- {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
-+ {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
- {}
- };
-
+++ /dev/null
-From 271a35ef6237c3b775aad357969dc75ae5b56988 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:19 +0800
-Subject: [PATCH] pinctrl: sunxi: Add Allwinner A20 clock output pin functions
-
-This patch adds the clock output pin functions on the A20.
-The 2 pins can output a configurable clock to be used by
-external modules. This is used on the CubieTruck, to supply
-a 32768 Hz low power clock to the onboard Wifi+BT module.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- drivers/pinctrl/pinctrl-sunxi-pins.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/pinctrl-sunxi-pins.h
-+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
-@@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
- SUNXI_FUNCTION(0x3, "uart6"), /* TX */
-+ SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
- SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
- SUNXI_FUNCTION(0x3, "uart6"), /* RX */
-+ SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
- SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
- SUNXI_FUNCTION(0x0, "gpio_in"),
+++ /dev/null
-From f3a50c26f33a4627e5d3e35f80db3f22a5375237 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 24 Dec 2013 21:26:20 +0800
-Subject: [PATCH] ARM: dts: sun7i: Add pin muxing options for clock outputs
-
-This patch adds the clock output pin options on the A20.
-The 2 pins can output a configurable clock to be used by
-external modules. This is used on the CubieTruck, to supply
-a 32768 Hz low power clock to the onboard Wifi+BT module.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -490,6 +490,20 @@
- allwinner,drive = <3>;
- allwinner,pull = <0>;
- };
-+
-+ clk_out_a_pins: clk_out_a@0 {
-+ allwinner,pins = "PI12";
-+ allwinner,function = "clk_out_a";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ clk_out_b_pins: clk_out_b@0 {
-+ allwinner,pins = "PI13";
-+ allwinner,function = "clk_out_b";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- sata: ahci@01c18000 {
+++ /dev/null
-From 10b302a297aee952949423aaec0749b757f34950 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 17 Nov 2013 10:03:04 +0100
-Subject: [PATCH] ARM: sun4i: dt: Move the aliases to the DTSI
-
-The aliases are shared across boards are really belong to the DTSI.
-Move them there.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ----
- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 5 -----
- arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
- 3 files changed, 2 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-index eb4d73b..d4b081d 100644
---- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
-@@ -18,10 +18,6 @@
- model = "Mele A1000";
- compatible = "mele,a1000", "allwinner,sun4i-a10";
-
-- aliases {
-- serial0 = &uart0;
-- };
--
- soc@01c00000 {
- emac: ethernet@01c0b000 {
- pinctrl-names = "default";
-diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-index 425a7db..f1c77e0 100644
---- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
-@@ -17,11 +17,6 @@
- model = "Cubietech Cubieboard";
- compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
-
-- aliases {
-- serial0 = &uart0;
-- serial1 = &uart1;
-- };
--
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- };
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 3ba2b46..0adbbe3 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -17,6 +17,8 @@
-
- aliases {
- ethernet0 = &emac;
-+ serial0 = &uart0;
-+ serial1 = &uart1;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 4dae1686782d52084893421b89ff1aa61e223aaf Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:11 +0100
-Subject: [PATCH] net: ethernet: sunxi: Add new compatibles
-
-The Allwinner A10 compatibles were following a slightly different compatible
-patterns than the rest of the SoCs for historical reasons. Add compatibles
-matching the other pattern to the ethernet driver for consistency, and keep the
-older one for backward compatibility.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt | 5 +++--
- drivers/net/ethernet/allwinner/sun4i-emac.c | 3 +++
- 2 files changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-index b90bfcd..863d5b81 100644
---- a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
-@@ -1,7 +1,8 @@
- * Allwinner EMAC ethernet controller
-
- Required properties:
--- compatible: should be "allwinner,sun4i-emac".
-+- compatible: should be "allwinner,sun4i-a10-emac" (Deprecated:
-+ "allwinner,sun4i-emac")
- - reg: address and length of the register set for the device.
- - interrupts: interrupt for the device
- - phy: A phandle to a phy node defining the PHY address (as the reg
-@@ -14,7 +15,7 @@ Optional properties:
- Example:
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c b/drivers/net/ethernet/allwinner/sun4i-emac.c
-index 0cc2143..511f6ee 100644
---- a/drivers/net/ethernet/allwinner/sun4i-emac.c
-+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c
-@@ -929,6 +929,9 @@ static int emac_resume(struct platform_device *dev)
- }
-
- static const struct of_device_id emac_of_match[] = {
-+ {.compatible = "allwinner,sun4i-a10-emac",},
-+
-+ /* Deprecated */
- {.compatible = "allwinner,sun4i-emac",},
- {},
- };
---
-1.8.5.5
-
+++ /dev/null
-From efe205704fa8435b7bca495138dd2dbd973e0c28 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:12 +0100
-Subject: [PATCH] net: phy: sunxi: Add new compatibles
-
-The Allwinner A10 compatibles were following a slightly different compatible
-patterns than the rest of the SoCs for historical reasons. Add compatibles
-matching the other pattern to the mdio driver for consistency, and keep the
-older one for backward compatibility.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt | 5 +++--
- drivers/net/phy/mdio-sun4i.c | 3 +++
- 2 files changed, 6 insertions(+), 2 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-index 00b9f9a..4ec5641 100644
---- a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
-@@ -1,7 +1,8 @@
- * Allwinner A10 MDIO Ethernet Controller interface
-
- Required properties:
--- compatible: should be "allwinner,sun4i-mdio".
-+- compatible: should be "allwinner,sun4i-a10-mdio"
-+ (Deprecated: "allwinner,sun4i-mdio").
- - reg: address and length of the register set for the device.
-
- Optional properties:
-@@ -9,7 +10,7 @@ Optional properties:
-
- Example at the SoC level:
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- #address-cells = <1>;
- #size-cells = <0>;
-diff --git a/drivers/net/phy/mdio-sun4i.c b/drivers/net/phy/mdio-sun4i.c
-index bb88bc7..9367acc 100644
---- a/drivers/net/phy/mdio-sun4i.c
-+++ b/drivers/net/phy/mdio-sun4i.c
-@@ -170,6 +170,9 @@ static int sun4i_mdio_remove(struct platform_device *pdev)
- }
-
- static const struct of_device_id sun4i_mdio_dt_ids[] = {
-+ { .compatible = "allwinner,sun4i-a10-mdio" },
-+
-+ /* Deprecated */
- { .compatible = "allwinner,sun4i-mdio" },
- { }
- };
---
-1.8.5.5
-
+++ /dev/null
-From 1c70e099ac80ee779ffac66a6169ad936425fe41 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:49:13 +0100
-Subject: [PATCH] ARM: sunxi: dt: Convert to the new net compatibles
-
-Switch the device tree to the new compatibles introduced in the ethernet and
-mdio drivers to have a common pattern accross all Allwinner SoCs.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++--
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 040bb0e..10666ca 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -315,7 +315,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-@@ -323,7 +323,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index ea16054..6496159 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -278,7 +278,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <55>;
- clocks = <&ahb_gates 17>;
-@@ -286,7 +286,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 119f066..9ff0948 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -340,7 +340,7 @@
- ranges;
-
- emac: ethernet@01c0b000 {
-- compatible = "allwinner,sun4i-emac";
-+ compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
- interrupts = <0 55 4>;
- clocks = <&ahb_gates 17>;
-@@ -348,7 +348,7 @@
- };
-
- mdio@01c0b080 {
-- compatible = "allwinner,sun4i-mdio";
-+ compatible = "allwinner,sun4i-a10-mdio";
- reg = <0x01c0b080 0x14>;
- status = "disabled";
- #address-cells = <1>;
---
-1.8.5.5
-
+++ /dev/null
-From 791f631bb8f3feb10871b82015a25a7f40ce68e7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun4i: a10: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 10666ca..d9c097c 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -19,6 +19,12 @@
- ethernet0 = &emac;
- serial0 = &uart0;
- serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ serial6 = &uart6;
-+ serial7 = &uart7;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 64c3866d232e6b29862f4773ea97b16f4dad6950 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun5i: a10s: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index 6496159..e00f292 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -18,6 +18,10 @@
-
- aliases {
- ethernet0 = &emac;
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
- };
-
- cpus {
---
-1.8.5.5
-
+++ /dev/null
-From 0cc774ef2524ec54e9d2db8771ba3739cb8ebc99 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 13 Jan 2014 11:08:47 +0100
-Subject: [PATCH] ARM: sun5i: a13: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 320335a..6de40b6 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -16,6 +16,11 @@
- / {
- interrupt-parent = <&intc>;
-
-+ aliases {
-+ serial0 = &uart1;
-+ serial1 = &uart3;
-+ };
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---
-1.8.5.5
-
+++ /dev/null
-From 27fb9d199aa3d2f89b4d0b1930062bb1a5a69a57 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Thu, 2 Jan 2014 22:05:04 +0100
-Subject: [PATCH] ARM: sun6i: Add missing serial aliases
-
-Some UART aliases have been defined, but not all of them. Add the remaining
-ones to be consistent and to ease the parsing of the DT by the bootloaders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index 5256ad9..092bf97 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -16,6 +16,16 @@
- / {
- interrupt-parent = <&gic>;
-
-+ aliases {
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ serial2 = &uart2;
-+ serial3 = &uart3;
-+ serial4 = &uart4;
-+ serial5 = &uart5;
-+ };
-+
-+
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
---
-1.8.5.5
-
+++ /dev/null
-From 4261ec43b199a214f6b0ae5fefefff2e524f8977 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Tue, 14 Jan 2014 22:49:50 +0800
-Subject: [PATCH] ARM: dts: sun7i: add pin muxing options for UART2
-
-UART2 is used on CubieTruck to connect to the Bluetooth module.
-Add the pin set used in this case.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index b476855..bfb2cf2 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -381,6 +381,13 @@
- allwinner,pull = <0>;
- };
-
-+ uart2_pins_a: uart2@0 {
-+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-+ allwinner,function = "uart2";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
- uart6_pins_a: uart6@0 {
- allwinner,pins = "PI12", "PI13";
- allwinner,function = "uart6";
---
-1.8.5.5
-
+++ /dev/null
-From 97e36b3ce3106988b82e1ca53b1d1c872bde855a Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:40 +0800
-Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
- clock
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Divs clocks consist of a parent factor clock with multiple outputs,
-and seperate clocks for each output. Get the name of the parent
-clock from the parent factor clock, instead of the DT node name.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 7a2ed98..736fb60 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -869,7 +869,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- struct divs_data *data)
- {
- struct clk_onecell_data *clk_data;
-- const char *parent = node->name;
-+ const char *parent;
- const char *clk_name;
- struct clk **clks, *pclk;
- struct clk_hw *gate_hw, *rate_hw;
-@@ -883,6 +883,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
-
- /* Set up factor clock that we will be dividing */
- pclk = sunxi_factors_clk_setup(node, data->factors);
-+ parent = __clk_get_name(pclk);
-
- reg = of_iomap(node, 0);
-
---
-1.8.5.5
-
+++ /dev/null
-From f64111ebaf6776558f0e60d0ea8c7a9c579b9436 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:37 +0800
-Subject: [PATCH] clk: sunxi: add clock-output-names dt property support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-sunxi clock drivers use dt node name as clock name, but clock
-nodes should be named clk@X, so the names would be the same.
-Let the drivers read clock names from dt clock-output-names
-property.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index abb6c5a..0ed9794 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -51,6 +51,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
- if (!gate)
- goto err_free_fixed;
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- /* set up gate and fixed rate properties */
- gate->reg = of_iomap(node, 0);
- gate->bit_idx = SUNXI_OSC24M_GATE;
-@@ -601,6 +603,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- clk = clk_register_mux(NULL, clk_name, parents, i,
- CLK_SET_RATE_NO_REPARENT, reg,
- data->shift, SUNXI_MUX_GATE_WIDTH,
-@@ -660,6 +664,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-+
- clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
- reg, data->shift, data->width,
- data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
---
-1.8.5.5
-
+++ /dev/null
-From 667f542db542fddc62d1299b17451d7cae84f6e1 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 3 Feb 2014 09:51:39 +0800
-Subject: [PATCH] clk: sunxi: add names for pll5, pll6 parent clocks to
- factors_data
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Some factor clocks, such as the parent clock of pll5 and pll6, have
-multiple output names. Add the corresponding names to factors_data
-tied to compatible string.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Acked-by: Mike Turquette <mturquette@linaro.org>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 27 ++++++++++++++++++---------
- 1 file changed, 18 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 0ed9794..7a2ed98 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -389,6 +389,7 @@ struct factors_data {
- int mux;
- struct clk_factors_config *table;
- void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
-+ const char *name;
- };
-
- static struct clk_factors_config sun4i_pll1_config = {
-@@ -457,6 +458,14 @@ struct factors_data {
- .enable = 31,
- .table = &sun4i_pll5_config,
- .getter = sun4i_get_pll5_factors,
-+ .name = "pll5",
-+};
-+
-+static const struct factors_data sun4i_pll6_data __initconst = {
-+ .enable = 31,
-+ .table = &sun4i_pll5_config,
-+ .getter = sun4i_get_pll5_factors,
-+ .name = "pll6",
- };
-
- static const struct factors_data sun4i_apb1_data __initconst = {
-@@ -499,14 +508,14 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
- (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
- i++;
-
-- /* Nodes should be providing the name via clock-output-names
-- * but originally our dts didn't, and so we used node->name.
-- * The new, better nodes look like clk@deadbeef, so we pull the
-- * name just in this case */
-- if (!strcmp("clk", clk_name)) {
-- of_property_read_string_index(node, "clock-output-names",
-- 0, &clk_name);
-- }
-+ /*
-+ * some factor clocks, such as pll5 and pll6, may have multiple
-+ * outputs, and have their name designated in factors_data
-+ */
-+ if (data->name)
-+ clk_name = data->name;
-+ else
-+ of_property_read_string(node, "clock-output-names", &clk_name);
-
- factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
- if (!factors)
-@@ -838,7 +847,7 @@ struct divs_data {
- };
-
- static const struct divs_data pll6_divs_data __initconst = {
-- .factors = &sun4i_pll5_data,
-+ .factors = &sun4i_pll6_data,
- .div = {
- { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
- { .fixed = 2 }, /* P, other */
---
-1.8.5.5
-
+++ /dev/null
-From 967f938d4b16233fd7596e94803a36161847c6a8 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Mon, 10 Feb 2014 18:35:47 +0800
-Subject: [PATCH] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
-
-The Allwinner A20/A31 clock module controls the transmit clock source
-and interface type of the GMAC ethernet controller. Model this as
-a single clock for GMAC drivers to use.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++++++
- drivers/clk/sunxi/clk-sunxi.c | 96 +++++++++++++++++++++++
- 2 files changed, 126 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index 93d003c..0da774c 100644
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -37,6 +37,7 @@ Required properties:
- "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
- "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
- "allwinner,sun7i-a20-out-clk" - for the external output clocks
-+ "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
-
- Required properties for all clocks:
- - reg : shall be the control register address for the clock.
-@@ -50,6 +51,9 @@ Required properties for all clocks:
- If the clock module only has one output, the name shall be the
- module name.
-
-+For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
-+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
-+
- Clock consumers should specify the desired clocks they use with a
- "clocks" phandle cell. Consumers that are using a gated clock should
- provide an additional ID in their clock property. This ID is the
-@@ -96,3 +100,29 @@ mmc0_clk: clk@01c20088 {
- clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0";
- };
-+
-+mii_phy_tx_clk: clk@2 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <25000000>;
-+ clock-output-names = "mii_phy_tx";
-+};
-+
-+gmac_int_tx_clk: clk@3 {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_int_tx";
-+};
-+
-+gmac_clk: clk@01c20164 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun7i-a20-gmac-clk";
-+ reg = <0x01c20164 0x4>;
-+ /*
-+ * The first clock must be fixed at 25MHz;
-+ * the second clock must be fixed at 125MHz
-+ */
-+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
-+ clock-output-names = "gmac";
-+};
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 0dce6fd..3283179 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -404,6 +404,102 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
-
-
- /**
-+ * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
-+ *
-+ * This clock looks something like this
-+ * ________________________
-+ * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
-+ * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
-+ * Ext. 125MHz RGMII TX clk >--|__divider__/ |
-+ * |________________________|
-+ *
-+ * The external 125 MHz reference is optional, i.e. GMAC can use its
-+ * internal TX clock just fine. The A31 GMAC clock module does not have
-+ * the divider controls for the external reference.
-+ *
-+ * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
-+ * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
-+ * select the appropriate source and gate/ungate the output to the PHY.
-+ *
-+ * Only the GMAC should use this clock. Altering the clock so that it doesn't
-+ * match the GMAC's operation parameters will result in the GMAC not being
-+ * able to send traffic out. The GMAC driver should set the clock rate and
-+ * enable/disable this clock to configure the required state. The clock
-+ * driver then responds by auto-reparenting the clock.
-+ */
-+
-+#define SUN7I_A20_GMAC_GPIT 2
-+#define SUN7I_A20_GMAC_MASK 0x3
-+#define SUN7I_A20_GMAC_PARENTS 2
-+
-+static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
-+{
-+ struct clk *clk;
-+ struct clk_mux *mux;
-+ struct clk_gate *gate;
-+ const char *clk_name = node->name;
-+ const char *parents[SUN7I_A20_GMAC_PARENTS];
-+ void *reg;
-+
-+ if (of_property_read_string(node, "clock-output-names", &clk_name))
-+ return;
-+
-+ /* allocate mux and gate clock structs */
-+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
-+ if (!mux)
-+ return;
-+
-+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
-+ if (!gate)
-+ goto free_mux;
-+
-+ /* gmac clock requires exactly 2 parents */
-+ parents[0] = of_clk_get_parent_name(node, 0);
-+ parents[1] = of_clk_get_parent_name(node, 1);
-+ if (!parents[0] || !parents[1])
-+ goto free_gate;
-+
-+ reg = of_iomap(node, 0);
-+ if (!reg)
-+ goto free_gate;
-+
-+ /* set up gate and fixed rate properties */
-+ gate->reg = reg;
-+ gate->bit_idx = SUN7I_A20_GMAC_GPIT;
-+ gate->lock = &clk_lock;
-+ mux->reg = reg;
-+ mux->mask = SUN7I_A20_GMAC_MASK;
-+ mux->flags = CLK_MUX_INDEX_BIT;
-+ mux->lock = &clk_lock;
-+
-+ clk = clk_register_composite(NULL, clk_name,
-+ parents, SUN7I_A20_GMAC_PARENTS,
-+ &mux->hw, &clk_mux_ops,
-+ NULL, NULL,
-+ &gate->hw, &clk_gate_ops,
-+ 0);
-+
-+ if (IS_ERR(clk))
-+ goto iounmap_reg;
-+
-+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
-+ clk_register_clkdev(clk, clk_name, NULL);
-+
-+ return;
-+
-+iounmap_reg:
-+ iounmap(reg);
-+free_gate:
-+ kfree(gate);
-+free_mux:
-+ kfree(mux);
-+}
-+CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
-+ sun7i_a20_gmac_clk_setup);
-+
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
---
-1.8.5.5
-
+++ /dev/null
-From 673fac742946bcb7cc43b9e67459862d6c4a8a6c Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wens@csie.org>
-Date: Wed, 1 Jan 2014 10:30:47 +0800
-Subject: [PATCH] ARM: dts: sun7i: Change 32768 Hz oscillator node name to
- clk@N style
-
-Device tree naming conventions state that node names should match
-the nodes function. Change external low speed oscillator node name
-to match.
-
-Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 898b021..edad6f1 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -53,10 +53,11 @@
- clock-frequency = <24000000>;
- };
-
-- osc32k: osc32k {
-+ osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
-+ clock-output-names = "osc32k";
- };
-
- pll1: pll1@01c20000 {
---
-1.8.5.5
-
+++ /dev/null
-From 92ef67c53ad92487c3c8de75e7940384c2edd793 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:03 +0100
-Subject: [PATCH] clk: sunxi: Add support for PLL6 on the A31
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The A31 has a slightly different PLL6 clock. Add support for this new clock in
-our driver.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
- drivers/clk/sunxi/clk-sunxi.c | 45 +++++++++++++++++++++++
- 2 files changed, 46 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index ca2b692..c37c764 100644
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -11,6 +11,7 @@ Required properties:
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
- "allwinner,sun4i-pll5-clk" - for the PLL5 clock
- "allwinner,sun4i-pll6-clk" - for the PLL6 clock
-+ "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
- "allwinner,sun4i-axi-gates-clk" - for the AXI gates
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index a779c31..d4cf297 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -252,7 +252,38 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
- *n = DIV_ROUND_UP(div, (*k+1));
- }
-
-+/**
-+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
-+ * PLL6 rate is calculated as follows
-+ * rate = parent_rate * n * (k + 1) / 2
-+ * parent_rate is always 24Mhz
-+ */
-+
-+static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
-+ u8 *n, u8 *k, u8 *m, u8 *p)
-+{
-+ u8 div;
-+
-+ /*
-+ * We always have 24MHz / 2, so we can just say that our
-+ * parent clock is 12MHz.
-+ */
-+ parent_rate = parent_rate / 2;
-+
-+ /* Normalize value to a parent_rate multiple (24M / 2) */
-+ div = *freq / parent_rate;
-+ *freq = parent_rate * div;
-+
-+ /* we were called to round the frequency, we can now return */
-+ if (n == NULL)
-+ return;
-+
-+ *k = div / 32;
-+ if (*k > 3)
-+ *k = 3;
-
-+ *n = DIV_ROUND_UP(div, (*k+1));
-+}
-
- /**
- * sun4i_get_apb1_factors() - calculates m, p factors for APB1
-@@ -420,6 +451,13 @@ struct factors_data {
- .kwidth = 2,
- };
-
-+static struct clk_factors_config sun6i_a31_pll6_config = {
-+ .nshift = 8,
-+ .nwidth = 5,
-+ .kshift = 4,
-+ .kwidth = 2,
-+};
-+
- static struct clk_factors_config sun4i_apb1_config = {
- .mshift = 0,
- .mwidth = 5,
-@@ -469,6 +507,12 @@ struct factors_data {
- .name = "pll6",
- };
-
-+static const struct factors_data sun6i_a31_pll6_data __initconst = {
-+ .enable = 31,
-+ .table = &sun6i_a31_pll6_config,
-+ .getter = sun6i_a31_get_pll6_factors,
-+};
-+
- static const struct factors_data sun4i_apb1_data __initconst = {
- .table = &sun4i_apb1_config,
- .getter = sun4i_get_apb1_factors,
-@@ -1069,6 +1113,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
- static const struct of_device_id clk_factors_match[] __initconst = {
- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
- {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
-+ {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
- {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
- {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
---
-1.8.5.5
-
+++ /dev/null
-From 3558fe900e8af6c3bfadeff24a12ffb19ac9b108 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:05 +0100
-Subject: [PATCH 1/2] spi: sunxi: Add Allwinner A31 SPI controller driver
-
-The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
-SoCs.
-
-It supports DMA, but the driver only does PIO for now, and DMA will be
-supported eventually.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- .../devicetree/bindings/spi/spi-sun6i.txt | 24 +
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-sun6i.c | 483 +++++++++++++++++++++
- 4 files changed, 514 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
- create mode 100644 drivers/spi/spi-sun6i.c
-
-diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
-new file mode 100644
-index 0000000..21de73d
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
-@@ -0,0 +1,24 @@
-+Allwinner A31 SPI controller
-+
-+Required properties:
-+- compatible: Should be "allwinner,sun6i-a31-spi".
-+- reg: Should contain register location and length.
-+- interrupts: Should contain interrupt.
-+- clocks: phandle to the clocks feeding the SPI controller. Two are
-+ needed:
-+ - "ahb": the gated AHB parent clock
-+ - "mod": the parent module clock
-+- clock-names: Must contain the clock names described just above
-+- resets: phandle to the reset controller asserting this device in
-+ reset
-+
-+Example:
-+
-+spi1: spi@01c69000 {
-+ compatible = "allwinner,sun6i-a31-spi";
-+ reg = <0x01c69000 0x1000>;
-+ interrupts = <0 66 4>;
-+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ resets = <&ahb1_rst 21>;
-+};
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index ba9310b..7cfe0ee 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -446,6 +446,12 @@ config SPI_SIRF
- help
- SPI driver for CSR SiRFprimaII SoCs
-
-+config SPI_SUN6I
-+ tristate "Allwinner A31 SPI controller"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ This enables using the SPI controller on the Allwinner A31 SoCs.
-+
- config SPI_MXS
- tristate "Freescale MXS SPI controller"
- depends on ARCH_MXS
-diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
-index 95af48d..13b6ccf 100644
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
- obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
- obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
- obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
-+obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
- obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
- obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
- obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
-diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
-new file mode 100644
-index 0000000..94d38d0
---- /dev/null
-+++ b/drivers/spi/spi-sun6i.c
-@@ -0,0 +1,483 @@
-+/*
-+ * Copyright (C) 2012 - 2014 Allwinner Tech
-+ * Pan Nan <pannan@allwinnertech.com>
-+ *
-+ * Copyright (C) 2014 Maxime Ripard
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/spi/spi.h>
-+
-+#define SUN6I_FIFO_DEPTH 128
-+
-+#define SUN6I_GBL_CTL_REG 0x04
-+#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
-+#define SUN6I_GBL_CTL_MASTER BIT(1)
-+#define SUN6I_GBL_CTL_TP BIT(7)
-+#define SUN6I_GBL_CTL_RST BIT(31)
-+
-+#define SUN6I_TFR_CTL_REG 0x08
-+#define SUN6I_TFR_CTL_CPHA BIT(0)
-+#define SUN6I_TFR_CTL_CPOL BIT(1)
-+#define SUN6I_TFR_CTL_SPOL BIT(2)
-+#define SUN6I_TFR_CTL_CS_MASK 0x3
-+#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
-+#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
-+#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
-+#define SUN6I_TFR_CTL_DHB BIT(8)
-+#define SUN6I_TFR_CTL_FBS BIT(12)
-+#define SUN6I_TFR_CTL_XCH BIT(31)
-+
-+#define SUN6I_INT_CTL_REG 0x10
-+#define SUN6I_INT_CTL_RF_OVF BIT(8)
-+#define SUN6I_INT_CTL_TC BIT(12)
-+
-+#define SUN6I_INT_STA_REG 0x14
-+
-+#define SUN6I_FIFO_CTL_REG 0x18
-+#define SUN6I_FIFO_CTL_RF_RST BIT(15)
-+#define SUN6I_FIFO_CTL_TF_RST BIT(31)
-+
-+#define SUN6I_FIFO_STA_REG 0x1c
-+#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
-+#define SUN6I_FIFO_STA_RF_CNT_BITS 0
-+#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
-+#define SUN6I_FIFO_STA_TF_CNT_BITS 16
-+
-+#define SUN6I_CLK_CTL_REG 0x24
-+#define SUN6I_CLK_CTL_CDR2_MASK 0xff
-+#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
-+#define SUN6I_CLK_CTL_CDR1_MASK 0xf
-+#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
-+#define SUN6I_CLK_CTL_DRS BIT(12)
-+
-+#define SUN6I_BURST_CNT_REG 0x30
-+#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_XMIT_CNT_REG 0x34
-+#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_BURST_CTL_CNT_REG 0x38
-+#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN6I_TXDATA_REG 0x200
-+#define SUN6I_RXDATA_REG 0x300
-+
-+struct sun6i_spi {
-+ struct spi_master *master;
-+ void __iomem *base_addr;
-+ struct clk *hclk;
-+ struct clk *mclk;
-+ struct reset_control *rstc;
-+
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
-+{
-+ return readl(sspi->base_addr + reg);
-+}
-+
-+static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
-+{
-+ writel(value, sspi->base_addr + reg);
-+}
-+
-+static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
-+{
-+ u32 reg, cnt;
-+ u8 byte;
-+
-+ /* See how much data is available */
-+ reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
-+ reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
-+ cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
-+
-+ if (len > cnt)
-+ len = cnt;
-+
-+ while (len--) {
-+ byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
-+ if (sspi->rx_buf)
-+ *sspi->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
-+{
-+ u8 byte;
-+
-+ if (len > sspi->len)
-+ len = sspi->len;
-+
-+ while (len--) {
-+ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-+ writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
-+ sspi->len--;
-+ }
-+}
-+
-+static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
-+ u32 reg;
-+
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+ reg &= ~SUN6I_TFR_CTL_CS_MASK;
-+ reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
-+
-+ if (enable)
-+ reg |= SUN6I_TFR_CTL_CS_LEVEL;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
-+
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
-+}
-+
-+
-+static int sun6i_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr)
-+{
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+ unsigned int mclk_rate, div, timeout;
-+ unsigned int tx_len = 0;
-+ int ret = 0;
-+ u32 reg;
-+
-+ /* We don't support transfer larger than the FIFO */
-+ if (tfr->len > SUN6I_FIFO_DEPTH)
-+ return -EINVAL;
-+
-+ reinit_completion(&sspi->done);
-+ sspi->tx_buf = tfr->tx_buf;
-+ sspi->rx_buf = tfr->rx_buf;
-+ sspi->len = tfr->len;
-+
-+ /* Clear pending interrupts */
-+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
-+
-+ /* Reset FIFO */
-+ sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
-+ SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
-+
-+ /*
-+ * Setup the transfer control register: Chip Select,
-+ * polarities, etc.
-+ */
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+
-+ if (spi->mode & SPI_CPOL)
-+ reg |= SUN6I_TFR_CTL_CPOL;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CPOL;
-+
-+ if (spi->mode & SPI_CPHA)
-+ reg |= SUN6I_TFR_CTL_CPHA;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_CPHA;
-+
-+ if (spi->mode & SPI_LSB_FIRST)
-+ reg |= SUN6I_TFR_CTL_FBS;
-+ else
-+ reg &= ~SUN6I_TFR_CTL_FBS;
-+
-+ /*
-+ * If it's a TX only transfer, we don't want to fill the RX
-+ * FIFO with bogus data
-+ */
-+ if (sspi->rx_buf)
-+ reg &= ~SUN6I_TFR_CTL_DHB;
-+ else
-+ reg |= SUN6I_TFR_CTL_DHB;
-+
-+ /* We want to control the chip select manually */
-+ reg |= SUN6I_TFR_CTL_CS_MANUAL;
-+
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
-+
-+ /* Ensure that we have a parent clock fast enough */
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ if (mclk_rate < (2 * spi->max_speed_hz)) {
-+ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ }
-+
-+ /*
-+ * Setup clock divider.
-+ *
-+ * We have two choices there. Either we can use the clock
-+ * divide rate 1, which is calculated thanks to this formula:
-+ * SPI_CLK = MOD_CLK / (2 ^ cdr)
-+ * Or we can use CDR2, which is calculated with the formula:
-+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+ * Wether we use the former or the latter is set through the
-+ * DRS bit.
-+ *
-+ * First try CDR2, and if we can't reach the expected
-+ * frequency, fall back to CDR1.
-+ */
-+ div = mclk_rate / (2 * spi->max_speed_hz);
-+ if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
-+ if (div > 0)
-+ div--;
-+
-+ reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
-+ } else {
-+ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
-+ reg = SUN6I_CLK_CTL_CDR1(div);
-+ }
-+
-+ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
-+
-+ /* Setup the transfer now... */
-+ if (sspi->tx_buf)
-+ tx_len = tfr->len;
-+
-+ /* Setup the counters */
-+ sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
-+ sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
-+ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
-+ SUN6I_BURST_CTL_CNT_STC(tx_len));
-+
-+ /* Fill the TX FIFO */
-+ sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
-+
-+ /* Enable the interrupts */
-+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
-+
-+ /* Start the transfer */
-+ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
-+ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
-+
-+ timeout = wait_for_completion_timeout(&sspi->done,
-+ msecs_to_jiffies(1000));
-+ if (!timeout) {
-+ ret = -ETIMEDOUT;
-+ goto out;
-+ }
-+
-+ sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
-+
-+out:
-+ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
-+
-+ return ret;
-+}
-+
-+static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
-+{
-+ struct sun6i_spi *sspi = dev_id;
-+ u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
-+
-+ /* Transfer complete */
-+ if (status & SUN6I_INT_CTL_TC) {
-+ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
-+ complete(&sspi->done);
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static int sun6i_spi_runtime_resume(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+ int ret;
-+
-+ ret = clk_prepare_enable(sspi->hclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable AHB clock\n");
-+ goto out;
-+ }
-+
-+ ret = clk_prepare_enable(sspi->mclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable module clock\n");
-+ goto err;
-+ }
-+
-+ ret = reset_control_deassert(sspi->rstc);
-+ if (ret) {
-+ dev_err(dev, "Couldn't deassert the device from reset\n");
-+ goto err2;
-+ }
-+
-+ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
-+ SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
-+
-+ return 0;
-+
-+err2:
-+ clk_disable_unprepare(sspi->mclk);
-+err:
-+ clk_disable_unprepare(sspi->hclk);
-+out:
-+ return ret;
-+}
-+
-+static int sun6i_spi_runtime_suspend(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun6i_spi *sspi = spi_master_get_devdata(master);
-+
-+ reset_control_assert(sspi->rstc);
-+ clk_disable_unprepare(sspi->mclk);
-+ clk_disable_unprepare(sspi->hclk);
-+
-+ return 0;
-+}
-+
-+static int sun6i_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct sun6i_spi *sspi;
-+ struct resource *res;
-+ int ret = 0, irq;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
-+ if (!master) {
-+ dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
-+ return -ENOMEM;
-+ }
-+
-+ platform_set_drvdata(pdev, master);
-+ sspi = spi_master_get_devdata(master);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(sspi->base_addr)) {
-+ ret = PTR_ERR(sspi->base_addr);
-+ goto err_free_master;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "No spi IRQ specified\n");
-+ ret = -ENXIO;
-+ goto err_free_master;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
-+ 0, "sun6i-spi", sspi);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Cannot request IRQ\n");
-+ goto err_free_master;
-+ }
-+
-+ sspi->master = master;
-+ master->set_cs = sun6i_spi_set_cs;
-+ master->transfer_one = sun6i_spi_transfer_one;
-+ master->num_chipselect = 4;
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+ master->dev.of_node = pdev->dev.of_node;
-+ master->auto_runtime_pm = true;
-+
-+ sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(sspi->hclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
-+ ret = PTR_ERR(sspi->hclk);
-+ goto err_free_master;
-+ }
-+
-+ sspi->mclk = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(sspi->mclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire module clock\n");
-+ ret = PTR_ERR(sspi->mclk);
-+ goto err_free_master;
-+ }
-+
-+ init_completion(&sspi->done);
-+
-+ sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
-+ if (IS_ERR(sspi->rstc)) {
-+ dev_err(&pdev->dev, "Couldn't get reset controller\n");
-+ ret = PTR_ERR(sspi->rstc);
-+ goto err_free_master;
-+ }
-+
-+ /*
-+ * This wake-up/shutdown pattern is to be able to have the
-+ * device woken up, even if runtime_pm is disabled
-+ */
-+ ret = sun6i_spi_runtime_resume(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Couldn't resume the device\n");
-+ goto err_free_master;
-+ }
-+
-+ pm_runtime_set_active(&pdev->dev);
-+ pm_runtime_enable(&pdev->dev);
-+ pm_runtime_idle(&pdev->dev);
-+
-+ ret = devm_spi_register_master(&pdev->dev, master);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot register SPI master\n");
-+ goto err_pm_disable;
-+ }
-+
-+ return 0;
-+
-+err_pm_disable:
-+ pm_runtime_disable(&pdev->dev);
-+ sun6i_spi_runtime_suspend(&pdev->dev);
-+err_free_master:
-+ spi_master_put(master);
-+ return ret;
-+}
-+
-+static int sun6i_spi_remove(struct platform_device *pdev)
-+{
-+ pm_runtime_disable(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun6i_spi_match[] = {
-+ { .compatible = "allwinner,sun6i-a31-spi", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun6i_spi_match);
-+
-+static const struct dev_pm_ops sun6i_spi_pm_ops = {
-+ .runtime_resume = sun6i_spi_runtime_resume,
-+ .runtime_suspend = sun6i_spi_runtime_suspend,
-+};
-+
-+static struct platform_driver sun6i_spi_driver = {
-+ .probe = sun6i_spi_probe,
-+ .remove = sun6i_spi_remove,
-+ .driver = {
-+ .name = "sun6i-spi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sun6i_spi_match,
-+ .pm = &sun6i_spi_pm_ops,
-+ },
-+};
-+module_platform_driver(sun6i_spi_driver);
-+
-+MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
-
-From 7961656a6f11b69966500d7bd25273203fd930da Mon Sep 17 00:00:00 2001
-From: Mark Brown <broonie@linaro.org>
-Date: Thu, 6 Feb 2014 10:53:51 +0000
-Subject: [PATCH 2/2] spi/sunxi: Add missing dependency on RESET_CONTROLLER
-
-Signed-off-by: Mark Brown <broonie@linaro.org>
----
- drivers/spi/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index 7cfe0ee..0ec4641 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -449,6 +449,7 @@ config SPI_SIRF
- config SPI_SUN6I
- tristate "Allwinner A31 SPI controller"
- depends on ARCH_SUNXI || COMPILE_TEST
-+ depends on RESET_CONTROLLER
- help
- This enables using the SPI controller on the Allwinner A31 SoCs.
-
---
-1.8.5.5
-
+++ /dev/null
-From b0a09c756bf6e0b89d6b88a7620ba4cd86b1895b Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:04 +0100
-Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
-
-The module clocks in the A31 are still compatible with the A10 one. Add the SPI
-module clocks and the PLL6 in the device tree to allow their use by the SPI
-controllers.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
- 1 file changed, 37 insertions(+), 9 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index 092bf97..93d7bb6 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -83,16 +83,12 @@
- clocks = <&osc24M>;
- };
-
-- /*
-- * This is a dummy clock, to be used as placeholder on
-- * other mux clocks when a specific parent clock is not
-- * yet implemented. It should be dropped when the driver
-- * is complete.
-- */
-- pll6: pll6 {
-+ pll6: clk@01c20028 {
- #clock-cells = <0>;
-- compatible = "fixed-clock";
-- clock-frequency = <0>;
-+ compatible = "allwinner,sun6i-a31-pll6-clk";
-+ reg = <0x01c20028 0x4>;
-+ clocks = <&osc24M>;
-+ clock-output-names = "pll6";
- };
-
- cpu: cpu@01c20050 {
-@@ -192,6 +188,38 @@
- "apb2_uart1", "apb2_uart2", "apb2_uart3",
- "apb2_uart4", "apb2_uart5";
- };
-+
-+ spi0_clk: clk@01c200a0 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a0 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi0";
-+ };
-+
-+ spi1_clk: clk@01c200a4 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a4 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi1";
-+ };
-+
-+ spi2_clk: clk@01c200a8 {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200a8 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi2";
-+ };
-+
-+ spi3_clk: clk@01c200ac {
-+ #clock-cells = <0>;
-+ compatible = "allwinner,sun4i-mod0-clk";
-+ reg = <0x01c200ac 0x4>;
-+ clocks = <&osc24M>, <&pll6>;
-+ clock-output-names = "spi3";
-+ };
- };
-
- soc@01c00000 {
---
-1.8.5.5
-
+++ /dev/null
-From 67e7ba38902a28679bf6ee8fd82952ae6795f5f5 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:53 +0100
-Subject: [PATCH] spi: sunxi: Add Allwinner A10 SPI controller driver
-
-The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
-controller.
-
-Unfortunately, this SPI controller, even though quite similar, is significantly
-different from the recently supported A31 SPI controller (different registers
-offset, split/merged registers, etc.). Supporting both controllers in a single
-driver would be unreasonable, hence the addition of a new driver.
-
-Like its more recent counterpart, it supports DMA, but the driver only does PIO
-until we have a dmaengine driver for this platform.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../devicetree/bindings/spi/spi-sun4i.txt | 24 ++
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-sun4i.c | 477 +++++++++++++++++++++
- 4 files changed, 508 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-sun4i.txt
- create mode 100644 drivers/spi/spi-sun4i.c
-
-diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
-new file mode 100644
-index 0000000..de827f5
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
-@@ -0,0 +1,24 @@
-+Allwinner A10 SPI controller
-+
-+Required properties:
-+- compatible: Should be "allwinner,sun4-a10-spi".
-+- reg: Should contain register location and length.
-+- interrupts: Should contain interrupt.
-+- clocks: phandle to the clocks feeding the SPI controller. Two are
-+ needed:
-+ - "ahb": the gated AHB parent clock
-+ - "mod": the parent module clock
-+- clock-names: Must contain the clock names described just above
-+
-+Example:
-+
-+spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+};
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index 58530d3..78adfae 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -446,6 +446,12 @@ config SPI_SIRF
- help
- SPI driver for CSR SiRFprimaII SoCs
-
-+config SPI_SUN4I
-+ tristate "Allwinner A10 SoCs SPI controller"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
-+
- config SPI_SUN6I
- tristate "Allwinner A31 SPI controller"
- depends on ARCH_SUNXI || COMPILE_TEST
-diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
-index 13b6ccf..65f4993 100644
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
- obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
- obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
- obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
-+obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
- obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
- obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
- obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
-diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
-new file mode 100644
-index 0000000..3f82705
---- /dev/null
-+++ b/drivers/spi/spi-sun4i.c
-@@ -0,0 +1,477 @@
-+/*
-+ * Copyright (C) 2012 - 2014 Allwinner Tech
-+ * Pan Nan <pannan@allwinnertech.com>
-+ *
-+ * Copyright (C) 2014 Maxime Ripard
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/spi/spi.h>
-+
-+#define SUN4I_FIFO_DEPTH 64
-+
-+#define SUN4I_RXDATA_REG 0x00
-+
-+#define SUN4I_TXDATA_REG 0x04
-+
-+#define SUN4I_CTL_REG 0x08
-+#define SUN4I_CTL_ENABLE BIT(0)
-+#define SUN4I_CTL_MASTER BIT(1)
-+#define SUN4I_CTL_CPHA BIT(2)
-+#define SUN4I_CTL_CPOL BIT(3)
-+#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
-+#define SUN4I_CTL_LMTF BIT(6)
-+#define SUN4I_CTL_TF_RST BIT(8)
-+#define SUN4I_CTL_RF_RST BIT(9)
-+#define SUN4I_CTL_XCH BIT(10)
-+#define SUN4I_CTL_CS_MASK 0x3000
-+#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
-+#define SUN4I_CTL_DHB BIT(15)
-+#define SUN4I_CTL_CS_MANUAL BIT(16)
-+#define SUN4I_CTL_CS_LEVEL BIT(17)
-+#define SUN4I_CTL_TP BIT(18)
-+
-+#define SUN4I_INT_CTL_REG 0x0c
-+#define SUN4I_INT_CTL_TC BIT(16)
-+
-+#define SUN4I_INT_STA_REG 0x10
-+
-+#define SUN4I_DMA_CTL_REG 0x14
-+
-+#define SUN4I_WAIT_REG 0x18
-+
-+#define SUN4I_CLK_CTL_REG 0x1c
-+#define SUN4I_CLK_CTL_CDR2_MASK 0xff
-+#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
-+#define SUN4I_CLK_CTL_CDR1_MASK 0xf
-+#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
-+#define SUN4I_CLK_CTL_DRS BIT(12)
-+
-+#define SUN4I_BURST_CNT_REG 0x20
-+#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN4I_XMIT_CNT_REG 0x24
-+#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
-+
-+#define SUN4I_FIFO_STA_REG 0x28
-+#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
-+#define SUN4I_FIFO_STA_RF_CNT_BITS 0
-+#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
-+#define SUN4I_FIFO_STA_TF_CNT_BITS 16
-+
-+struct sun4i_spi {
-+ struct spi_master *master;
-+ void __iomem *base_addr;
-+ struct clk *hclk;
-+ struct clk *mclk;
-+
-+ struct completion done;
-+
-+ const u8 *tx_buf;
-+ u8 *rx_buf;
-+ int len;
-+};
-+
-+static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
-+{
-+ return readl(sspi->base_addr + reg);
-+}
-+
-+static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
-+{
-+ writel(value, sspi->base_addr + reg);
-+}
-+
-+static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
-+{
-+ u32 reg, cnt;
-+ u8 byte;
-+
-+ /* See how much data is available */
-+ reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
-+ reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
-+ cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
-+
-+ if (len > cnt)
-+ len = cnt;
-+
-+ while (len--) {
-+ byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
-+ if (sspi->rx_buf)
-+ *sspi->rx_buf++ = byte;
-+ }
-+}
-+
-+static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
-+{
-+ u8 byte;
-+
-+ if (len > sspi->len)
-+ len = sspi->len;
-+
-+ while (len--) {
-+ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
-+ writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
-+ sspi->len--;
-+ }
-+}
-+
-+static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
-+ u32 reg;
-+
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+
-+ reg &= ~SUN4I_CTL_CS_MASK;
-+ reg |= SUN4I_CTL_CS(spi->chip_select);
-+
-+ if (enable)
-+ reg |= SUN4I_CTL_CS_LEVEL;
-+ else
-+ reg &= ~SUN4I_CTL_CS_LEVEL;
-+
-+ /*
-+ * Even though this looks irrelevant since we are supposed to
-+ * be controlling the chip select manually, this bit also
-+ * controls the levels of the chip select for inactive
-+ * devices.
-+ *
-+ * If we don't set it, the chip select level will go low by
-+ * default when the device is idle, which is not really
-+ * expected in the common case where the chip select is active
-+ * low.
-+ */
-+ if (spi->mode & SPI_CS_HIGH)
-+ reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
-+ else
-+ reg |= SUN4I_CTL_CS_ACTIVE_LOW;
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
-+}
-+
-+static int sun4i_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi,
-+ struct spi_transfer *tfr)
-+{
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+ unsigned int mclk_rate, div, timeout;
-+ unsigned int tx_len = 0;
-+ int ret = 0;
-+ u32 reg;
-+
-+ /* We don't support transfer larger than the FIFO */
-+ if (tfr->len > SUN4I_FIFO_DEPTH)
-+ return -EINVAL;
-+
-+ reinit_completion(&sspi->done);
-+ sspi->tx_buf = tfr->tx_buf;
-+ sspi->rx_buf = tfr->rx_buf;
-+ sspi->len = tfr->len;
-+
-+ /* Clear pending interrupts */
-+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
-+
-+
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+
-+ /* Reset FIFOs */
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG,
-+ reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
-+
-+ /*
-+ * Setup the transfer control register: Chip Select,
-+ * polarities, etc.
-+ */
-+ if (spi->mode & SPI_CPOL)
-+ reg |= SUN4I_CTL_CPOL;
-+ else
-+ reg &= ~SUN4I_CTL_CPOL;
-+
-+ if (spi->mode & SPI_CPHA)
-+ reg |= SUN4I_CTL_CPHA;
-+ else
-+ reg &= ~SUN4I_CTL_CPHA;
-+
-+ if (spi->mode & SPI_LSB_FIRST)
-+ reg |= SUN4I_CTL_LMTF;
-+ else
-+ reg &= ~SUN4I_CTL_LMTF;
-+
-+
-+ /*
-+ * If it's a TX only transfer, we don't want to fill the RX
-+ * FIFO with bogus data
-+ */
-+ if (sspi->rx_buf)
-+ reg &= ~SUN4I_CTL_DHB;
-+ else
-+ reg |= SUN4I_CTL_DHB;
-+
-+ /* We want to control the chip select manually */
-+ reg |= SUN4I_CTL_CS_MANUAL;
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
-+
-+ /* Ensure that we have a parent clock fast enough */
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ if (mclk_rate < (2 * spi->max_speed_hz)) {
-+ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ }
-+
-+ /*
-+ * Setup clock divider.
-+ *
-+ * We have two choices there. Either we can use the clock
-+ * divide rate 1, which is calculated thanks to this formula:
-+ * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
-+ * Or we can use CDR2, which is calculated with the formula:
-+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+ * Wether we use the former or the latter is set through the
-+ * DRS bit.
-+ *
-+ * First try CDR2, and if we can't reach the expected
-+ * frequency, fall back to CDR1.
-+ */
-+ div = mclk_rate / (2 * spi->max_speed_hz);
-+ if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
-+ if (div > 0)
-+ div--;
-+
-+ reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
-+ } else {
-+ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
-+ reg = SUN4I_CLK_CTL_CDR1(div);
-+ }
-+
-+ sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
-+
-+ /* Setup the transfer now... */
-+ if (sspi->tx_buf)
-+ tx_len = tfr->len;
-+
-+ /* Setup the counters */
-+ sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
-+ sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
-+
-+ /* Fill the TX FIFO */
-+ sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
-+
-+ /* Enable the interrupts */
-+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
-+
-+ /* Start the transfer */
-+ reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
-+
-+ timeout = wait_for_completion_timeout(&sspi->done,
-+ msecs_to_jiffies(1000));
-+ if (!timeout) {
-+ ret = -ETIMEDOUT;
-+ goto out;
-+ }
-+
-+ sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
-+
-+out:
-+ sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
-+
-+ return ret;
-+}
-+
-+static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
-+{
-+ struct sun4i_spi *sspi = dev_id;
-+ u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
-+
-+ /* Transfer complete */
-+ if (status & SUN4I_INT_CTL_TC) {
-+ sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
-+ complete(&sspi->done);
-+ return IRQ_HANDLED;
-+ }
-+
-+ return IRQ_NONE;
-+}
-+
-+static int sun4i_spi_runtime_resume(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+ int ret;
-+
-+ ret = clk_prepare_enable(sspi->hclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable AHB clock\n");
-+ goto out;
-+ }
-+
-+ ret = clk_prepare_enable(sspi->mclk);
-+ if (ret) {
-+ dev_err(dev, "Couldn't enable module clock\n");
-+ goto err;
-+ }
-+
-+ sun4i_spi_write(sspi, SUN4I_CTL_REG,
-+ SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
-+
-+ return 0;
-+
-+err:
-+ clk_disable_unprepare(sspi->hclk);
-+out:
-+ return ret;
-+}
-+
-+static int sun4i_spi_runtime_suspend(struct device *dev)
-+{
-+ struct spi_master *master = dev_get_drvdata(dev);
-+ struct sun4i_spi *sspi = spi_master_get_devdata(master);
-+
-+ clk_disable_unprepare(sspi->mclk);
-+ clk_disable_unprepare(sspi->hclk);
-+
-+ return 0;
-+}
-+
-+static int sun4i_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct sun4i_spi *sspi;
-+ struct resource *res;
-+ int ret = 0, irq;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
-+ if (!master) {
-+ dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
-+ return -ENOMEM;
-+ }
-+
-+ platform_set_drvdata(pdev, master);
-+ sspi = spi_master_get_devdata(master);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(sspi->base_addr)) {
-+ ret = PTR_ERR(sspi->base_addr);
-+ goto err_free_master;
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "No spi IRQ specified\n");
-+ ret = -ENXIO;
-+ goto err_free_master;
-+ }
-+
-+ ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
-+ 0, "sun4i-spi", sspi);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Cannot request IRQ\n");
-+ goto err_free_master;
-+ }
-+
-+ sspi->master = master;
-+ master->set_cs = sun4i_spi_set_cs;
-+ master->transfer_one = sun4i_spi_transfer_one;
-+ master->num_chipselect = 4;
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+ master->dev.of_node = pdev->dev.of_node;
-+ master->auto_runtime_pm = true;
-+
-+ sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
-+ if (IS_ERR(sspi->hclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
-+ ret = PTR_ERR(sspi->hclk);
-+ goto err_free_master;
-+ }
-+
-+ sspi->mclk = devm_clk_get(&pdev->dev, "mod");
-+ if (IS_ERR(sspi->mclk)) {
-+ dev_err(&pdev->dev, "Unable to acquire module clock\n");
-+ ret = PTR_ERR(sspi->mclk);
-+ goto err_free_master;
-+ }
-+
-+ init_completion(&sspi->done);
-+
-+ /*
-+ * This wake-up/shutdown pattern is to be able to have the
-+ * device woken up, even if runtime_pm is disabled
-+ */
-+ ret = sun4i_spi_runtime_resume(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Couldn't resume the device\n");
-+ goto err_free_master;
-+ }
-+
-+ pm_runtime_set_active(&pdev->dev);
-+ pm_runtime_enable(&pdev->dev);
-+ pm_runtime_idle(&pdev->dev);
-+
-+ ret = devm_spi_register_master(&pdev->dev, master);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot register SPI master\n");
-+ goto err_pm_disable;
-+ }
-+
-+ return 0;
-+
-+err_pm_disable:
-+ pm_runtime_disable(&pdev->dev);
-+ sun4i_spi_runtime_suspend(&pdev->dev);
-+err_free_master:
-+ spi_master_put(master);
-+ return ret;
-+}
-+
-+static int sun4i_spi_remove(struct platform_device *pdev)
-+{
-+ pm_runtime_disable(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_spi_match[] = {
-+ { .compatible = "allwinner,sun4i-a10-spi", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_spi_match);
-+
-+static const struct dev_pm_ops sun4i_spi_pm_ops = {
-+ .runtime_resume = sun4i_spi_runtime_resume,
-+ .runtime_suspend = sun4i_spi_runtime_suspend,
-+};
-+
-+static struct platform_driver sun4i_spi_driver = {
-+ .probe = sun4i_spi_probe,
-+ .remove = sun4i_spi_remove,
-+ .driver = {
-+ .name = "sun4i-spi",
-+ .owner = THIS_MODULE,
-+ .of_match_table = sun4i_spi_match,
-+ .pm = &sun4i_spi_pm_ops,
-+ },
-+};
-+module_platform_driver(sun4i_spi_driver);
-+
-+MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 3fff6e0d2bdd3b3f999a9dfcc8432ecba56eaad8 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:54 +0100
-Subject: [PATCH] ARM: dt: sun7i: Add A20 SPI controller nodes
-
-The A20 has 4 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index 1961751..bcea04a 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -393,6 +393,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <0 10 4>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <0 11 4>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -485,6 +507,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <0 12 4>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -513,6 +546,17 @@
- status = "disabled";
- };
-
-+ spi3: spi@01c1f000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c1f000 0x1000>;
-+ interrupts = <0 50 4>;
-+ clocks = <&ahb_gates 23>, <&spi3_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- pio: pinctrl@01c20800 {
- compatible = "allwinner,sun7i-a20-pinctrl";
- reg = <0x01c20800 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From f21f034bd5b288068e1fa35c28d5e48e9ae8cbf5 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:55 +0100
-Subject: [PATCH] ARM: dt: sun4i: Add A10 SPI controller nodes
-
-The A10 has 4 SPI controllers that are now supported. Add them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 3a5775c..cdd5b72 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -331,6 +331,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -423,6 +445,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ahci: sata@01c18000 {
- compatible = "allwinner,sun4i-a10-ahci";
- reg = <0x01c18000 0x1000>;
-@@ -451,6 +484,17 @@
- status = "disabled";
- };
-
-+ spi3: spi@01c1f000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c1f000 0x1000>;
-+ interrupts = <50>;
-+ clocks = <&ahb_gates 23>, <&spi3_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From f76e72a20510fa17934c82bed5e23f7c4a4f2931 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:56 +0100
-Subject: [PATCH] ARM: dt: sun5i: Add A10s SPI controller nodes
-
-The A10s has 3 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a10s.dtsi | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index e5064dc..2dedb7c 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -292,6 +292,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- emac: ethernet@01c0b000 {
- compatible = "allwinner,sun4i-a10-emac";
- reg = <0x01c0b000 0x1000>;
-@@ -373,6 +395,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From a02b2ef06a3f11d2e6c20c2cdcdd6f0b4217d234 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:57 +0100
-Subject: [PATCH] ARM: dt: sun5i: Add A13 SPI controller nodes
-
-The A13 has 3 SPI controllers compatible with the one found in the A10. Add
-them in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun5i-a13.dtsi | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index b0cc56c..1ff406b 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -290,6 +290,28 @@
- #size-cells = <1>;
- ranges;
-
-+ spi0: spi@01c05000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c05000 0x1000>;
-+ interrupts = <10>;
-+ clocks = <&ahb_gates 20>, <&spi0_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@01c06000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c06000 0x1000>;
-+ interrupts = <11>;
-+ clocks = <&ahb_gates 21>, <&spi1_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
-@@ -344,6 +366,17 @@
- status = "disabled";
- };
-
-+ spi2: spi@01c17000 {
-+ compatible = "allwinner,sun4i-a10-spi";
-+ reg = <0x01c17000 0x1000>;
-+ interrupts = <12>;
-+ clocks = <&ahb_gates 22>, <&spi2_clk>;
-+ clock-names = "ahb", "mod";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- intc: interrupt-controller@01c20400 {
- compatible = "allwinner,sun4i-ic";
- reg = <0x01c20400 0x400>;
---
-1.8.5.5
-
+++ /dev/null
-From eb9180f426a7da1da5ed0f3aa13b92609c869fc0 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:58 +0100
-Subject: [PATCH] ARM: dt: sun7i: Add SPI muxing options
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index bcea04a..9f57035 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -688,6 +688,20 @@
- allwinner,drive = <2>;
- allwinner,pull = <0>;
- };
-+
-+ spi1_pins_a: spi1@0 {
-+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-+ allwinner,function = "spi1";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ spi2_pins_a: spi2@0 {
-+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
-+ allwinner,function = "spi2";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
- };
-
- timer@01c20c00 {
---
-1.8.5.5
-
+++ /dev/null
-From 5c5ac3fb749c64e7c1e6e3208fcabab065359f56 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sat, 22 Feb 2014 22:35:59 +0100
-Subject: [PATCH] ARM: dts: sun7i: Enable the SPI controllers of the
- A20-olinuxino-micro
-
-The A20-Olinuxino-micro has two SPI bus exposed on its UEXT connectors, enable
-them.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-index 824ce0a..68cedf3 100644
---- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
-@@ -21,7 +21,24 @@
- model = "Olimex A20-Olinuxino Micro";
- compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
-
-+ aliases {
-+ spi0 = &spi1;
-+ spi1 = &spi2;
-+ };
-+
- soc@01c00000 {
-+ spi1: spi@01c06000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi1_pins_a>;
-+ status = "okay";
-+ };
-+
-+ spi2: spi@01c17000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi2_pins_a>;
-+ status = "okay";
-+ };
-+
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default", "default";
- pinctrl-0 = <&mmc0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 111579574584c73a91c2b1bf8657c3691cc22409 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:23 +0100
-Subject: [PATCH] wdt: sunxi: Introduce a new compatible for the A10 and A31
-
-For historical reasons, the Allwinner A10 compatibles are not following the
-patterns used for this other Allwinner SoCs.
-
-Introduce a new compatible following the usual pattern, and deprecate the olders.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 7 ++++---
- drivers/watchdog/sunxi_wdt.c | 1 +
- 2 files changed, 5 insertions(+), 3 deletions(-)
-
-diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-index e39cb26..6e8c937 100644
---- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
-@@ -2,13 +2,14 @@ Allwinner SoCs Watchdog timer
-
- Required properties:
-
--- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
-- SoC families being sun4i and sun6i
-+- compatible : should be either "allwinner,sun4i-a10-wdt" or
-+ "allwinner,sun6i-a31-wdt" (deprecated:
-+ "allwinner,sun4i-wdt", "allwinner,sun6i-wdt")
- - reg : Specifies base physical address and size of the registers.
-
- Example:
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
-index 76332d89..7c8923d 100644
---- a/drivers/watchdog/sunxi_wdt.c
-+++ b/drivers/watchdog/sunxi_wdt.c
-@@ -206,6 +206,7 @@ static void sunxi_wdt_shutdown(struct platform_device *pdev)
-
- static const struct of_device_id sunxi_wdt_dt_ids[] = {
- { .compatible = "allwinner,sun4i-wdt" },
-+ { .compatible = "allwinner,sun4i-a10-wdt" },
- { /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
---
-1.8.5.5
-
+++ /dev/null
-From b50ff681c8e3e9e408ee1fb6c6317bc8da653a01 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:24 +0100
-Subject: [PATCH] ARM: sunxi: Add the new watchog compatibles to the reboot
- code
-
-Now that the watchdog driver has new compatibles, we need to support them in
-the machine reboot code too.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/mach-sunxi/sunxi.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
-index aeea6ce..c310df6 100644
---- a/arch/arm/mach-sunxi/sunxi.c
-+++ b/arch/arm/mach-sunxi/sunxi.c
-@@ -95,7 +95,9 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd)
-
- static struct of_device_id sunxi_restart_ids[] = {
- { .compatible = "allwinner,sun4i-wdt" },
-+ { .compatible = "allwinner,sun4i-a10-wdt" },
- { .compatible = "allwinner,sun6i-wdt" },
-+ { .compatible = "allwinner,sun6i-a31-wdt" },
- { /*sentinel*/ }
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 0dba36162dffdee935287645d515f53057de3537 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Sun, 2 Feb 2014 14:55:25 +0100
-Subject: [PATCH] ARM: sunxi: dt: Update the watchdog compatibles
-
-The watchdog compatibles were following a different pattern than the one found
-in the other devices. Now that the driver supports the right pattern, switch to
-it in the DT.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +-
- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
- 5 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
-index 80bbdeb..3a5775c 100644
---- a/arch/arm/boot/dts/sun4i-a10.dtsi
-+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
-@@ -545,7 +545,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
-index a5431ed..e5064dc 100644
---- a/arch/arm/boot/dts/sun5i-a10s.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
-@@ -467,7 +467,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
-index 7fe9cdc..b0cc56c 100644
---- a/arch/arm/boot/dts/sun5i-a13.dtsi
-+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
-@@ -413,7 +413,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
-diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
-index b4407f17..c15f30e 100644
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -289,7 +289,7 @@
- };
-
- wdt1: watchdog@01c20ca0 {
-- compatible = "allwinner,sun6i-wdt";
-+ compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- };
-
-diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
-index e67924a..1961751 100644
---- a/arch/arm/boot/dts/sun7i-a20.dtsi
-+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
-@@ -659,7 +659,7 @@
- };
-
- wdt: watchdog@01c20c90 {
-- compatible = "allwinner,sun4i-wdt";
-+ compatible = "allwinner,sun4i-a10-wdt";
- reg = <0x01c20c90 0x10>;
- };
-
---
-1.8.5.5
-
+++ /dev/null
-From 328d21d9c56ddca56ed80b1595066b1621f6926b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 23 Dec 2013 16:21:02 +0100
-Subject: [PATCH] input: Add new sun4i-ts driver for Allwinner sunxi SoC's rtp
- controller
-
-Note the sun4i-ts controller is capable of detecting a second touch, but when
-a second touch is present then the accuracy becomes so bad the reported touch
-location is not useable.
-
-The original android driver contains some complicated heuristics using the
-aprox. distance between the 2 touches to see if the user is making a pinch
-open / close movement, and then reports emulated multi-touch events around
-the last touch coordinate (as the dual-touch coordinates are worthless).
-
-These kinds of heuristics are just asking for trouble (and don't belong
-in the kernel). So this driver offers straight forward, reliable single
-touch functionality only.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- .../bindings/input/touchscreen/sun4i.txt | 15 ++
- drivers/input/touchscreen/Kconfig | 10 +
- drivers/input/touchscreen/Makefile | 1 +
- drivers/input/touchscreen/sun4i-ts.c | 262 +++++++++++++++++++++
- 4 files changed, 288 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
- create mode 100644 drivers/input/touchscreen/sun4i-ts.c
-
-diff --git a/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-new file mode 100644
-index 0000000..e45927e
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/touchscreen/sun4i.txt
-@@ -0,0 +1,15 @@
-+sun4i resistive touchscreen controller
-+--------------------------------------
-+
-+Required properties:
-+ - compatible: "allwinner,sun4i-ts"
-+ - reg: mmio address range of the chip
-+ - interrupts: interrupt to which the chip is connected
-+
-+Example:
-+
-+ rtp: rtp@01c25000 {
-+ compatible = "allwinner,sun4i-ts";
-+ reg = <0x01c25000 0x100>;
-+ interrupts = <29>;
-+ };
-diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
-index 07e9e82..f4c5ca3 100644
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -906,6 +906,16 @@ config TOUCHSCREEN_STMPE
- To compile this driver as a module, choose M here: the
- module will be called stmpe-ts.
-
-+config TOUCHSCREEN_SUN4I
-+ tristate "Allwinner sun4i resistive touchscreen controller support"
-+ depends on ARCH_SUNXI
-+ help
-+ This selects support for the resistive touchscreen controller
-+ found on Allwinner sunxi SoCs.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called sun4i-ts.
-+
- config TOUCHSCREEN_SUR40
- tristate "Samsung SUR40 (Surface 2.0/PixelSense) touchscreen"
- depends on USB
-diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
-index 62801f2..c8f7375 100644
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_TOUCHSCREEN_PIXCIR) += pixcir_i2c_ts.o
- obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o
- obj-$(CONFIG_TOUCHSCREEN_ST1232) += st1232.o
- obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o
-+obj-$(CONFIG_TOUCHSCREEN_SUN4I) += sun4i-ts.o
- obj-$(CONFIG_TOUCHSCREEN_SUR40) += sur40.o
- obj-$(CONFIG_TOUCHSCREEN_TI_AM335X_TSC) += ti_am335x_tsc.o
- obj-$(CONFIG_TOUCHSCREEN_TNETV107X) += tnetv107x-ts.o
-diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c
-new file mode 100644
-index 0000000..5945219
---- /dev/null
-+++ b/drivers/input/touchscreen/sun4i-ts.c
-@@ -0,0 +1,262 @@
-+/*
-+ * Allwinner sunxi resistive touchscreen controller driver
-+ *
-+ * Copyright (C) 2013 - 2014 Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * The sun4i-ts controller is capable of detecting a second touch, but when a
-+ * second touch is present then the accuracy becomes so bad the reported touch
-+ * location is not useable.
-+ *
-+ * The original android driver contains some complicated heuristics using the
-+ * aprox. distance between the 2 touches to see if the user is making a pinch
-+ * open / close movement, and then reports emulated multi-touch events around
-+ * the last touch coordinate (as the dual-touch coordinates are worthless).
-+ *
-+ * These kinds of heuristics are just asking for trouble (and don't belong
-+ * in the kernel). So this driver offers straight forward, reliable single
-+ * touch functionality only.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#define TP_CTRL0 0x00
-+#define TP_CTRL1 0x04
-+#define TP_CTRL2 0x08
-+#define TP_CTRL3 0x0c
-+#define TP_INT_FIFOC 0x10
-+#define TP_INT_FIFOS 0x14
-+#define TP_TPR 0x18
-+#define TP_CDAT 0x1c
-+#define TEMP_DATA 0x20
-+#define TP_DATA 0x24
-+
-+/* TP_CTRL0 bits */
-+#define ADC_FIRST_DLY(x) ((x) << 24) /* 8 bits */
-+#define ADC_FIRST_DLY_MODE(x) ((x) << 23)
-+#define ADC_CLK_SEL(x) ((x) << 22)
-+#define ADC_CLK_DIV(x) ((x) << 20) /* 3 bits */
-+#define FS_DIV(x) ((x) << 16) /* 4 bits */
-+#define T_ACQ(x) ((x) << 0) /* 16 bits */
-+
-+/* TP_CTRL1 bits */
-+#define STYLUS_UP_DEBOUN(x) ((x) << 12) /* 8 bits */
-+#define STYLUS_UP_DEBOUN_EN(x) ((x) << 9)
-+#define TOUCH_PAN_CALI_EN(x) ((x) << 6)
-+#define TP_DUAL_EN(x) ((x) << 5)
-+#define TP_MODE_EN(x) ((x) << 4)
-+#define TP_ADC_SELECT(x) ((x) << 3)
-+#define ADC_CHAN_SELECT(x) ((x) << 0) /* 3 bits */
-+
-+/* TP_CTRL2 bits */
-+#define TP_SENSITIVE_ADJUST(x) ((x) << 28) /* 4 bits */
-+#define TP_MODE_SELECT(x) ((x) << 26) /* 2 bits */
-+#define PRE_MEA_EN(x) ((x) << 24)
-+#define PRE_MEA_THRE_CNT(x) ((x) << 0) /* 24 bits */
-+
-+/* TP_CTRL3 bits */
-+#define FILTER_EN(x) ((x) << 2)
-+#define FILTER_TYPE(x) ((x) << 0) /* 2 bits */
-+
-+/* TP_INT_FIFOC irq and fifo mask / control bits */
-+#define TEMP_IRQ_EN(x) ((x) << 18)
-+#define OVERRUN_IRQ_EN(x) ((x) << 17)
-+#define DATA_IRQ_EN(x) ((x) << 16)
-+#define TP_DATA_XY_CHANGE(x) ((x) << 13)
-+#define FIFO_TRIG(x) ((x) << 8) /* 5 bits */
-+#define DATA_DRQ_EN(x) ((x) << 7)
-+#define FIFO_FLUSH(x) ((x) << 4)
-+#define TP_UP_IRQ_EN(x) ((x) << 1)
-+#define TP_DOWN_IRQ_EN(x) ((x) << 0)
-+
-+/* TP_INT_FIFOS irq and fifo status bits */
-+#define TEMP_DATA_PENDING BIT(18)
-+#define FIFO_OVERRUN_PENDING BIT(17)
-+#define FIFO_DATA_PENDING BIT(16)
-+#define TP_IDLE_FLG BIT(2)
-+#define TP_UP_PENDING BIT(1)
-+#define TP_DOWN_PENDING BIT(0)
-+
-+/* TP_TPR bits */
-+#define TEMP_ENABLE(x) ((x) << 16)
-+#define TEMP_PERIOD(x) ((x) << 0) /* t = x * 256 * 16 / clkin */
-+
-+struct sun4i_ts_data {
-+ struct device *dev;
-+ struct input_dev *input;
-+ void __iomem *base;
-+ unsigned int irq;
-+ bool ignore_fifo_data;
-+};
-+
-+static irqreturn_t sun4i_ts_irq(int irq, void *dev_id)
-+{
-+ struct sun4i_ts_data *ts = dev_id;
-+ u32 reg_val, x, y;
-+
-+ reg_val = readl(ts->base + TP_INT_FIFOS);
-+
-+ if (reg_val & FIFO_DATA_PENDING) {
-+ x = readl(ts->base + TP_DATA);
-+ y = readl(ts->base + TP_DATA);
-+ /* The 1st location reported after an up event is unreliable */
-+ if (!ts->ignore_fifo_data) {
-+ input_report_abs(ts->input, ABS_X, x);
-+ input_report_abs(ts->input, ABS_Y, y);
-+ /*
-+ * The hardware has a separate down status bit, but
-+ * that gets set before we get the first location,
-+ * resulting in reporting a click on the old location.
-+ */
-+ input_report_key(ts->input, BTN_TOUCH, 1);
-+ input_sync(ts->input);
-+ } else {
-+ ts->ignore_fifo_data = false;
-+ }
-+ }
-+
-+ if (reg_val & TP_UP_PENDING) {
-+ ts->ignore_fifo_data = true;
-+ input_report_key(ts->input, BTN_TOUCH, 0);
-+ input_sync(ts->input);
-+ }
-+
-+ writel(reg_val, ts->base + TP_INT_FIFOS);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int sun4i_ts_open(struct input_dev *dev)
-+{
-+ struct sun4i_ts_data *ts = input_get_drvdata(dev);
-+
-+ /* Flush, set trig level to 1, enable data and up irqs */
-+ writel(DATA_IRQ_EN(1) | FIFO_TRIG(1) | FIFO_FLUSH(1) | TP_UP_IRQ_EN(1),
-+ ts->base + TP_INT_FIFOC);
-+
-+ return 0;
-+}
-+
-+static void sun4i_ts_close(struct input_dev *dev)
-+{
-+ struct sun4i_ts_data *ts = input_get_drvdata(dev);
-+
-+ /* Deactivate all IRQs */
-+ writel(0, ts->base + TP_INT_FIFOC);
-+}
-+
-+static int sun4i_ts_probe(struct platform_device *pdev)
-+{
-+ struct sun4i_ts_data *ts;
-+ struct device *dev = &pdev->dev;
-+ int ret;
-+
-+ ts = devm_kzalloc(dev, sizeof(struct sun4i_ts_data), GFP_KERNEL);
-+ if (!ts)
-+ return -ENOMEM;
-+
-+ ts->dev = dev;
-+ ts->ignore_fifo_data = true;
-+
-+ ts->input = devm_input_allocate_device(dev);
-+ if (!ts->input)
-+ return -ENOMEM;
-+
-+ ts->input->name = pdev->name;
-+ ts->input->phys = "sun4i_ts/input0";
-+ ts->input->open = sun4i_ts_open;
-+ ts->input->close = sun4i_ts_close;
-+ ts->input->id.bustype = BUS_HOST;
-+ ts->input->id.vendor = 0x0001;
-+ ts->input->id.product = 0x0001;
-+ ts->input->id.version = 0x0100;
-+ ts->input->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
-+ set_bit(BTN_TOUCH, ts->input->keybit);
-+ input_set_abs_params(ts->input, ABS_X, 0, 4095, 0, 0);
-+ input_set_abs_params(ts->input, ABS_Y, 0, 4095, 0, 0);
-+ input_set_drvdata(ts->input, ts);
-+
-+ ts->base = devm_ioremap_resource(dev,
-+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
-+ if (IS_ERR(ts->base))
-+ return PTR_ERR(ts->base);
-+
-+ ts->irq = platform_get_irq(pdev, 0);
-+ ret = devm_request_irq(dev, ts->irq, sun4i_ts_irq, 0, "sun4i-ts", ts);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Select HOSC clk, clkin = clk / 6, adc samplefreq = clkin / 8192,
-+ * t_acq = clkin / (16 * 64)
-+ */
-+ writel(ADC_CLK_SEL(0) | ADC_CLK_DIV(2) | FS_DIV(7) | T_ACQ(63),
-+ ts->base + TP_CTRL0);
-+
-+ /*
-+ * sensitive_adjust = 15 : max, which is not all that sensitive,
-+ * tp_mode = 0 : only x and y coordinates, as we don't use dual touch
-+ */
-+ writel(TP_SENSITIVE_ADJUST(15) | TP_MODE_SELECT(0),
-+ ts->base + TP_CTRL2);
-+
-+ /* Enable median filter, type 1 : 5/3 */
-+ writel(FILTER_EN(1) | FILTER_TYPE(1), ts->base + TP_CTRL3);
-+
-+ /* Enable temperature measurement, period 1953 (2 seconds) */
-+ writel(TEMP_ENABLE(1) | TEMP_PERIOD(1953), ts->base + TP_TPR);
-+
-+ /*
-+ * Set stylus up debounce to aprox 10 ms, enable debounce, and
-+ * finally enable tp mode.
-+ */
-+ writel(STYLUS_UP_DEBOUN(5) | STYLUS_UP_DEBOUN_EN(1) | TP_MODE_EN(1),
-+ ts->base + TP_CTRL1);
-+
-+ ret = input_register_device(ts->input);
-+ if (ret)
-+ return ret;
-+
-+ platform_set_drvdata(pdev, ts);
-+ return 0;
-+}
-+
-+static const struct of_device_id sun4i_ts_of_match[] = {
-+ { .compatible = "allwinner,sun4i-ts", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, sun4i_ts_of_match);
-+
-+static struct platform_driver sun4i_ts_driver = {
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "sun4i-ts",
-+ .of_match_table = of_match_ptr(sun4i_ts_of_match),
-+ },
-+ .probe = sun4i_ts_probe,
-+};
-+
-+module_platform_driver(sun4i_ts_driver);
-+
-+MODULE_DESCRIPTION("Allwinner sun4i resistive touchscreen controller driver");
-+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
-+MODULE_LICENSE("GPL");
---
-1.8.5.5
-
+++ /dev/null
-From 248529e6c78ba746988f1313f7bfb7ae74eae785 Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Mon, 13 Jan 2014 14:15:01 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add basic board support for LinkSprite
- pcDuino
-
-This patch will add a basic board support DT for the
-LinkSprite pcDuino board.
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 48 +++++++++++++++++++++++++++++++++
- 2 files changed, 49 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-pcduino.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 6d1e43d..0b127db 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -283,6 +283,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-cubieboard.dtb \
- sun4i-a10-mini-xplus.dtb \
- sun4i-a10-hackberry.dtb \
-+ sun4i-a10-pcduino.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
- sun5i-a13-olinuxino-micro.dtb \
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-new file mode 100644
-index 0000000..f5692a3
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright 2014 Zoltan HERPAI
-+ * Zoltan HERPAI <wigyori@uid0.hu>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun4i-a10.dtsi"
-+
-+/ {
-+ model = "LinkSprite pcDuino";
-+ compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
-+
-+ soc@01c00000 {
-+ emac: ethernet@01c0b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_pins_a>;
-+ phy = <&phy1>;
-+ status = "okay";
-+ };
-+
-+ mdio@01c0b080 {
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+
-+ uart0: serial@01c28000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+ };
-+
-+ i2c0: i2c@01c2ac00 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c0_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-From 54b9b9ab635ed8e643784402096524768f490f5d Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 11 Jan 2014 04:33:23 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add mmc node to a few more boards
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +++++++++
- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 8 ++++++++
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 8 ++++++++
- 3 files changed, 25 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-index 6692d336..2eb30d0 100644
---- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
-@@ -35,6 +35,15 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ cd-mode = <1>;
-+ status = "okay";
-+ };
-+
- pio: pinctrl@01c20800 {
- pinctrl-names = "default";
- pinctrl-0 = <&hackberry_hogs>;
-diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-index 70b3323..6dbe53c 100644
---- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
-@@ -19,6 +19,14 @@
- compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
-
- soc@01c00000 {
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-index f5692a3..87f7742 100644
---- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -33,6 +33,14 @@
- };
- };
-
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 713c2957f8b9e49b2170c9e546d705c9c358faee Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Mon, 17 Feb 2014 20:41:04 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add USB host nodes to pcduino.dts
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 27 +++++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-index 87f7742..3ccd357 100644
---- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
-@@ -12,6 +12,7 @@
-
- /dts-v1/;
- /include/ "sun4i-a10.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-
- / {
- model = "LinkSprite pcDuino";
-@@ -41,6 +42,32 @@
- status = "okay";
- };
-
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ahci: sata@01c18000 {
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
---
-1.8.5.5
-
+++ /dev/null
-From 75e7218e107016a4baae26c70a81b1111fc8c70b Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Fri, 10 Jan 2014 23:23:06 +0100
-Subject: [PATCH] ARM: sun4i: dt: Add sun4i-a10-olinuxino-lime.dtb
-
-This add support for the A10-OLinuXino-LIME:
-https://www.olimex.com/Products/OLinuXino/A10/A10-OLinuXino-LIME
-
-A low cost Allwinner A10 based dev-board, with sata, ethernet, hdmi and 2x USB.
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 112 +++++++++++++++++++++++++
- 2 files changed, 113 insertions(+)
- create mode 100644 arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 0b127db..c576de8 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -283,6 +283,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
- sun4i-a10-cubieboard.dtb \
- sun4i-a10-mini-xplus.dtb \
- sun4i-a10-hackberry.dtb \
-+ sun4i-a10-olinuxino-lime.dtb \
- sun4i-a10-pcduino.dtb \
- sun5i-a10s-olinuxino-micro.dtb \
- sun5i-a13-olinuxino.dtb \
-diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-new file mode 100644
-index 0000000..3c076f2
---- /dev/null
-+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
-@@ -0,0 +1,112 @@
-+/*
-+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
-+ *
-+ * The code contained herein is licensed under the GNU General Public
-+ * License. You may obtain a copy of the GNU General Public License
-+ * Version 2 or later at the following locations:
-+ *
-+ * http://www.opensource.org/licenses/gpl-license.html
-+ * http://www.gnu.org/copyleft/gpl.html
-+ */
-+
-+/dts-v1/;
-+/include/ "sun4i-a10.dtsi"
-+/include/ "sunxi-ahci-reg.dtsi"
-+/include/ "sun4i-a10-usb-vbus-reg.dtsi"
-+
-+/ {
-+ model = "Olimex A10-OLinuXino-LIME";
-+ compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
-+
-+ soc@01c00000 {
-+ emac: ethernet@01c0b000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emac_pins_a>;
-+ phy = <&phy1>;
-+ status = "okay";
-+ };
-+
-+ mdio@01c0b080 {
-+ status = "okay";
-+
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ };
-+
-+ mmc0: mmc@01c0f000 {
-+ pinctrl-names = "default", "default";
-+ pinctrl-0 = <&mmc0_pins_a>;
-+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
-+ cd-gpios = <&pio 7 1 0>; /* PH1 */
-+ cd-mode = <1>;
-+ status = "okay";
-+ };
-+
-+ usbphy: phy@01c13400 {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ usb2_vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+ };
-+
-+ ehci0: usb@01c14000 {
-+ status = "okay";
-+ };
-+
-+ ohci0: usb@01c14400 {
-+ status = "okay";
-+ };
-+
-+ ahci: sata@01c18000 {
-+ target-supply = <®_ahci_5v>;
-+ status = "okay";
-+ };
-+
-+ ehci1: usb@01c1c000 {
-+ status = "okay";
-+ };
-+
-+ ohci1: usb@01c1c400 {
-+ status = "okay";
-+ };
-+
-+ pinctrl@01c20800 {
-+ ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
-+ allwinner,pins = "PC3";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <0>;
-+ allwinner,pull = <0>;
-+ };
-+
-+ led_pins_olinuxinolime: led_pins@0 {
-+ allwinner,pins = "PH2";
-+ allwinner,function = "gpio_out";
-+ allwinner,drive = <1>;
-+ allwinner,pull = <0>;
-+ };
-+ };
-+
-+ uart0: serial@01c28000 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pins_a>;
-+ status = "okay";
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_pins_olinuxinolime>;
-+
-+ green {
-+ label = "a10-olinuxino-lime:green:usr";
-+ gpios = <&pio 7 2 0>;
-+ default-state = "on";
-+ };
-+ };
-+
-+ reg_ahci_5v: ahci-5v {
-+ pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
-+ gpio = <&pio 2 3 0>;
-+ };
-+};
---
-1.8.5.5
-
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/Makefile new/arch/arm/boot/dts/Makefile
---- old/arch/arm/boot/dts/Makefile 2014-04-26 15:15:01.000000000 +0200
-+++ new/arch/arm/boot/dts/Makefile 2014-04-26 15:46:58.336223315 +0200
-@@ -292,7 +292,8 @@
- sun6i-a31-colombus.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
-- sun7i-a20-olinuxino-micro.dtb
-+ sun7i-a20-olinuxino-micro.dtb \
-+ sun7i-a20-pcduino3.dtb
- dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
- tegra20-iris-512.dtb \
- tegra20-medcom-wide.dtb \
+++ /dev/null
-diff -ruN old/arch/arm/boot/dts/Makefile new/arch/arm/boot/dts/Makefile
---- old/arch/arm/boot/dts/Makefile 2014-04-28 22:20:54.000000000 +0200
-+++ new/arch/arm/boot/dts/Makefile 2014-06-01 17:28:54.187703560 +0200
-@@ -259,6 +259,7 @@
- sun5i-a13-olinuxino.dtb \
- sun5i-a13-olinuxino-micro.dtb \
- sun6i-a31-colombus.dtb \
-+ sun7i-a20-bananapi.dtb \
- sun7i-a20-cubieboard2.dtb \
- sun7i-a20-cubietruck.dtb \
- sun7i-a20-olinuxino-micro.dtb \
projects / openwrt / staging / noltari.git / commitdiff