drm/amd/display: Clear water mark change request bit before programing.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 948aaeb731229f02ce77dea58aaaed725578bf59..9165dc80cd22dcefc5fccb6218312328bf7cfd6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -320,6 +320,9 @@ static void program_watermarks(
         */
        uint32_t prog_wm_value;
 
+       REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+                       DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
+
        /* Repeat for water mark set A, B, C and D. */
        /* clock state A */
        prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
@@ -518,8 +521,7 @@ static void program_watermarks(
 
        REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
                        DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-       REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-                       DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
+
        REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
                        DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
        REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,