arm64: dts: ti: k3-am654: Add interrupt controllers in main domain

Main domain in AM654 has the following interrupt controller instances:
- Main Domain GPIO Interrupt router connected to gpio in main domain.
- Under the Main Domain Navigator Subsystem(NAVSS)
    - Main Navss Interrupt Router connected to main navss inta and mailboxes.
    - Main Navss Interrupt Aggregator connected to main domain UDMASS

Add DT nodes for the above three interrupt controllers available
in main domain.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 752455269fab830da778cd8fda157674687517bc..22154f4019304606dff9be8307386b951a59ca52 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -309,4 +309,45 @@
                clock-names = "wkupclk", "refclk";
                #phy-cells = <0>;
        };
+
+       intr_main_gpio: interrupt-controller0 {
+               compatible = "ti,sci-intr";
+               ti,intr-trigger-type = <1>;
+               interrupt-controller;
+               interrupt-parent = <&gic500>;
+               #interrupt-cells = <2>;
+               ti,sci = <&dmsc>;
+               ti,sci-dst-id = <56>;
+               ti,sci-rm-range-girq = <0x1>;
+       };
+
+       cbass_main_navss: interconnect0 {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               intr_main_navss: interrupt-controller1 {
+                       compatible = "ti,sci-intr";
+                       ti,intr-trigger-type = <4>;
+                       interrupt-controller;
+                       interrupt-parent = <&gic500>;
+                       #interrupt-cells = <2>;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dst-id = <56>;
+                       ti,sci-rm-range-girq = <0x0>, <0x2>;
+               };
+
+               inta_main_udmass: interrupt-controller@33d00000 {
+                       compatible = "ti,sci-inta";
+                       reg = <0x0 0x33d00000 0x0 0x100000>;
+                       interrupt-controller;
+                       interrupt-parent = <&intr_main_navss>;
+                       msi-controller;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <179>;
+                       ti,sci-rm-range-vint = <0x0>;
+                       ti,sci-rm-range-global-event = <0x1>;
+               };
+       };
 };