ARC: [axs10x] Specify reserved memory for frame buffer
authorAlexey Brodkin <abrodkin@synopsys.com>
Wed, 27 Apr 2016 13:59:50 +0000 (16:59 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Fri, 29 Apr 2016 11:34:13 +0000 (14:34 +0300)
Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a range 0x8z-0xAz.

I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.

Even though for AXS101 (which sorts ARC770 CPU) IOC is not
an option for a sake of keeping one DT description for the
base-board (axs10x_mb.dtsi) we're still defining reserved
memory location in the very end of DDR.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Cc: devicetree@vger.kernel.org
arch/arc/boot/dts/axc001.dtsi
arch/arc/boot/dts/axc003.dtsi
arch/arc/boot/dts/axc003_idu.dtsi
arch/arc/boot/dts/axs10x_mb.dtsi

index 420dcfde289fe8fe3e99193df1876d399b0dce04..262496ac2628e1b1721ac11220a9993868065bc5 100644 (file)
        memory {
                #address-cells = <1>;
                #size-cells = <1>;
-               ranges = <0x00000000 0x80000000 0x40000000>;
+               ranges = <0x00000000 0x80000000 0x20000000>;
                device_type = "memory";
-               reg = <0x80000000 0x20000000>;  /* 512MiB */
+               reg = <0x80000000 0x1b000000>;  /* (512 - 32) MiB */
+       };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               /*
+                * We just move frame buffer area to the very end of
+                * available DDR. And even though in case of ARC770 there's
+                * no strict requirement for a frame-buffer to be in any
+                * particular location it allows us to use the same
+                * base board's DT node for ARC PGU as for ARc HS38.
+                */
+               frame_buffer: frame_buffer@9e000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x9e000000 0x2000000>;
+                       no-map;
+               };
        };
 };
index f90fadf7f94e5e51f551d9e914aaad728aa5bc84..35ece04d8353d13a9151642989d1e8fb2cab57b6 100644 (file)
                device_type = "memory";
                reg = <0x80000000 0x20000000>;  /* 512MiB */
        };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               /*
+                * Move frame buffer out of IOC aperture (0x8z-0xAz).
+                */
+               frame_buffer: frame_buffer@be000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0xbe000000 0x2000000>;
+                       no-map;
+               };
+       };
 };
index 06a9f294a2e600a4aa7f8f7b18316ceb60d87ef0..df9ddb623bfe574fc98b7149111ed4a9d73c64f5 100644 (file)
                device_type = "memory";
                reg = <0x80000000 0x20000000>;  /* 512MiB */
        };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               /*
+                * Move frame buffer out of IOC aperture (0x8z-0xAz).
+                */
+               frame_buffer: frame_buffer@be000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0xbe000000 0x2000000>;
+                       no-map;
+               };
+       };
 };
index 823f15ca68df03aa017484974bab80adbd71b66e..64b063d4e9969e61f50247caabab9ed148379845 100644 (file)
                        encoder-slave = <&adv7511>;
                        clocks = <&pguclk>;
                        clock-names = "pxlclk";
-
+                       memory-region = <&frame_buffer>;
                        port {
                                pgu_output: endpoint {
                                        remote-endpoint = <&adv7511_input>;