ralink: update ethernet driver to use new ralink_soc variable
authorJohn Crispin <john@openwrt.org>
Fri, 14 Nov 2014 16:52:52 +0000 (16:52 +0000)
committerJohn Crispin <john@openwrt.org>
Fri, 14 Nov 2014 16:52:52 +0000 (16:52 +0000)
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 43247

target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c

index ae37a0307dac9d79c109f683acf8377163942911..247983b79e29f9b559cfaa4258b37fe6a97ced0b 100644 (file)
 #include <linux/mii.h>
 
 #include <ralink_regs.h>
-#ifdef CONFIG_SOC_MT7620
-static inline int soc_is_rt3352(void)
-{
-       return 0;
-}
-
-static inline int soc_is_mt7628(void)
-{
-       return 1;
-}
-
-static inline int soc_is_rt5350(void)
-{
-       return 0;
-}
-#else
-#include <asm/mach-ralink/rt305x.h>
-static inline int soc_is_mt7628(void)
-{
-       return 0;
-}
-#endif
 
 #include <asm/mach-ralink/rt305x_esw_platform.h>
 
@@ -532,7 +510,7 @@ static void esw_hw_init(struct rt305x_esw *esw)
        for (i = 0; i < 6; i++)
                esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 
-       if (soc_is_rt3352()) {
+       if (ralink_soc == RT305X_SOC_RT3352) {
                /* reset EPHY */
                u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
                rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
@@ -583,7 +561,7 @@ static void esw_hw_init(struct rt305x_esw *esw)
                rt305x_mii_write(esw, 0, 29, 0x598b);
                /* select local register */
                rt305x_mii_write(esw, 0, 31, 0x8000);
-       } else if (soc_is_rt5350()) {
+       } else if (ralink_soc == RT305X_SOC_RT5350) {
                /* reset EPHY */
                u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
                rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
@@ -638,9 +616,9 @@ static void esw_hw_init(struct rt305x_esw *esw)
                rt305x_mii_write(esw, 0, 29, 0x598b);
                /* select local register */
                rt305x_mii_write(esw, 0, 31, 0x8000);
-       } else if (soc_is_mt7628()) {
+       } else if (ralink_soc == MT762X_SOC_MT7628AN) {
                int i;
-               u32 phy_val;
+//             u32 phy_val;
                u32 val;
 
                /* reset EPHY */
@@ -1071,7 +1049,7 @@ esw_get_port_tr_badgood(struct switch_dev *dev,
        int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
        u32 reg;
 
-       if (!soc_is_rt5350() && !soc_is_mt7628())
+       if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN))
                return -EINVAL;
 
        if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
index c406013228cdb254e296f9a9b5116465c1c66879..1ece54855ce1677e15c5fa3f41ad3af375f4f883 100644 (file)
 #include <linux/module.h>
 
 #include <asm/mach-ralink/ralink_regs.h>
-#ifdef CONFIG_SOC_MT7620
-static inline int soc_is_rt3352(void)
-{
-       return 0;
-}
-
-static inline int soc_is_rt3052(void)
-{
-       return 0;
-}
-#else
-#include <asm/mach-ralink/rt305x.h>
-#endif
 
 #include "ralink_soc_eth.h"
 #include "mdio_rt2880.h"
@@ -69,14 +56,14 @@ static int rt3050_fwd_config(struct fe_priv *priv)
 {
        int ret;
 
-       if (soc_is_rt3052()) {
+       if (ralink_soc != RT305X_SOC_RT3052) {
                ret = fe_set_clock_cycle(priv);
                if (ret)
                        return ret;
        }
 
        fe_fwd_config(priv);
-       if (!soc_is_rt3352())
+       if (ralink_soc != RT305X_SOC_RT3352)
                fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
        fe_csum_config(priv);