rockchip: rk3399: improve the m0 enable flow

This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
   poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
   to the M0 clock.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 77cb07f8a55ea70296d6374b13a9a7b135c2f492..3932b4cd0adeab12751f3289b7d60d0a9258796f 100644 (file)
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1961,6 +1961,7 @@ static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index)
        mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz);
 
        mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4);
+       dmbst();
 }
 
 static uint32_t prepare_ddr_timing(uint32_t mhz)
@@ -2032,6 +2033,10 @@ uint32_t ddr_set_rate(uint32_t hz)
        if (ddr_index > 1)
                goto out;
 
+       /*
+        * Make sure the clock is enabled. The M0 clocks should be on all of the
+        * time during S0.
+        */
        m0_configure_ddr(dpll_rates_table[index], ddr_index);
        m0_start();
        m0_wait_done();

diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
index 6f9a25cd66560d544584527639df337c08eb86c9..11bc0eaefb18638cd302ba88fff58181a6ac90a6 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
+++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
@@ -53,7 +53,7 @@ void m0_init(void)
                                      0xf, 0));
 
        /* gating disable for M0 */
-       mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1));
+       mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(0));
 
        /*
         * To switch the parent to xin24M and div == 1,
@@ -65,21 +65,28 @@ void m0_init(void)
         */
        mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
                      BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
+
+       mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
 }
 
 void m0_start(void)
 {
+       /* enable clocks for M0 */
+       mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
+                     BITS_WITH_WMASK(0x0, 0xf, 0));
+
        /* clean the PARAM_M0_DONE flag, mean that M0 will start working */
        mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
        dmbst();
 
-       /* enable clocks for M0 */
-       mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
-                     BITS_WITH_WMASK(0x0, 0x2f, 0));
+       mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
+                     BITS_WITH_WMASK(0x0, 0x4, 0));
 
+       udelay(5);
        /* start M0 */
        mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
-                     BITS_WITH_WMASK(0x0, 0x24, 0));
+                     BITS_WITH_WMASK(0x0, 0x20, 0));
+       dmbst();
 }
 
 void m0_stop(void)
@@ -90,17 +97,24 @@ void m0_stop(void)
 
        /* disable clocks for M0 */
        mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
-                     BITS_WITH_WMASK(0x2f, 0x2f, 0));
+                     BITS_WITH_WMASK(0xf, 0xf, 0));
 }
 
 void m0_wait_done(void)
 {
-       while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG) {
+       do {
                /*
                 * Don't starve the M0 for access to SRAM, so delay before
                 * reading the PARAM_M0_DONE value again.
                 */
                udelay(5);
                dsb();
-       }
+       } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
+
+       /*
+        * Let the M0 settle into WFI before we leave. This is so we don't reset
+        * the M0 in a bad spot which can cause problems with the M0.
+        */
+       udelay(10);
+       dsb();
 }

diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h
index fcee9b0ce4b1811ab68e6b44d884c4d6adaa5dd4..c21caab1a0365be2ae4e11435165726578aa0808 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h
+++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h
@@ -44,5 +44,4 @@ extern void m0_init(void);
 extern void m0_start(void);
 extern void m0_stop(void);
 extern void m0_wait_done(void);
-
 #endif /* __M0_CTL_H__ */

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index b8afd387acf3f5768f5f1fff9aeba18d71ca342f..cd3987e1e7fef5118fbecc00c82e379b58f48911 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1218,7 +1218,6 @@ static int sys_pwr_domain_resume(void)
                                BIT(PMU_CLR_GIC));
 
        plat_rockchip_gic_cpuif_enable();
-
        m0_stop();
 
        ddr_prepare_for_sys_resume();