powerpc/p2041rdb: add NAND and NAND boot support

New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/boards.cfg b/boards.cfg
index 3cf75c3151b0c7be6c91405661c962c78002ca3c..1986da9cd9bea36d14476ceb81de1734a857bf41 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -742,6 +742,7 @@ P2020RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
 P2041RDB                     powerpc     mpc85xx     p2041rdb            freescale
+P2041RDB_NAND               powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SDCARD              powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SECURE_BOOT         powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:SECURE_BOOT
 P2041RDB_SPIFLASH            powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index da98f8f027481cda6336239580031c2df693ff31..501726ca4cbe29c076909b353560746bda76c1f1 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -186,10 +186,11 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM \
+#define CONFIG_SYS_FLASH_BR_PRELIM \
                (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
-                               | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+#define CONFIG_SYS_FLASH_OR_PRELIM \
+               ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+                | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_FSL_CPLD
 #define CPLD_BASE              0xffdf0000      /* CPLD registers */
@@ -221,6 +222,53 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
+#define CONFIG_NAND_FSL_ELBC
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS      0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                              | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                              | BR_PS_8               /* Port Size = 8 bit */ \
+                              | BR_MS_FCM             /* MSEL = FCM */ \
+                              | BR_V)                 /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000       /* length 256K */ \
+                              | OR_FCM_PGS            /* Large Page*/ \
+                              | OR_FCM_CSCT \
+                              | OR_FCM_CST \
+                              | OR_FCM_CHT \
+                              | OR_FCM_SCY_1 \
+                              | OR_FCM_TRLX \
+                              | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}