net: stmmac: ARP Offload for GMAC4+ Cores
authorJose Abreu <Jose.Abreu@synopsys.com>
Tue, 10 Sep 2019 14:41:27 +0000 (16:41 +0200)
committerDavid S. Miller <davem@davemloft.net>
Wed, 11 Sep 2019 08:21:34 +0000 (09:21 +0100)
Implement the ARP Offload feature in GMAC4 and GMAC5 cores.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c

index e88dac1dd765e90aaf4b82f6e3476697f1c838dd..89a3420eba421ad41dd99fb5dd7f67d940ef1b4b 100644 (file)
@@ -40,6 +40,7 @@
 #define GMAC_HW_FEATURE3               0x00000128
 #define GMAC_MDIO_ADDR                 0x00000200
 #define GMAC_MDIO_DATA                 0x00000204
+#define GMAC_ARP_ADDR                  0x00000210
 #define GMAC_ADDR_HIGH(reg)            (0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg)             (0x304 + reg * 8)
 
@@ -165,6 +166,7 @@ enum power_event {
 #define GMAC_DEBUG_RPESTS              BIT(0)
 
 /* MAC config */
+#define GMAC_CONFIG_ARPEN              BIT(31)
 #define GMAC_CONFIG_SARC               GENMASK(30, 28)
 #define GMAC_CONFIG_SARC_SHIFT         28
 #define GMAC_CONFIG_IPC                        BIT(27)
@@ -188,6 +190,7 @@ enum power_event {
 #define GMAC_HW_FEAT_TXCOSEL           BIT(14)
 #define GMAC_HW_FEAT_EEESEL            BIT(13)
 #define GMAC_HW_FEAT_TSSEL             BIT(12)
+#define GMAC_HW_FEAT_ARPOFFSEL         BIT(9)
 #define GMAC_HW_FEAT_MMCSEL            BIT(8)
 #define GMAC_HW_FEAT_MGKSEL            BIT(7)
 #define GMAC_HW_FEAT_RWKSEL            BIT(6)
index a99effe6132558c325a669e46af032c70aaf5a01..9b4b5f69fc0211995591f772f9e8f1bf4dea2ae8 100644 (file)
@@ -782,6 +782,22 @@ static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
        writel(value, ioaddr + GMAC_VLAN_INCL);
 }
 
+static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
+                                  u32 addr)
+{
+       void __iomem *ioaddr = hw->pcsr;
+       u32 value;
+
+       writel(addr, ioaddr + GMAC_ARP_ADDR);
+
+       value = readl(ioaddr + GMAC_CONFIG);
+       if (en)
+               value |= GMAC_CONFIG_ARPEN;
+       else
+               value &= ~GMAC_CONFIG_ARPEN;
+       writel(value, ioaddr + GMAC_CONFIG);
+}
+
 const struct stmmac_ops dwmac4_ops = {
        .core_init = dwmac4_core_init,
        .set_mac = stmmac_set_mac,
@@ -815,6 +831,7 @@ const struct stmmac_ops dwmac4_ops = {
        .update_vlan_hash = dwmac4_update_vlan_hash,
        .sarc_configure = dwmac4_sarc_configure,
        .enable_vlan = dwmac4_enable_vlan,
+       .set_arp_offload = dwmac4_set_arp_offload,
 };
 
 const struct stmmac_ops dwmac410_ops = {
@@ -850,6 +867,7 @@ const struct stmmac_ops dwmac410_ops = {
        .update_vlan_hash = dwmac4_update_vlan_hash,
        .sarc_configure = dwmac4_sarc_configure,
        .enable_vlan = dwmac4_enable_vlan,
+       .set_arp_offload = dwmac4_set_arp_offload,
 };
 
 const struct stmmac_ops dwmac510_ops = {
@@ -890,6 +908,7 @@ const struct stmmac_ops dwmac510_ops = {
        .update_vlan_hash = dwmac4_update_vlan_hash,
        .sarc_configure = dwmac4_sarc_configure,
        .enable_vlan = dwmac4_enable_vlan,
+       .set_arp_offload = dwmac4_set_arp_offload,
 };
 
 int dwmac4_setup(struct stmmac_priv *priv)
index f3ca0236450d71f3ddb8c51c5695a909e668faa6..68c157979b947be5f9c0a1d3847646362ec37957 100644 (file)
@@ -349,6 +349,7 @@ static void dwmac4_get_hw_feature(void __iomem *ioaddr,
        dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
        dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
        dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
+       dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
 
        /* MAC HW feature1 */
        hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);