OMAP242x fix for GP device booting

- Add SRAM unlock for GP devices.
- Change DDR DLL unlock value to allow DPLLout*1 operation.
Patches by Richard Woodruff, 21 Jan 2005:

diff --git a/CHANGELOG b/CHANGELOG
index 6569616d57f9fafd5de8f4ee94dd478bf0933cb6..16421a43875ab0fe6ad2d2a86b0e9d0545ef4192 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* OMAP242x fix for GP device booting
+  - Add SRAM unlock for GP devices.
+  - Change DDR DLL unlock value to allow DPLLout*1 operation.
+  Patches by Richard Woodruff, 21 Jan 2005:
+
 * Add support for AMD's Pb1x00 eval board;
   add MII routines to the au1x00 ethernet driver;
   add USB ohci driver (work in progress)

diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
index 8c7982d679ae866abb1213258156d3c2fce444e8..a6543951f165a84821f76ed9943feb39116bd7f1 100644 (file)
--- a/board/omap2420h4/omap2420h4.c
+++ b/board/omap2420h4/omap2420h4.c
@@ -64,6 +64,24 @@ int board_init (void)
        return 0;
 }
 
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ *  general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+       int mode;
+
+       /* if GP device unlock device SRAM for general use */
+       mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
+       if (mode == GP_DEVICE) {
+               __raw_writel(0xFF, A_REQINFOPERM0);
+               __raw_writel(0xCFDE, A_READPERM0);
+               __raw_writel(0xCFDE, A_WRITEPERM0);
+       }
+}
+
 /**********************************************************
  * Routine: s_init
  * Description: Does early system init of muxing and clocks.
@@ -76,6 +94,7 @@ void s_init(void)
        watchdog_init();
        set_muxconf_regs();
        delay(100);
+       try_unlock_sram();
 
        if(!in_sdram)
                prcm_init();
@@ -102,20 +121,10 @@ int misc_init_r (void)
  *****************************************/
 void watchdog_init(void)
 {
-       int mode;
-       #define GP (BIT8|BIT9)
-
        /* There are 4 watch dogs.  1 secure, and 3 general purpose.
-        * I would expect that the ROM takes care of the secure one,
-        * but we will try also.  Of the 3 GP ones, 1 can reset us
-        * directly, the other 2 only generate MPU interrupts.
-        */
-       mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
-       if (mode == GP) {
-               __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
-               wait_for_command_complete(WD1_BASE);
-               __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
-       }
+       * The ROM takes care of the secure one. Of the 3 GP ones, 
+       * 1 can reset us directly, the other 2 only generate MPU interrupts.
+       */
        __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
        wait_for_command_complete(WD2_BASE);
        __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);

diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h
index 2ead7d83b9b7bda34b0cebf245fd6e4dac123e95..dfaf56876935fef02c46664f331c731a8fe46deb 100644 (file)
--- a/include/asm-arm/arch-arm1136/mem.h
+++ b/include/asm-arm/arch-arm1136/mem.h
@@ -68,8 +68,8 @@ typedef enum {
 # define H4_2420_SDRC_RFR_CTRL_ES1     0x00002401
 # define H4_2420_SDRC_RFR_CTRL         0x0002da01
 #endif
-#define H4_2420_SDRC_DLLA_CTRL         0x00007307 /* load value at 100Mhz */
-#define H4_2420_SDRC_DLLB_CTRL         0x00007307
+#define H4_2420_SDRC_DLLA_CTRL         0x0000E307 /* DLL value used for 50MHz */
+#define H4_2420_SDRC_DLLB_CTRL         0x0000E307 /* allow DPLLout*1 to work */
 
 #define H4_2422_SDRC_SHARING           0x00004b00
 #define H4_2422_SDRC_MDCFG_0_DDR       0x00801011 /* stacked ddr on 2422 */

diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index a2a97981b6cd4325d50a4b050ccdd173e02cce70..eba385cea322e7721df548f86ed386d32a8db4dd 100644 (file)
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -31,6 +31,12 @@
  * 2420 specific Section
  */
 
+/* L3 Firewall */
+#define A_REQINFOPERM0        0x68005048
+#define A_READPERM0           0x68005050
+#define A_WRITEPERM0          0x68005058
+#define GP_DEVICE             (BIT8|BIT9)
+
 /* CONTROL */
 #define OMAP2420_CTRL_BASE    (0x48000000)
 #define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)