drm/amd/display: clean up set_bandwidth usage

This removes redundant set_bandwidth calls as well
as fixes a bug in post_set_address_update where dcn1
would never get to lower clocks.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 53ce7fa864b4f6173a8989223e3b77c1ab06a61b..2a785bbf2b8f1de5011ede286cfee2d229556c36 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -944,12 +944,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 
        dc->optimized_required = false;
 
-       /* 3rd param should be true, temp w/a for RV*/
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-       dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0);
-#else
        dc->hwss.set_bandwidth(dc, context, true);
-#endif
        return true;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4cdf86690d19d38ca52613aa7fa9a1067b94f28a..3b983b3f342342cd55f9e5b80d11d91577f0abe3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2036,8 +2036,6 @@ enum dc_status dce110_apply_ctx_to_hw(
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
 
-       dc->hwss.set_bandwidth(dc, context, false);
-
        dce110_setup_audio_dto(dc, context);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2066,9 +2064,6 @@ enum dc_status dce110_apply_ctx_to_hw(
                        return status;
        }
 
-       /* to save power */
-       dc->hwss.set_bandwidth(dc, context, true);
-
        dcb->funcs->set_scratch_critical_state(dcb, false);
 
        if (dc->fbc_compressor)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 60e99477930b1441fbe76ef9bd37c2f73c1ac744..08809b0ff6bfd8725762075bbbfdc11425a810b0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2268,8 +2268,7 @@ static void dcn10_apply_ctx_for_surface(
                        hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);
                        removed_pipe[i] = true;
 
-                       DC_LOG_DC(
-                                       "Reset mpcc for pipe %d\n",
+                       DC_LOG_DC("Reset mpcc for pipe %d\n",
                                        old_pipe_ctx->pipe_idx);
                }
        }
@@ -2365,9 +2364,8 @@ static void dcn10_set_bandwidth(
                struct dc_state *context,
                bool decrease_allowed)
 {
-       if (dc->debug.sanity_checks) {
+       if (dc->debug.sanity_checks)
                dcn10_verify_allow_pstate_change_high(dc);
-       }
 
        if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
                return;
@@ -2382,11 +2380,8 @@ static void dcn10_set_bandwidth(
 
        dcn10_pplib_apply_display_requirements(dc, context);
 
-       if (dc->debug.sanity_checks) {
+       if (dc->debug.sanity_checks)
                dcn10_verify_allow_pstate_change_high(dc);
-       }
-
-       /* need to fix this function.  not doing the right thing here */
 }
 
 static void set_drr(struct pipe_ctx **pipe_ctx,