ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database
authorVaibhav Hiremath <hvaibhav@ti.com>
Tue, 8 May 2012 17:34:30 +0000 (11:34 -0600)
committerPaul Walmsley <paul@pwsan.com>
Tue, 8 May 2012 23:25:36 +0000 (17:25 -0600)
Add 32k-sync timer hwmod-data and add ocp_if details to
omap2 & 3 hwmod table.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/omap_hwmod_2420_data.c
arch/arm/mach-omap2/omap_hwmod_2430_data.c
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
arch/arm/mach-omap2/omap_hwmod_common_data.h

index 85419f86b280ef9b13d03424647e8c99dd0c5b6c..a7640d1b215e7f94f5dc8fea09738930d75a0208 100644 (file)
@@ -519,6 +519,24 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 };
 
 
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
+       {
+               .pa_start       = 0x48004000,
+               .pa_end         = 0x4800401f,
+               .flags          = ADDR_TYPE_RT
+       },
+       { }
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
+       .master         = &omap2xxx_l4_wkup_hwmod,
+       .slave          = &omap2xxx_counter_32k_hwmod,
+       .clk            = "sync_32k_ick",
+       .addr           = omap2420_counter_32k_addrs,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
        &omap2xxx_l3_main__l4_core,
        &omap2xxx_mpu__l3_main,
@@ -561,6 +579,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
        &omap2420_l4_core__mcbsp2,
        &omap2420_l4_core__msdi1,
        &omap2420_l4_core__hdq1w,
+       &omap2420_l4_wkup__counter_32k,
        NULL,
 };
 
index ff93a8dbf427c3fb85ab508e9e0da37b1dced525..4d72649812303cddc2c1eeb73f6bee3bcd4c4027 100644 (file)
@@ -865,6 +865,24 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
 
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
+       {
+               .pa_start       = 0x49020000,
+               .pa_end         = 0x4902001f,
+               .flags          = ADDR_TYPE_RT
+       },
+       { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
+       .master         = &omap2xxx_l4_wkup_hwmod,
+       .slave          = &omap2xxx_counter_32k_hwmod,
+       .clk            = "sync_32k_ick",
+       .addr           = omap2430_counter_32k_addrs,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
        &omap2xxx_l3_main__l4_core,
        &omap2xxx_mpu__l3_main,
@@ -914,6 +932,7 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
        &omap2430_l4_core__mcbsp4,
        &omap2430_l4_core__mcbsp5,
        &omap2430_l4_core__hdq1w,
+       &omap2430_l4_wkup__counter_32k,
        NULL,
 };
 
index 45aaa07e3025b4684d7b27767538616fd7045148..5941f14130a1717625e16f5197e7a267355309c5 100644 (file)
@@ -732,3 +732,23 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
 };
+
+
+static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
+       .name   = "counter",
+};
+
+struct omap_hwmod omap2xxx_counter_32k_hwmod = {
+       .name           = "counter_32k",
+       .main_clk       = "func_32k_ck",
+       .prcm           = {
+               .omap2  = {
+                       .module_offs = WKUP_MOD,
+                       .prcm_reg_id = 1,
+                       .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+                       .idlest_reg_id = 1,
+                       .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+               },
+       },
+       .class          = &omap2xxx_counter_hwmod_class,
+};
index 87742e20cd5fe6193b002f54e9d2a37330d690f0..2432574123c69622a10e94990e3eef110d1478e9 100644 (file)
@@ -1996,6 +1996,40 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
        .class          = &omap2_hdq1w_class,
 };
 
+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
+       .rev_offs       = 0x0000,
+       .sysc_offs      = 0x0004,
+       .sysc_flags     = SYSC_HAS_SIDLEMODE,
+       .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+       .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
+       .name   = "counter",
+       .sysc   = &omap3xxx_counter_sysc,
+};
+
+static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
+       .name           = "counter_32k",
+       .class          = &omap3xxx_counter_hwmod_class,
+       .clkdm_name     = "wkup_clkdm",
+       .flags          = HWMOD_SWSUP_SIDLE,
+       .main_clk       = "wkup_32k_fck",
+       .prcm           = {
+               .omap2  = {
+                       .module_offs = WKUP_MOD,
+                       .prcm_reg_id = 1,
+                       .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
+                       .idlest_reg_id = 1,
+                       .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
+               },
+       },
+};
+
 /*
  * interfaces
  */
@@ -3085,6 +3119,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
 
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
+       {
+               .pa_start       = 0x48320000,
+               .pa_end         = 0x4832001f,
+               .flags          = ADDR_TYPE_RT
+       },
+       { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
+       .master         = &omap3xxx_l4_wkup_hwmod,
+       .slave          = &omap3xxx_counter_32k_hwmod,
+       .clk            = "omap_32ksync_ick",
+       .addr           = omap3xxx_counter_32k_addrs,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
        &omap3xxx_l3_main__l4_core,
        &omap3xxx_l3_main__l4_per,
@@ -3129,6 +3181,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
        &omap34xx_l4_core__mcspi2,
        &omap34xx_l4_core__mcspi3,
        &omap34xx_l4_core__mcspi4,
+       &omap3xxx_l4_wkup__counter_32k,
        NULL,
 };
 
index e244829308bde19d136f302061c7eddde029f5ce..e7e8eeae95e5d08ac9ea6d58c377e0505920a1ec 100644 (file)
@@ -75,6 +75,7 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod;
 extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
+extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;