void (*inquire_remote_apic)(int apicid);
};
-extern struct genapic *genapic;
+extern struct genapic *apic;
#ifdef CONFIG_X86_32
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
-#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
-#define INT_DEST_MODE (genapic->int_dest_mode)
-#define TARGET_CPUS (genapic->target_cpus())
-#define apic_id_registered (genapic->apic_id_registered)
-#define init_apic_ldr (genapic->init_apic_ldr)
-#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
-#define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
-#define phys_pkg_id (genapic->phys_pkg_id)
-#define vector_allocation_domain (genapic->vector_allocation_domain)
+#define INT_DELIVERY_MODE (apic->int_delivery_mode)
+#define INT_DEST_MODE (apic->int_dest_mode)
+#define TARGET_CPUS (apic->target_cpus())
+#define apic_id_registered (apic->apic_id_registered)
+#define init_apic_ldr (apic->init_apic_ldr)
+#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
+#define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
+#define phys_pkg_id (apic->phys_pkg_id)
+#define vector_allocation_domain (apic->vector_allocation_domain)
#define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
-#define send_IPI_self (genapic->send_IPI_self)
-#define wakeup_secondary_cpu (genapic->wakeup_cpu)
+#define send_IPI_self (apic->send_IPI_self)
+#define wakeup_secondary_cpu (apic->wakeup_cpu)
extern void setup_apic_routing(void);
#else
#define INT_DELIVERY_MODE dest_LowestPrio
#include <asm/apic.h>
#ifdef CONFIG_X86_64
-#define APIC_ID_MASK (genapic->apic_id_mask)
-#define GET_APIC_ID(x) (genapic->get_apic_id(x))
-#define SET_APIC_ID(x) (genapic->set_apic_id(x))
+#define APIC_ID_MASK (apic->apic_id_mask)
+#define GET_APIC_ID(x) (apic->get_apic_id(x))
+#define SET_APIC_ID(x) (apic->set_apic_id(x))
#else
#define APIC_ID_MASK (0xF<<24)
static inline unsigned get_apic_id(unsigned long x)
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
-#define send_IPI_mask (genapic->send_IPI_mask)
-#define send_IPI_mask_allbutself (genapic->send_IPI_mask_allbutself)
+#define send_IPI_mask (apic->send_IPI_mask)
+#define send_IPI_mask_allbutself (apic->send_IPI_mask_allbutself)
#else
static inline void send_IPI_mask(const struct cpumask *mask, int vector)
{
}
#ifdef CONFIG_X86_64
-#define send_IPI_allbutself (genapic->send_IPI_allbutself)
-#define send_IPI_all (genapic->send_IPI_all)
+#define send_IPI_allbutself (apic->send_IPI_allbutself)
+#define send_IPI_all (apic->send_IPI_all)
#else
static inline void send_IPI_allbutself(int vector)
{
#include <asm/genapic.h>
-#define esr_disable (genapic->ESR_DISABLE)
-#define NO_BALANCE_IRQ (genapic->no_balance_irq)
-#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
-#define INT_DEST_MODE (genapic->int_dest_mode)
+#define esr_disable (apic->ESR_DISABLE)
+#define NO_BALANCE_IRQ (apic->no_balance_irq)
+#define INT_DELIVERY_MODE (apic->int_delivery_mode)
+#define INT_DEST_MODE (apic->int_dest_mode)
#undef APIC_DEST_LOGICAL
-#define APIC_DEST_LOGICAL (genapic->apic_destination_logical)
-#define TARGET_CPUS (genapic->target_cpus())
-#define apic_id_registered (genapic->apic_id_registered)
-#define init_apic_ldr (genapic->init_apic_ldr)
-#define ioapic_phys_id_map (genapic->ioapic_phys_id_map)
-#define setup_apic_routing (genapic->setup_apic_routing)
-#define multi_timer_check (genapic->multi_timer_check)
-#define apicid_to_node (genapic->apicid_to_node)
-#define cpu_to_logical_apicid (genapic->cpu_to_logical_apicid)
-#define cpu_present_to_apicid (genapic->cpu_present_to_apicid)
-#define apicid_to_cpu_present (genapic->apicid_to_cpu_present)
-#define setup_portio_remap (genapic->setup_portio_remap)
-#define check_apicid_present (genapic->check_apicid_present)
-#define check_phys_apicid_present (genapic->check_phys_apicid_present)
-#define check_apicid_used (genapic->check_apicid_used)
-#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
-#define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
-#define vector_allocation_domain (genapic->vector_allocation_domain)
-#define enable_apic_mode (genapic->enable_apic_mode)
-#define phys_pkg_id (genapic->phys_pkg_id)
-#define wakeup_secondary_cpu (genapic->wakeup_cpu)
+#define APIC_DEST_LOGICAL (apic->apic_destination_logical)
+#define TARGET_CPUS (apic->target_cpus())
+#define apic_id_registered (apic->apic_id_registered)
+#define init_apic_ldr (apic->init_apic_ldr)
+#define ioapic_phys_id_map (apic->ioapic_phys_id_map)
+#define setup_apic_routing (apic->setup_apic_routing)
+#define multi_timer_check (apic->multi_timer_check)
+#define apicid_to_node (apic->apicid_to_node)
+#define cpu_to_logical_apicid (apic->cpu_to_logical_apicid)
+#define cpu_present_to_apicid (apic->cpu_present_to_apicid)
+#define apicid_to_cpu_present (apic->apicid_to_cpu_present)
+#define setup_portio_remap (apic->setup_portio_remap)
+#define check_apicid_present (apic->check_apicid_present)
+#define check_phys_apicid_present (apic->check_phys_apicid_present)
+#define check_apicid_used (apic->check_apicid_used)
+#define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
+#define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
+#define vector_allocation_domain (apic->vector_allocation_domain)
+#define enable_apic_mode (apic->enable_apic_mode)
+#define phys_pkg_id (apic->phys_pkg_id)
+#define wakeup_secondary_cpu (apic->wakeup_cpu)
extern void generic_bigsmp_probe(void);
#ifndef APIC_DEFINITION
#include <asm/genapic.h>
-#define GET_APIC_ID (genapic->get_apic_id)
-#define APIC_ID_MASK (genapic->apic_id_mask)
+#define GET_APIC_ID (apic->get_apic_id)
+#define APIC_ID_MASK (apic->apic_id_mask)
#endif
#endif /* _ASM_X86_MACH_GENERIC_MACH_APICDEF_H */
#include <asm/genapic.h>
-#define send_IPI_mask (genapic->send_IPI_mask)
-#define send_IPI_allbutself (genapic->send_IPI_allbutself)
-#define send_IPI_all (genapic->send_IPI_all)
+#define send_IPI_mask (apic->send_IPI_mask)
+#define send_IPI_allbutself (apic->send_IPI_allbutself)
+#define send_IPI_all (apic->send_IPI_all)
#endif /* _ASM_X86_MACH_GENERIC_MACH_IPI_H */
#ifndef _ASM_X86_MACH_GENERIC_MACH_WAKECPU_H
#define _ASM_X86_MACH_GENERIC_MACH_WAKECPU_H
-#define TRAMPOLINE_PHYS_LOW (genapic->trampoline_phys_low)
-#define TRAMPOLINE_PHYS_HIGH (genapic->trampoline_phys_high)
-#define wait_for_init_deassert (genapic->wait_for_init_deassert)
-#define smp_callin_clear_local_apic (genapic->smp_callin_clear_local_apic)
-#define store_NMI_vector (genapic->store_NMI_vector)
-#define restore_NMI_vector (genapic->restore_NMI_vector)
-#define inquire_remote_apic (genapic->inquire_remote_apic)
+#define TRAMPOLINE_PHYS_LOW (apic->trampoline_phys_low)
+#define TRAMPOLINE_PHYS_HIGH (apic->trampoline_phys_high)
+#define wait_for_init_deassert (apic->wait_for_init_deassert)
+#define smp_callin_clear_local_apic (apic->smp_callin_clear_local_apic)
+#define store_NMI_vector (apic->store_NMI_vector)
+#define restore_NMI_vector (apic->restore_NMI_vector)
+#define inquire_remote_apic (apic->inquire_remote_apic)
#endif /* _ASM_X86_MACH_GENERIC_MACH_APIC_H */
static int __init es7000_update_genapic(void)
{
- genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+ apic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
/* MPENTIUMIII */
if (boot_cpu_data.x86 == 6 &&
(boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11)) {
es7000_update_genapic_to_cluster();
- genapic->wait_for_init_deassert = noop_wait_for_deassert;
- genapic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
+ apic->wait_for_init_deassert = noop_wait_for_deassert;
+ apic->wakeup_cpu = wakeup_secondary_cpu_via_mip;
}
return 0;
extern struct genapic apic_x2apic_phys;
extern struct genapic apic_x2apic_cluster;
-struct genapic __read_mostly *genapic = &apic_flat;
+struct genapic __read_mostly *apic = &apic_flat;
static struct genapic *apic_probe[] __initdata = {
#ifdef CONFIG_X86_UV
*/
void __init setup_apic_routing(void)
{
- if (genapic == &apic_x2apic_phys || genapic == &apic_x2apic_cluster) {
+ if (apic == &apic_x2apic_phys || apic == &apic_x2apic_cluster) {
if (!intr_remapping_enabled)
- genapic = &apic_flat;
+ apic = &apic_flat;
}
- if (genapic == &apic_flat) {
+ if (apic == &apic_flat) {
if (max_physical_apicid >= 8)
- genapic = &apic_physflat;
- printk(KERN_INFO "Setting APIC routing to %s\n", genapic->name);
+ apic = &apic_physflat;
+ printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
}
if (x86_quirks->update_genapic)
for (i = 0; apic_probe[i]; ++i) {
if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
- genapic = apic_probe[i];
+ apic = apic_probe[i];
printk(KERN_INFO "Setting APIC routing to %s.\n",
- genapic->name);
+ apic->name);
return 1;
}
}
handle_edge_irq, "edge");
}
-static int setup_ioapic_entry(int apic, int irq,
+static int setup_ioapic_entry(int apic_id, int irq,
struct IO_APIC_route_entry *entry,
unsigned int destination, int trigger,
int polarity, int vector)
#ifdef CONFIG_INTR_REMAP
if (intr_remapping_enabled) {
- struct intel_iommu *iommu = map_ioapic_to_ir(apic);
+ struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
struct irte irte;
struct IR_IO_APIC_route_entry *ir_entry =
(struct IR_IO_APIC_route_entry *) entry;
int index;
if (!iommu)
- panic("No mapping iommu for ioapic %d\n", apic);
+ panic("No mapping iommu for ioapic %d\n", apic_id);
index = alloc_irte(iommu, irq, 1);
if (index < 0)
- panic("Failed to allocate IRTE for ioapic %d\n", apic);
+ panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
memset(&irte, 0, sizeof(irte));
return 0;
}
-static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
+static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
int trigger, int polarity)
{
struct irq_cfg *cfg;
apic_printk(APIC_VERBOSE,KERN_DEBUG
"IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
"IRQ %d Mode:%i Active:%i)\n",
- apic, mp_ioapics[apic].apicid, pin, cfg->vector,
+ apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
irq, trigger, polarity);
- if (setup_ioapic_entry(mp_ioapics[apic].apicid, irq, &entry,
+ if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
dest, trigger, polarity, cfg->vector)) {
printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
- mp_ioapics[apic].apicid, pin);
+ mp_ioapics[apic_id].apicid, pin);
__clear_irq_vector(irq, cfg);
return;
}
if (irq < NR_IRQS_LEGACY)
disable_8259A_irq(irq);
- ioapic_write_entry(apic, pin, entry);
+ ioapic_write_entry(apic_id, pin, entry);
}
static void __init setup_IO_APIC_irqs(void)
{
- int apic, pin, idx, irq;
+ int apic_id, pin, idx, irq;
int notcon = 0;
struct irq_desc *desc;
struct irq_cfg *cfg;
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
- for (apic = 0; apic < nr_ioapics; apic++) {
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
+ for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
- idx = find_irq_entry(apic, pin, mp_INT);
+ idx = find_irq_entry(apic_id, pin, mp_INT);
if (idx == -1) {
if (!notcon) {
notcon = 1;
apic_printk(APIC_VERBOSE,
KERN_DEBUG " %d-%d",
- mp_ioapics[apic].apicid, pin);
+ mp_ioapics[apic_id].apicid, pin);
} else
apic_printk(APIC_VERBOSE, " %d-%d",
- mp_ioapics[apic].apicid, pin);
+ mp_ioapics[apic_id].apicid, pin);
continue;
}
if (notcon) {
notcon = 0;
}
- irq = pin_2_irq(idx, apic, pin);
+ irq = pin_2_irq(idx, apic_id, pin);
#ifdef CONFIG_X86_32
- if (multi_timer_check(apic, irq))
+ if (multi_timer_check(apic_id, irq))
continue;
#endif
desc = irq_to_desc_alloc_cpu(irq, cpu);
continue;
}
cfg = desc->chip_data;
- add_pin_to_irq_cpu(cfg, cpu, apic, pin);
+ add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
- setup_IO_APIC_irq(apic, pin, irq, desc,
+ setup_IO_APIC_irq(apic_id, pin, irq, desc,
irq_trigger(idx), irq_polarity(idx));
}
}
/*
* Set up the timer pin, possibly with the 8259A-master behind.
*/
-static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
+static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
int vector)
{
struct IO_APIC_route_entry entry;
/*
* Add it to the IO-APIC irq-routing table:
*/
- ioapic_write_entry(apic, pin, entry);
+ ioapic_write_entry(apic_id, pin, entry);
}
{
union IO_APIC_reg_00 reg_00;
physid_mask_t phys_id_present_map;
- int apic;
+ int apic_id;
int i;
unsigned char old_id;
unsigned long flags;
/*
* Set the IOAPIC ID to the value stored in the MPC table.
*/
- for (apic = 0; apic < nr_ioapics; apic++) {
+ for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
/* Read the register 0 value */
spin_lock_irqsave(&ioapic_lock, flags);
- reg_00.raw = io_apic_read(apic, 0);
+ reg_00.raw = io_apic_read(apic_id, 0);
spin_unlock_irqrestore(&ioapic_lock, flags);
- old_id = mp_ioapics[apic].apicid;
+ old_id = mp_ioapics[apic_id].apicid;
- if (mp_ioapics[apic].apicid >= get_physical_broadcast()) {
+ if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
- apic, mp_ioapics[apic].apicid);
+ apic_id, mp_ioapics[apic_id].apicid);
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
reg_00.bits.ID);
- mp_ioapics[apic].apicid = reg_00.bits.ID;
+ mp_ioapics[apic_id].apicid = reg_00.bits.ID;
}
/*
* 'stuck on smp_invalidate_needed IPI wait' messages.
*/
if (check_apicid_used(phys_id_present_map,
- mp_ioapics[apic].apicid)) {
+ mp_ioapics[apic_id].apicid)) {
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
- apic, mp_ioapics[apic].apicid);
+ apic_id, mp_ioapics[apic_id].apicid);
for (i = 0; i < get_physical_broadcast(); i++)
if (!physid_isset(i, phys_id_present_map))
break;
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
i);
physid_set(i, phys_id_present_map);
- mp_ioapics[apic].apicid = i;
+ mp_ioapics[apic_id].apicid = i;
} else {
physid_mask_t tmp;
- tmp = apicid_to_cpu_present(mp_ioapics[apic].apicid);
+ tmp = apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
apic_printk(APIC_VERBOSE, "Setting %d in the "
"phys_id_present_map\n",
- mp_ioapics[apic].apicid);
+ mp_ioapics[apic_id].apicid);
physids_or(phys_id_present_map, phys_id_present_map, tmp);
}
* We need to adjust the IRQ routing table
* if the ID changed.
*/
- if (old_id != mp_ioapics[apic].apicid)
+ if (old_id != mp_ioapics[apic_id].apicid)
for (i = 0; i < mp_irq_entries; i++)
if (mp_irqs[i].dstapic == old_id)
mp_irqs[i].dstapic
- = mp_ioapics[apic].apicid;
+ = mp_ioapics[apic_id].apicid;
/*
* Read the right value from the MPC table and
*/
apic_printk(APIC_VERBOSE, KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
- mp_ioapics[apic].apicid);
+ mp_ioapics[apic_id].apicid);
- reg_00.bits.ID = mp_ioapics[apic].apicid;
+ reg_00.bits.ID = mp_ioapics[apic_id].apicid;
spin_lock_irqsave(&ioapic_lock, flags);
- io_apic_write(apic, 0, reg_00.raw);
+ io_apic_write(apic_id, 0, reg_00.raw);
spin_unlock_irqrestore(&ioapic_lock, flags);
/*
* Sanity check
*/
spin_lock_irqsave(&ioapic_lock, flags);
- reg_00.raw = io_apic_read(apic, 0);
+ reg_00.raw = io_apic_read(apic_id, 0);
spin_unlock_irqrestore(&ioapic_lock, flags);
- if (reg_00.bits.ID != mp_ioapics[apic].apicid)
+ if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
printk("could not set ID!\n");
else
apic_printk(APIC_VERBOSE, " ok.\n");
static int __init numaq_update_genapic(void)
{
- genapic->wakeup_cpu = wakeup_secondary_cpu_via_nmi;
+ apic->wakeup_cpu = wakeup_secondary_cpu_via_nmi;
return 0;
}
{
#ifdef CONFIG_X86_SMP
# if defined(CONFIG_X86_GENERICARCH) || defined(CONFIG_X86_64)
- genapic->wakeup_cpu = wakeup_secondary_cpu_via_init;
+ apic->wakeup_cpu = wakeup_secondary_cpu_via_init;
# endif
#endif
void __init es7000_update_genapic_to_cluster(void)
{
- genapic->target_cpus = target_cpus_cluster;
- genapic->int_delivery_mode = INT_DELIVERY_MODE_CLUSTER;
- genapic->int_dest_mode = INT_DEST_MODE_CLUSTER;
- genapic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER;
+ apic->target_cpus = target_cpus_cluster;
+ apic->int_delivery_mode = INT_DELIVERY_MODE_CLUSTER;
+ apic->int_dest_mode = INT_DEST_MODE_CLUSTER;
+ apic->no_balance_irq = NO_BALANCE_IRQ_CLUSTER;
- genapic->init_apic_ldr = init_apic_ldr_cluster;
+ apic->init_apic_ldr = init_apic_ldr_cluster;
- genapic->cpu_mask_to_apicid = cpu_mask_to_apicid_cluster;
+ apic->cpu_mask_to_apicid = cpu_mask_to_apicid_cluster;
}
static int probe_es7000(void)
extern struct genapic apic_es7000;
extern struct genapic apic_default;
-struct genapic *genapic = &apic_default;
+struct genapic *apic = &apic_default;
static struct genapic *apic_probe[] __initdata = {
#ifdef CONFIG_X86_NUMAQ
for (i = 0; apic_probe[i]; i++) {
if (!strcmp(apic_probe[i]->name, arg)) {
- genapic = apic_probe[i];
+ apic = apic_probe[i];
cmdline_apic = 1;
return 0;
}
* - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
*/
- if (!cmdline_apic && genapic == &apic_default) {
+ if (!cmdline_apic && apic == &apic_default) {
if (apic_bigsmp.probe()) {
- genapic = &apic_bigsmp;
+ apic = &apic_bigsmp;
if (x86_quirks->update_genapic)
x86_quirks->update_genapic();
printk(KERN_INFO "Overriding APIC driver with %s\n",
- genapic->name);
+ apic->name);
}
}
#endif
int i;
for (i = 0; apic_probe[i]; i++) {
if (apic_probe[i]->probe()) {
- genapic = apic_probe[i];
+ apic = apic_probe[i];
break;
}
}
if (x86_quirks->update_genapic)
x86_quirks->update_genapic();
}
- printk(KERN_INFO "Using APIC driver %s\n", genapic->name);
+ printk(KERN_INFO "Using APIC driver %s\n", apic->name);
}
/* These functions can switch the APIC even after the initial ->probe() */
for (i = 0; apic_probe[i]; ++i) {
if (apic_probe[i]->mps_oem_check(mpc, oem, productid)) {
if (!cmdline_apic) {
- genapic = apic_probe[i];
+ apic = apic_probe[i];
if (x86_quirks->update_genapic)
x86_quirks->update_genapic();
printk(KERN_INFO "Switched to APIC driver `%s'.\n",
- genapic->name);
+ apic->name);
}
return 1;
}
for (i = 0; apic_probe[i]; ++i) {
if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
if (!cmdline_apic) {
- genapic = apic_probe[i];
+ apic = apic_probe[i];
if (x86_quirks->update_genapic)
x86_quirks->update_genapic();
printk(KERN_INFO "Switched to APIC driver `%s'.\n",
- genapic->name);
+ apic->name);
}
return 1;
}
int hard_smp_processor_id(void)
{
- return genapic->get_apic_id(*(unsigned long *)(APIC_BASE+APIC_ID));
+ return apic->get_apic_id(*(unsigned long *)(APIC_BASE+APIC_ID));
}