ltq-deu: set correct control register for AES

Some devices initialize AES during boot and AES works out of the box
and the correct endianess is set.
NDC means (No Danube Compatibility Mode) and the endianess setting has
no effect if its set to 0.
NDC 0: OFF ENDI bit cannot be written as in Danube
To make it work for other devices, the NDC control register needs to
be set to 1.

Signed-off-by: Daniel Kestrel <kestrel1974@t-online.de>

diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
index aaa7bce237b6c3b52bd935e7ab5c5724b0a9fcfa..8063672613a43d948a4bf3f869c1a169b683611c 100644 (file)
--- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
+++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
@@ -107,7 +107,7 @@ void aes_chip_init (void)
 
     // start crypto engine with write to ILR
     aes->controlr.SM = 1;
-    aes->controlr.NDC = 0;
+    aes->controlr.NDC = 1;
     asm("sync");
     aes->controlr.ENDI = 1;
     asm("sync");