drm/amdgpu: update the vm invalidation engine layout V2

We need new invalidation engine layout due to new SDMA page
queues added.

V2: fix coding style and add correct return value

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ce150de723c98132511304944720629a8a9eb460..bacdaef77b6c1ad0d3e12943e2bf53fefcea74b9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -718,37 +718,46 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
        }
 }
 
-static int gmc_v9_0_late_init(void *handle)
+static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       /*
-        * The latest engine allocation on gfx9 is:
-        * Engine 0, 1: idle
-        * Engine 2, 3: firmware
-        * Engine 4~13: amdgpu ring, subject to change when ring number changes
-        * Engine 14~15: idle
-        * Engine 16: kfd tlb invalidation
-        * Engine 17: Gart flushes
-        */
-       unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
+       struct amdgpu_ring *ring;
+       unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
+               {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
        unsigned i;
-       int r;
+       unsigned vmhub, inv_eng;
 
-       if (!gmc_v9_0_keep_stolen_memory(adev))
-               amdgpu_bo_late_init(adev);
+       for (i = 0; i < adev->num_rings; ++i) {
+               ring = adev->rings[i];
+               vmhub = ring->funcs->vmhub;
+
+               inv_eng = ffs(vm_inv_engs[vmhub]);
+               if (!inv_eng) {
+                       dev_err(adev->dev, "no VM inv eng for ring %s\n",
+                               ring->name);
+                       return -EINVAL;
+               }
 
-       for(i = 0; i < adev->num_rings; ++i) {
-               struct amdgpu_ring *ring = adev->rings[i];
-               unsigned vmhub = ring->funcs->vmhub;
+               ring->vm_inv_eng = inv_eng - 1;
+               change_bit(inv_eng - 1, (unsigned long *)(&vm_inv_engs[vmhub]));
 
-               ring->vm_inv_eng = vm_inv_eng[vmhub]++;
                dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
                         ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
        }
 
-       /* Engine 16 is used for KFD and 17 for GART flushes */
-       for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
-               BUG_ON(vm_inv_eng[i] > 16);
+       return 0;
+}
+
+static int gmc_v9_0_late_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int r;
+
+       if (!gmc_v9_0_keep_stolen_memory(adev))
+               amdgpu_bo_late_init(adev);
+
+       r = gmc_v9_0_allocate_vm_inv_eng(adev);
+       if (r)
+               return r;
 
        if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
                r = gmc_v9_0_ecc_available(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
index b030ca5ea1072eb66674a7ebea16ad7cdc694bc2..5c8deac65580603ac69f516efb17162efe75bfab 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
@@ -24,6 +24,16 @@
 #ifndef __GMC_V9_0_H__
 #define __GMC_V9_0_H__
 
+       /*
+        * The latest engine allocation on gfx9 is:
+        * Engine 2, 3: firmware
+        * Engine 0, 1, 4~16: amdgpu ring,
+        *                    subject to change when ring number changes
+        * Engine 17: Gart flushes
+        */
+#define GFXHUB_FREE_VM_INV_ENGS_BITMAP         0x1FFF3
+#define MMHUB_FREE_VM_INV_ENGS_BITMAP          0x1FFF3
+
 extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;