AMU: Implement context save/restore for aarch32

Add amu_context_save() and amu_context_restore() functions for aarch32

Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a
Signed-off-by: Joel Hutton <joel.hutton@arm.com>

diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index 630d3f26ff44d7f37d1e494e4f561574913c7f4e..3624cc689219907c68e062100471e53f188108e3 100644 (file)
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -544,7 +544,7 @@
 #define AMCNTENCLR0    p15, 0, c13, c2, 4
 #define AMCNTENSET0    p15, 0, c13, c2, 5
 #define AMCNTENCLR1    p15, 0, c13, c3, 0
-#define AMCNTENSET1    p15, 0, c13, c1, 1
+#define AMCNTENSET1    p15, 0, c13, c3, 1
 
 /* Activity Monitor Group 0 Event Counter Registers */
 #define AMEVCNTR00     p15, 0, c0

diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index faa0ee125f77a55331661a0f9da328b09961d907..559c8f13459ddafe2eb53face837bfefe2906602 100644 (file)
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -7,10 +7,10 @@
 #ifndef __AMU_H__
 #define __AMU_H__
 
-#include <sys/cdefs.h> /* for CASSERT() */
 #include <cassert.h>
 #include <platform_def.h>
 #include <stdint.h>
+#include <sys/cdefs.h> /* for CASSERT() */
 
 /* All group 0 counters */
 #define AMU_GROUP0_COUNTERS_MASK       0xf

diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c
index c1089a6071ff3f03ad29d79ce38a175ee7d35a33..a1ffcb0410026bc0fc0f4056ec37426e1d368c41 100644 (file)
--- a/lib/cpus/aarch64/cortex_a75_pubsub.c
+++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -5,8 +5,8 @@
  */
 
 #include <cortex_a75.h>
-#include <pubsub_events.h>
 #include <platform.h>
+#include <pubsub_events.h>
 
 struct amu_ctx {
        uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS];

diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index effc5bd3ae757dd1e2ea78cad2342b003b47ccfe..68cc4b34c8523d898e7d4ca917dad7dec4b7dd03 100644 (file)
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -5,6 +5,7 @@
  */
 
 #include <amu.h>
+#include <amu_private.h>
 #include <arch.h>
 #include <arch_helpers.h>
 #include <platform.h>
@@ -14,21 +15,26 @@
 
 struct amu_ctx {
        uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
+       uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
 };
 
 static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
 
-void amu_enable(int el2_unused)
+int amu_supported(void)
 {
        uint64_t features;
 
        features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
-       if ((features & ID_PFR0_AMU_MASK) != 1)
+       return (features & ID_PFR0_AMU_MASK) == 1;
+}
+
+void amu_enable(int el2_unused)
+{
+       if (!amu_supported())
                return;
 
        if (el2_unused) {
                uint64_t v;
-
                /*
                 * Non-secure access from EL0 or EL1 to the Activity Monitor
                 * registers do not trap to EL2.
@@ -40,15 +46,64 @@ void amu_enable(int el2_unused)
 
        /* Enable group 0 counters */
        write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
+
+       /* Enable group 1 counters */
+       write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
+}
+
+/* Read the group 0 counter identified by the given `idx`. */
+uint64_t amu_group0_cnt_read(int idx)
+{
+       assert(amu_supported());
+       assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+
+       return amu_group0_cnt_read_internal(idx);
+}
+
+/* Write the group 0 counter identified by the given `idx` with `val`. */
+void amu_group0_cnt_write(int idx, uint64_t val)
+{
+       assert(amu_supported());
+       assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+
+       amu_group0_cnt_write_internal(idx, val);
+       isb();
+}
+
+/* Read the group 1 counter identified by the given `idx`. */
+uint64_t amu_group1_cnt_read(int idx)
+{
+       assert(amu_supported());
+       assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+       return amu_group1_cnt_read_internal(idx);
+}
+
+/* Write the group 1 counter identified by the given `idx` with `val`. */
+void amu_group1_cnt_write(int idx, uint64_t val)
+{
+       assert(amu_supported());
+       assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+       amu_group1_cnt_write_internal(idx, val);
+       isb();
+}
+
+void amu_group1_set_evtype(int idx, unsigned int val)
+{
+       assert(amu_supported());
+       assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+       amu_group1_set_evtype_internal(idx, val);
+       isb();
 }
 
 static void *amu_context_save(const void *arg)
 {
        struct amu_ctx *ctx;
-       uint64_t features;
+       int i;
 
-       features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
-       if ((features & ID_PFR0_AMU_MASK) != 1)
+       if (!amu_supported())
                return (void *)-1;
 
        ctx = &amu_ctxs[plat_my_core_pos()];
@@ -61,12 +116,14 @@ static void *amu_context_save(const void *arg)
         * counter values from the future via the memory mapped view.
         */
        write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
+       write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
        isb();
 
-       ctx->group0_cnts[0] = read64_amevcntr00();
-       ctx->group0_cnts[1] = read64_amevcntr01();
-       ctx->group0_cnts[2] = read64_amevcntr02();
-       ctx->group0_cnts[3] = read64_amevcntr03();
+       for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
+               ctx->group0_cnts[i] = amu_group0_cnt_read(i);
+
+       for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
+               ctx->group1_cnts[i] = amu_group1_cnt_read(i);
 
        return 0;
 }
@@ -75,6 +132,7 @@ static void *amu_context_restore(const void *arg)
 {
        struct amu_ctx *ctx;
        uint64_t features;
+       int i;
 
        features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
        if ((features & ID_PFR0_AMU_MASK) != 1)
@@ -86,19 +144,16 @@ static void *amu_context_restore(const void *arg)
        assert(read_amcntenset0() == 0);
 
        /* Restore group 0 counters */
-       if (AMU_GROUP0_COUNTERS_MASK & (1U << 0))
-               write64_amevcntr00(ctx->group0_cnts[0]);
-       if (AMU_GROUP0_COUNTERS_MASK & (1U << 1))
-               write64_amevcntr01(ctx->group0_cnts[1]);
-       if (AMU_GROUP0_COUNTERS_MASK & (1U << 2))
-               write64_amevcntr02(ctx->group0_cnts[2]);
-       if (AMU_GROUP0_COUNTERS_MASK & (1U << 3))
-               write64_amevcntr03(ctx->group0_cnts[3]);
-       isb();
+       for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
+               amu_group0_cnt_write(i, ctx->group0_cnts[i]);
+       for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
+               amu_group1_cnt_write(i, ctx->group1_cnts[i]);
 
        /* Enable group 0 counters */
        write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
 
+       /* Enable group 1 counters */
+       write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
        return 0;
 }
 

diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index d7645a9e14c02f694694483572d4f315737dbad2..7d39f35c10187fd71806bd27b69747da6ca85df0 100644 (file)
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -172,7 +172,6 @@ static void *amu_context_restore(const void *arg)
        for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
                if (AMU_GROUP1_COUNTERS_MASK & (1U << i))
                        amu_group1_cnt_write(i, ctx->group1_cnts[i]);
-       isb();
 
        /* Restore group 0/1 counter configuration */
        write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);