if (clk->set_rate != NULL)
ret = clk->set_rate(clk, rate);
- if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
- propagate_rate(clk);
-
return ret;
}
pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
clk->name, clk->parent->name, clk->rate);
- if (unlikely(clk->flags & RATE_PROPAGATES))
- propagate_rate(clk);
-
return 0;
}
spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_rate)
ret = arch_clock->clk_set_rate(clk, rate);
+ if (ret == 0 && (clk->flags & RATE_PROPAGATES))
+ propagate_rate(clk);
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;
spin_lock_irqsave(&clockfw_lock, flags);
if (arch_clock->clk_set_parent)
- ret = arch_clock->clk_set_parent(clk, parent);
+ ret = arch_clock->clk_set_parent(clk, parent);
+ if (ret == 0 && (clk->flags & RATE_PROPAGATES))
+ propagate_rate(clk);
spin_unlock_irqrestore(&clockfw_lock, flags);
return ret;