[ARM] 5412/1: XSCALE: add ice dcc support

SCALE: add ice dcc support

Tested on the ixp425 with the ice PEEDI

Ack-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 35f8db35f44208ddfe3b886e5aab3171537f2fc6..a71fd941ade7cdd82610b62a1109a6dc04615907 100644 (file)
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -77,7 +77,7 @@ config DEBUG_ICEDCC
          Say Y here if you want the debug print routines to direct their
          output to the EmbeddedICE macrocell's DCC channel using
          co-processor 14. This is known to work on the ARM9 style ICE
-         channel.
+         channel and on the XScale with the PEEDI.
 
          It does include a timeout to ensure that the system does not
          totally freeze when there is nothing connected to read.

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 77d614232d815fd592e6798383e7eb4aa8be48ae..d1b678dc120bf5c5eef1fb5add9b03e74beb53f6 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -27,6 +27,12 @@
                .macro  writeb, ch, rb
                mcr     p14, 0, \ch, c0, c5, 0
                .endm
+#elif defined(CONFIG_CPU_XSCALE)
+               .macro  loadsp, rb
+               .endm
+               .macro  writeb, ch, rb
+               mcr     p14, 0, \ch, c8, c0, 0
+               .endm
 #else
                .macro  loadsp, rb
                .endm

diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 3fc08413fff05803a3f555de749917b56962b966..393c8164131484b03c7f0fa4561d294eb8bd0c31 100644 (file)
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -46,6 +46,21 @@ static void icedcc_putc(int ch)
 
        asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
 }
+#elif defined(CONFIG_CPU_XSCALE)
+
+static void icedcc_putc(int ch)
+{
+       int status, i = 0x4000000;
+
+       do {
+               if (--i < 0)
+                       return;
+
+               asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status));
+       } while (status & (1 << 28));
+
+       asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch));
+}
 
 #else
 

diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index f53c582905430af58b91341e952e1fe180a022c8..b121b6053cce4e74a1b650c6bc83665920225ede 100644 (file)
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -49,6 +49,33 @@
 1002:
                .endm
 
+#elif defined(CONFIG_CPU_XSCALE)
+
+               .macro  addruart, rx
+               .endm
+
+               .macro  senduart, rd, rx
+               mcr     p14, 0, \rd, c8, c0, 0
+               .endm
+
+               .macro  busyuart, rd, rx
+1001:
+               mrc     p14, 0, \rx, c14, c0, 0
+               tst     \rx, #0x10000000
+               beq     1001b
+               .endm
+
+               .macro  waituart, rd, rx
+               mov     \rd, #0x10000000
+1001:
+               subs    \rd, \rd, #1
+               bmi     1002f
+               mrc     p14, 0, \rx, c14, c0, 0
+               tst     \rx, #0x10000000
+               bne     1001b
+1002:
+               .endm
+
 #else
 
                .macro  addruart, rx