MIPS: microMIPS: Fix improper definition of ISA exception bit.

The ISA exception bit selects whether exceptions are taken in classic
or microMIPS mode. This bit is Config3.ISAOnExc and was improperly
defined as bits 16 and 17 instead of just bit 16. A new function was
added so that platforms could set this bit when running a kernel
compiled with only microMIPS instructions.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5377/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207b05e4334f242cadf80b01305811edd3fd..fed1c3e9b486b7bf044f66cdedf9e2a1c302c80c 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,7 +596,7 @@
 #define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
 #define MIPS_CONF3_ISA         (_ULCAST_(3) << 14)
-#define MIPS_CONF3_ISA_OE      (_ULCAST_(3) << 16)
+#define MIPS_CONF3_ISA_OE      (_ULCAST_(1) << 16)
 #define MIPS_CONF3_VZ          (_ULCAST_(1) << 23)
 
 #define MIPS_CONF4_MMUSIZEEXT  (_ULCAST_(255) << 0)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f87039dbefe96cf166a5a12a4afca1ac173e6580..c7b1b3c5a761c0c46067ee940a722eb5ab490e5d 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -269,9 +269,6 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_ULRI;
        if (config3 & MIPS_CONF3_ISA)
                c->options |= MIPS_CPU_MICROMIPS;
-#ifdef CONFIG_CPU_MICROMIPS
-       write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE);
-#endif
        if (config3 & MIPS_CONF3_VZ)
                c->ases |= MIPS_ASE_VZ;
 

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d97ea234e2d3995c9ddae9a65854f5360aac4c9d..b0f3ad26063ea1dc381def2bdb8e6bf1c5855622 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1878,6 +1878,15 @@ void __init trap_init(void)
                        ebase += (read_c0_ebase() & 0x3ffff000);
        }
 
+       if (cpu_has_mmips) {
+               unsigned int config3 = read_c0_config3();
+
+               if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
+                       write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
+               else
+                       write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
+       }
+
        if (board_ebase_setup)
                board_ebase_setup();
        per_cpu_trap_init(true);