drm/i915/gt: Expand bad CS completion event debug

Show the ring/request/context state if we see what we believe is an
early CS completion.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200211230944.1203098-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 57e8a051ddc2abbee284e3efd2f0c80f1e3e40ff..e4f89341d17cfad2d7b6450ff0ba421266a51787 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -116,7 +116,8 @@ int __intel_context_do_pin(struct intel_context *ce)
                if (unlikely(err))
                        goto err_active;
 
-               CE_TRACE(ce, "pin ring:{head:%04x, tail:%04x}\n",
+               CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n",
+                        i915_ggtt_offset(ce->ring->vma),
                         ce->ring->head, ce->ring->tail);
 
                smp_mb__before_atomic(); /* flush pin before it is visible */

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 902d440ef07d1ce37b7f98057471f2732959c67e..1e3db37dea2b986044a75a6fffa291757533dfce 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2328,8 +2328,35 @@ static void process_csb(struct intel_engine_cs *engine)
                         * coherent (visible from the CPU) before the
                         * user interrupt and CSB is processed.
                         */
-                       GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
-                                  !reset_in_progress(execlists));
+                       if (GEM_SHOW_DEBUG() &&
+                           !i915_request_completed(*execlists->active) &&
+                           !reset_in_progress(execlists)) {
+                               struct i915_request *rq = *execlists->active;
+                               const u32 *regs = rq->context->lrc_reg_state;
+
+                               ENGINE_TRACE(engine,
+                                            "ring:{start:0x%08x, head:%04x, tail:%04x, ctl:%08x, mode:%08x}\n",
+                                            ENGINE_READ(engine, RING_START),
+                                            ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR,
+                                            ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR,
+                                            ENGINE_READ(engine, RING_CTL),
+                                            ENGINE_READ(engine, RING_MI_MODE));
+                               ENGINE_TRACE(engine,
+                                            "rq:{start:%08x, head:%04x, tail:%04x, seqno:%llx:%d, hwsp:%d}, ",
+                                            i915_ggtt_offset(rq->ring->vma),
+                                            rq->head, rq->tail,
+                                            rq->fence.context,
+                                            lower_32_bits(rq->fence.seqno),
+                                            hwsp_seqno(rq));
+                               ENGINE_TRACE(engine,
+                                            "ctx:{start:%08x, head:%04x, tail:%04x}, ",
+                                            regs[CTX_RING_START],
+                                            regs[CTX_RING_HEAD],
+                                            regs[CTX_RING_TAIL]);
+
+                               GEM_BUG_ON("context completed before request");
+                       }
+
                        execlists_schedule_out(*execlists->active++);
 
                        GEM_BUG_ON(execlists->active - execlists->inflight >