}
static struct resource nand_slot0_res[] = {
- {
+ [0] = {
.name = "nand_membase",
.flags = IORESOURCE_MEM
}
};
static struct platform_device nand_slot0 = {
- .id = 0,
.name = "gen_nand",
+ .id = -1,
.resource = nand_slot0_res,
.num_resources = ARRAY_SIZE(nand_slot0_res),
.dev.platform_data = &rb500_nand_data,
changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
else
changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
+
+ /* Setup NAND specific settings */
+ rb500_nand_data.chip.nr_chips = 1;
+ rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
+ rb500_nand_data.chip.partitions = rb500_partition_info;
+ rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
+ rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
}
cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
}
- /* Initialise the NAND device */
- rb500_nand_setup();
-
/* Read the NAND resources from the device controller */
nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
-
- /* Setup NAND specific settings */
- rb500_nand_data.chip.nr_chips = 1;
- rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
- rb500_nand_data.chip.partitions = rb500_partition_info;
- rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
- rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
+
+ /* Initialise the NAND device */
+ rb500_nand_setup();
return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
}
unsigned int idt_cpu_freq = 132000000;
EXPORT_SYMBOL(idt_cpu_freq);
-char *board_type;
+char board_type[11];
EXPORT_SYMBOL(board_type);
unsigned int gpio_bootup_state = 0;
EXPORT_SYMBOL(gpio_bootup_state);
}
#endif
if (i>0) *(cp++) = ' ';
+
if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
- board_type = (char *)kzalloc((sizeof(prom_argv[i]) + sizeof(BOARD_TAG) -1), GFP_KERNEL);
strcpy(board_type, prom_argv[i] + sizeof(BOARD_TAG) -1);
}
if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {