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drm/amdgpu: Update gc_9_0 golden settings.
author
Feifei Xu
<Feifei.Xu@amd.com>
Tue, 16 Oct 2018 06:54:46 +0000
(14:54 +0800)
committer
Alex Deucher
<alexander.deucher@amd.com>
Tue, 16 Oct 2018 20:09:53 +0000
(15:09 -0500)
Add mmDB_DEBUG3 settings.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2f10ad569154b7028c36522a696e1baa4cb6f755..6d7baf59d6e11e947c83ef34d716c5a546d6460f 100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@
-97,6
+97,7
@@
MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
static const struct soc15_reg_golden golden_settings_gc_9_0[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),