drm/amd/display: Add dprefclk value to dce_dccg

This allows us to avoid any vbios bugs when initializing clocks

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 103dc3cf1c43c47a55f4dad6a0b7f4b49e1282a6..bf6261a1584be8b45d2351bace72fe31e2f03df4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -202,7 +202,7 @@ static int dce12_get_dp_ref_freq_khz(struct dccg *clk)
 {
        struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
 
-       return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);
+       return dccg_adjust_dp_ref_freq_for_ss(clk_dce, clk_dce->dprefclk_khz);
 }
 
 static enum dm_pp_clocks_state dce_get_required_clocks_state(
@@ -882,6 +882,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
        dce_dccg_construct(
                clk_dce, ctx, NULL, NULL, NULL);
 
+       clk_dce->dprefclk_khz = 600000;
        clk_dce->base.funcs = &dce120_funcs;
 
        return &clk_dce->base;
@@ -909,6 +910,7 @@ struct dccg *dcn1_dccg_create(struct dc_context *ctx)
        clk_dce->dprefclk_ss_divider = 1000;
        clk_dce->ss_on_dprefclk = false;
 
+       clk_dce->dprefclk_khz = 600000;
        if (bp->integrated_info)
                clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
        if (clk_dce->dentist_vco_freq_khz == 0) {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 8b5a53e98ad99966593acd2c2f52975d1ac485be..34fdb386c884855dc5e0edd4b98653eb2e0bde54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -90,6 +90,7 @@ struct dce_dccg {
        int dprefclk_ss_percentage;
        /* DPREFCLK SS percentage Divider (100 or 1000) */
        int dprefclk_ss_divider;
+       int dprefclk_khz;
 };