ARM: net: bpf: Improve prologue code sequence

Improve the prologue code sequence to be able to take advantage of
64-bit stores, changing the code from:

  push    {r4, r5, r6, r7, r8, r9, fp, lr}
  mov     fp, sp
  sub     ip, sp, #80     ; 0x50
  sub     sp, sp, #600    ; 0x258
  str     ip, [fp, #-100] ; 0xffffff9c
  mov     r6, #0
  str     r6, [fp, #-96]  ; 0xffffffa0
  mov     r4, #0
  mov     r3, r4
  mov     r2, r0
  str     r4, [fp, #-104] ; 0xffffff98
  str     r4, [fp, #-108] ; 0xffffff94

to the tighter:

  push    {r4, r5, r6, r7, r8, r9, fp, lr}
  mov     fp, sp
  mov     r3, #0
  sub     r2, sp, #80     ; 0x50
  sub     sp, sp, #600    ; 0x258
  strd    r2, [fp, #-100] ; 0xffffff9c
  mov     r2, #0
  strd    r2, [fp, #-108] ; 0xffffff94
  mov     r2, r0

resulting in a saving of three instructions.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/E1ieH2g-0004ih-Rb@rmk-PC.armlinux.org.uk

diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 97dc386e3cb8e9f28947da5dbe3b2b241a923271..cc29869d12a3ecb7bbb1fd4212355963b654952b 100644 (file)
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -1260,12 +1260,9 @@ static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx)
 
 static void build_prologue(struct jit_ctx *ctx)
 {
-       const s8 r0 = bpf2a32[BPF_REG_0][1];
-       const s8 r2 = bpf2a32[BPF_REG_1][1];
-       const s8 r3 = bpf2a32[BPF_REG_1][0];
-       const s8 r4 = bpf2a32[BPF_REG_6][1];
-       const s8 fplo = bpf2a32[BPF_REG_FP][1];
-       const s8 fphi = bpf2a32[BPF_REG_FP][0];
+       const s8 arm_r0 = bpf2a32[BPF_REG_0][1];
+       const s8 *bpf_r1 = bpf2a32[BPF_REG_1];
+       const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
        const s8 *tcc = bpf2a32[TCALL_CNT];
 
        /* Save callee saved registers. */
@@ -1278,8 +1275,10 @@ static void build_prologue(struct jit_ctx *ctx)
        emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
        emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
 #endif
-       /* Save frame pointer for later */
-       emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx);
+       /* mov r3, #0 */
+       /* sub r2, sp, #SCRATCH_SIZE */
+       emit(ARM_MOV_I(bpf_r1[0], 0), ctx);
+       emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx);
 
        ctx->stack_size = imm8m(STACK_SIZE);
 
@@ -1287,18 +1286,15 @@ static void build_prologue(struct jit_ctx *ctx)
        emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
 
        /* Set up BPF prog stack base register */
-       emit_a32_mov_r(fplo, ARM_IP, ctx);
-       emit_a32_mov_i(fphi, 0, ctx);
+       emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx);
 
-       /* mov r4, 0 */
-       emit(ARM_MOV_I(r4, 0), ctx);
+       /* Initialize Tail Count */
+       emit(ARM_MOV_I(bpf_r1[1], 0), ctx);
+       emit_a32_mov_r64(true, tcc, bpf_r1, ctx);
 
        /* Move BPF_CTX to BPF_R1 */
-       emit(ARM_MOV_R(r3, r4), ctx);
-       emit(ARM_MOV_R(r2, r0), ctx);
-       /* Initialize Tail Count */
-       emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[0])), ctx);
-       emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[1])), ctx);
+       emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx);
+
        /* end of prologue */
 }