cns3xxx: fix an rx irq handling corner case

When an rx interrupt comes in, rx interrupts are disabled and NAPI
polling is scheduled. During the NAPI poll, the driver first processes
received frames in the ring, then fills the dma descriptor slots with
new buffers and calls tx complete, before finally re-enabling rx
interrupts and completing NAPI (if below the budget).
If the hardware rx queue overflows before the napi complete is called,
the hardware will not throw any further rx interrupts and rx processing
stops completely.
Fix this by keeping NAPI polling scheduled until it completes a poll
without receiving any packets, and also handle NAPI completion before
refilling rx or completing tx.

SVN-Revision: 35942

diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
index 7ffff684de337f524b9dd453a14a2187e1e2b5a8..7309d9ea779cdc72d193a63b7d8c91d012721b0d 100644 (file)
--- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
+++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
@@ -706,15 +706,15 @@ static int eth_poll(struct napi_struct *napi, int budget)
                }
        }
 
-       cns3xxx_alloc_rx_buf(sw, received);
-
-       rx_ring->cur_index = i;
-
-       if (received != budget) {
+       if (!received) {
                napi_complete(napi);
                enable_irq(IRQ_CNS3XXX_SW_R0RXC);
        }
 
+       cns3xxx_alloc_rx_buf(sw, received);
+
+       rx_ring->cur_index = i;
+
        wmb();
        enable_rx_dma(sw);