pdata->reset_bit = AR934X_RESET_GE0_MAC |
AR934X_RESET_GE0_MDIO;
pdata->set_speed = ar934x_set_speed_ge0;
+
+ if (ath79_soc == ATH79_SOC_QCA9533)
+ pdata->disable_inline_checksum_engine = 1;
} else {
pdata->reset_bit = AR934X_RESET_GE1_MAC |
AR934X_RESET_GE1_MDIO;
pdata->set_speed = qca956x_set_speed_sgmii;
else
pdata->set_speed = ar934x_set_speed_ge0;
+
+ pdata->disable_inline_checksum_engine = 1;
} else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO;
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
+
+ if (pdata->disable_inline_checksum_engine) {
+ /*
+ * The rx ring buffer can stall on small packets on QCA953x and
+ * QCA956x. Disabling the inline checksum engine fixes the stall.
+ * The wr, rr functions cannot be used since this hidden register
+ * is outside of the normal ag71xx register block.
+ */
+ void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
+ if (dam) {
+ __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
+ (void)__raw_readl(dam);
+ iounmap(dam);
+ }
+ }
+
ag71xx_hw_start(ag);
netif_carrier_on(ag->dev);