allwinner: Adjust memory mapping to fit into 256MB
authorAndre Przywara <andre.przywara@arm.com>
Thu, 20 Sep 2018 20:13:55 +0000 (21:13 +0100)
committerAndre Przywara <andre.przywara@arm.com>
Sat, 20 Oct 2018 15:23:59 +0000 (16:23 +0100)
At the moment we map as much of the DRAM into EL3 as possible, however
we actually don't use it. The only exception is the secure DRAM for
BL32 (if that is configured).

To decrease the memory footprint of ATF, we save on some page tables by
reducing the memory mapping to the actually required regions: SRAM, device
MMIO, secure DRAM and U-Boot (to be used later).
This introduces a non-identity mapping for the DRAM regions.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
plat/allwinner/common/include/platform_def.h
plat/allwinner/common/sunxi_common.c
plat/allwinner/sun50i_a64/include/sunxi_mmap.h
plat/allwinner/sun50i_h6/include/sunxi_mmap.h

index b46d410165f1b52fb8b4a0203d56270bd7fcbb3b..b7cf30f5a3e25a7b896f8a9e1591d5fabf8f44c6 100644 (file)
 /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
 #define PLAT_SUNXI_NS_IMAGE_OFFSET     (SUNXI_DRAM_BASE + (160U << 20))
 
+/* How much memory to reserve as secure for BL32, if configured */
+#define SUNXI_DRAM_SEC_SIZE            (32U << 20)
+
+/* How much DRAM to map */
+#define SUNXI_DRAM_MAP_SIZE            (64U << 20)
+
 #define CACHE_WRITEBACK_SHIFT          6
 #define CACHE_WRITEBACK_GRANULE                (1 << CACHE_WRITEBACK_SHIFT)
 
 #define MAX_MMAP_REGIONS               (4 + PLATFORM_MMAP_REGIONS)
-#define MAX_XLAT_TABLES                        2
+#define MAX_XLAT_TABLES                        1
 
 #define PLAT_MAX_PWR_LVL_STATES                U(2)
 #define PLAT_MAX_RET_STATE             U(1)
                                         PLATFORM_CORE_COUNT)
 
 #define PLAT_PHY_ADDR_SPACE_SIZE       (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE      (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE      (1ULL << 28)
 
 #define PLATFORM_CLUSTER_COUNT         1
 #define PLATFORM_CORE_COUNT            (PLATFORM_CLUSTER_COUNT * \
                                         PLATFORM_MAX_CPUS_PER_CLUSTER)
 #define PLATFORM_MAX_CPUS_PER_CLUSTER  4
-#define PLATFORM_MMAP_REGIONS          3
+#define PLATFORM_MMAP_REGIONS          4
 #define PLATFORM_STACK_SIZE            (0x1000 / PLATFORM_CORE_COUNT)
 
 #ifndef SPD_none
index fc9bf20978fa1b588e5ac22d6dda6f499c7d166d..ef6f04c7d78f5114dfe0edba03eb1721aacf8779 100644 (file)
@@ -17,8 +17,12 @@ static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
                        MT_MEMORY | MT_RW | MT_SECURE),
        MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
                        MT_DEVICE | MT_RW | MT_SECURE),
-       MAP_REGION_FLAT(SUNXI_DRAM_BASE, SUNXI_DRAM_SIZE,
-                       MT_MEMORY | MT_RW | MT_NS),
+       MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
+                       MT_MEMORY | MT_RW | MT_SECURE),
+       MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET,
+                  SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
+                  SUNXI_DRAM_MAP_SIZE,
+                  MT_MEMORY | MT_RO | MT_NS),
        {},
 };
 
index 7d46487dc70f92f3eb645e5ee5d9f44b77182ae2..28b1dd3b84b3f2d2745a358373b9cd6c62db9d91 100644 (file)
@@ -21,7 +21,7 @@
 #define SUNXI_DEV_BASE                 0x01000000
 #define SUNXI_DEV_SIZE                 0x01000000
 #define SUNXI_DRAM_BASE                        0x40000000
-#define SUNXI_DRAM_SIZE                        0x80000000
+#define SUNXI_DRAM_VIRT_BASE           0x02000000
 
 /* Memory-mapped devices */
 #define SUNXI_CPU_MBIST_BASE           0x01502000
index f2d5aed6bdd89100b3571201540a67249a928058..901e536f809daea3041579af94a0a4a9c33e1a4d 100644 (file)
@@ -21,7 +21,7 @@
 #define SUNXI_DEV_BASE                 0x01000000
 #define SUNXI_DEV_SIZE                 0x09000000
 #define SUNXI_DRAM_BASE                        0x40000000
-#define SUNXI_DRAM_SIZE                        0xc0000000
+#define SUNXI_DRAM_VIRT_BASE           0x0a000000
 
 /* Memory-mapped devices */
 #define SUNXI_SYSCON_BASE              0x03000000