drm/i915: Finalize Wa_1408961008:icl
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 28 Feb 2019 17:36:39 +0000 (19:36 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 1 Mar 2019 16:10:42 +0000 (18:10 +0200)
The icl wm1+ underrun w/a has been added to the spec. It changed
slightly from the previous incarnation by requiring that we mirror
the lines watermark and the ignore lines bit from WM0 into WM1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190228173639.18422-1-ville.syrjala@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>
drivers/gpu/drm/i915/intel_pm.c

index 4c0e43caa5cdd71fbe6b06de482e8702f47426b7..9c97a95c1816b0d6cb6b1f12f0dd500e8d476a74 100644 (file)
@@ -4467,11 +4467,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
                        wm = &cstate->wm.skl.optimal.planes[plane_id];
                        memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
 
-                       /* W/A for underruns with WM1+ disabled */
+                       /*
+                        * Wa_1408961008:icl
+                        * Underruns with WM1+ disabled
+                        */
                        if (IS_ICELAKE(dev_priv) &&
                            level == 1 && wm->wm[0].plane_en) {
                                wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
-                               wm->wm[level].ignore_lines = true;
+                               wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
+                               wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
                        }
                }
        }