--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
-@@ -129,7 +129,7 @@ out:
+@@ -133,7 +133,7 @@ out:
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val = 0;
if (offset > MAX_PHY_REG_ADDRESS) {
-@@ -142,11 +142,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+@@ -146,11 +146,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
-@@ -171,6 +185,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+@@ -175,6 +189,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
*data = (u16) mdic;
out:
return ret_val;
}
-@@ -185,7 +211,7 @@ out:
+@@ -189,7 +215,7 @@ out:
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val = 0;
if (offset > MAX_PHY_REG_ADDRESS) {
-@@ -198,12 +224,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+@@ -202,12 +228,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
-@@ -227,6 +268,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+@@ -231,6 +272,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
}
out:
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
-@@ -126,9 +126,8 @@ out:
+@@ -130,9 +130,8 @@ out:
* Reads the MDI control regsiter in the PHY at offset and stores the
* information read to data.
**/
u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
-@@ -147,14 +146,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
+@@ -151,14 +150,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
case e1000_i211:
mdicnfg = rd32(E1000_MDICNFG);
mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
(E1000_MDIC_OP_READ));
break;
}
-@@ -208,9 +207,8 @@ out:
+@@ -212,9 +211,8 @@ out:
*
* Writes data to MDI control register in the PHY at offset.
**/
u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
-@@ -229,7 +227,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+@@ -233,7 +231,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
case e1000_i211:
mdicnfg = rd32(E1000_MDICNFG);
mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
wr32(E1000_MDICNFG, mdicnfg);
mdic = (((u32)data) |
(offset << E1000_MDIC_REG_SHIFT) |
-@@ -238,7 +236,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
+@@ -242,7 +240,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
default:
mdic = (((u32)data) |
(offset << E1000_MDIC_REG_SHIFT) |
(E1000_MDIC_OP_WRITE));
break;
}
-@@ -458,7 +456,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
+@@ -462,7 +460,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
goto out;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset);
if (ret_val) {
-@@ -467,8 +465,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
+@@ -471,8 +469,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
}
}
hw->phy.ops.release(hw);
-@@ -497,7 +495,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
+@@ -501,7 +499,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
goto out;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset);
if (ret_val) {
-@@ -506,8 +504,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
+@@ -510,8 +508,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
}
}
hw->phy.ops.release(hw);
-@@ -2547,8 +2545,9 @@ out:
+@@ -2551,8 +2549,9 @@ out:
}
/**
* @offset: lower half is register offset to write to
* upper half is page to use.
* @data: data to write at register offset
-@@ -2556,7 +2555,7 @@ out:
+@@ -2560,7 +2559,7 @@ out:
* Acquires semaphore, if necessary, then writes the data to PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
{
s32 ret_val;
u16 page = offset >> GS40G_PAGE_SHIFT;
-@@ -2566,10 +2565,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
+@@ -2570,10 +2569,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
if (ret_val)
return ret_val;
release:
hw->phy.ops.release(hw);
-@@ -2577,8 +2576,24 @@ release:
+@@ -2581,8 +2580,24 @@ release:
}
/**
* @offset: lower half is register offset to read to
* upper half is page to use.
* @data: data to read at register offset
-@@ -2586,7 +2601,7 @@ release:
+@@ -2590,7 +2605,7 @@ release:
* Acquires semaphore, if necessary, then reads the data in the PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
{
s32 ret_val;
u16 page = offset >> GS40G_PAGE_SHIFT;
-@@ -2596,10 +2611,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
+@@ -2600,10 +2615,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
if (ret_val)
return ret_val;
release:
hw->phy.ops.release(hw);
-@@ -2607,6 +2622,21 @@ release:
+@@ -2611,6 +2626,21 @@ release:
}
/**