static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
static void e1000_clear_vfta(struct e1000_hw *hw);
static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
-static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
+static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
+ bool link_up);
static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
static void e1000_init_rx_addrs(struct e1000_hw *hw);
static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
-static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
+static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
static void e1000_release_software_flag(struct e1000_hw *hw);
-static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
-static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
+static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
+static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
switch (hw->mac_type) {
case e1000_ich8lan:
- hw->swfwhw_semaphore_present = TRUE;
- hw->asf_firmware_present = TRUE;
+ hw->swfwhw_semaphore_present = true;
+ hw->asf_firmware_present = true;
break;
case e1000_80003es2lan:
- hw->swfw_sync_present = TRUE;
+ hw->swfw_sync_present = true;
/* fall through */
case e1000_82571:
case e1000_82572:
case e1000_82573:
- hw->eeprom_semaphore_present = TRUE;
+ hw->eeprom_semaphore_present = true;
/* fall through */
case e1000_82541:
case e1000_82547:
case e1000_82541_rev_2:
case e1000_82547_rev_2:
- hw->asf_firmware_present = TRUE;
+ hw->asf_firmware_present = true;
break;
default:
break;
* FD mode
*/
if (hw->mac_type == e1000_82543)
- hw->bad_tx_carr_stats_fd = TRUE;
+ hw->bad_tx_carr_stats_fd = true;
/* capable of receiving management packets to the host */
if (hw->mac_type >= e1000_82571)
- hw->has_manc2h = TRUE;
+ hw->has_manc2h = true;
/* In rare occasions, ESB2 systems would end up started without
* the RX unit being turned on.
*/
if (hw->mac_type == e1000_80003es2lan)
- hw->rx_needs_kicking = TRUE;
+ hw->rx_needs_kicking = true;
if (hw->mac_type > e1000_82544)
- hw->has_smbus = TRUE;
+ hw->has_smbus = true;
return E1000_SUCCESS;
}
if (hw->mac_type != e1000_82543) {
/* tbi_compatibility is only valid on 82543 */
- hw->tbi_compatibility_en = FALSE;
+ hw->tbi_compatibility_en = false;
}
switch (hw->device_id) {
if (status & E1000_STATUS_TBIMODE) {
hw->media_type = e1000_media_type_fiber;
/* tbi_compatibility not valid on fiber */
- hw->tbi_compatibility_en = FALSE;
+ hw->tbi_compatibility_en = false;
} else {
hw->media_type = e1000_media_type_copper;
}
E1000_WRITE_FLUSH(hw);
/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
- hw->tbi_compatibility_on = FALSE;
+ hw->tbi_compatibility_on = false;
/* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
msleep(20);
break;
case e1000_82573:
- if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+ if (!e1000_is_onboard_nvm_eeprom(hw)) {
udelay(10);
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
if (hw->mac_type <= e1000_82543 ||
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
- hw->phy_reset_disable = FALSE;
+ hw->phy_reset_disable = false;
return E1000_SUCCESS;
}
/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
if (hw->phy_type == e1000_phy_igp) {
/* disable lplu d3 during driver init */
- ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+ ret_val = e1000_set_d3_lplu_state(hw, false);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
/* disable lplu d0 during driver init */
- ret_val = e1000_set_d0_lplu_state(hw, FALSE);
+ ret_val = e1000_set_d0_lplu_state(hw, false);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D0\n");
return ret_val;
* firmware will have already initialized them. We only initialize
* them if the HW is not in IAMT mode.
*/
- if (e1000_check_mng_mode(hw) == FALSE) {
+ if (!e1000_check_mng_mode(hw)) {
/* Enable Electrical Idle on the PHY */
phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
}
}
- hw->get_link_status = TRUE;
+ hw->get_link_status = true;
return E1000_SUCCESS;
}
/* Config DSP to improve Giga link quality */
if (hw->phy_type == e1000_phy_igp) {
- ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
+ ret_val = e1000_config_dsp_after_link_change(hw, true);
if (ret_val) {
DEBUGOUT("Error Configuring DSP after link up\n");
return ret_val;
if (hw->media_type == e1000_media_type_fiber) {
signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
if (status & E1000_STATUS_LU)
- hw->get_link_status = FALSE;
+ hw->get_link_status = false;
}
}
return ret_val;
if (phy_data & MII_SR_LINK_STATUS) {
- hw->get_link_status = FALSE;
+ hw->get_link_status = false;
/* Check if there was DownShift, must be checked immediately after
* link-up */
e1000_check_downshift(hw);
} else {
/* No link detected */
- e1000_config_dsp_after_link_change(hw, FALSE);
+ e1000_config_dsp_after_link_change(hw, false);
return 0;
}
if (!hw->autoneg) return -E1000_ERR_CONFIG;
/* optimize the dsp settings for the igp phy */
- e1000_config_dsp_after_link_change(hw, TRUE);
+ e1000_config_dsp_after_link_change(hw, true);
/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
* have Si on board that is 82544 or newer, Auto
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
- hw->tbi_compatibility_on = FALSE;
+ hw->tbi_compatibility_on = false;
}
} else {
/* If TBI compatibility is was previously off, turn it on. For
* will look like CRC errors to to the hardware.
*/
if (!hw->tbi_compatibility_on) {
- hw->tbi_compatibility_on = TRUE;
+ hw->tbi_compatibility_on = true;
rctl = E1000_READ_REG(hw, RCTL);
rctl |= E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
- hw->serdes_link_down = FALSE;
+ hw->serdes_link_down = false;
}
/* If we force link for non-auto-negotiation switch, check link status
* based on MAC synchronization for internal serdes media type.
udelay(10);
if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
if (!(rxcw & E1000_RXCW_IV)) {
- hw->serdes_link_down = FALSE;
+ hw->serdes_link_down = false;
DEBUGOUT("SERDES: Link is up.\n");
}
} else {
- hw->serdes_link_down = TRUE;
+ hw->serdes_link_down = true;
DEBUGOUT("SERDES: Link is down.\n");
}
}
{
int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
- boolean_t match = FALSE;
+ bool match = false;
DEBUGFUNC("e1000_detect_gig_phy");
switch (hw->mac_type) {
case e1000_82543:
- if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
break;
case e1000_82544:
- if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+ if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
break;
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
- if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+ if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
- if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
+ if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
break;
case e1000_82573:
- if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
+ if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
break;
case e1000_80003es2lan:
- if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == GG82563_E_PHY_ID) match = true;
break;
case e1000_ich8lan:
- if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
- if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
+ if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
+ if (hw->phy_id == IFE_E_PHY_ID) match = true;
+ if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
+ if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
break;
default:
DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
eeprom->opcode_bits = 3;
eeprom->address_bits = 6;
eeprom->delay_usec = 50;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82540:
case e1000_82545:
eeprom->word_size = 64;
eeprom->address_bits = 6;
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82541:
case e1000_82541_rev_2:
eeprom->address_bits = 6;
}
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82571:
case e1000_82572:
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82573:
eeprom->type = e1000_eeprom_spi;
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = TRUE;
- if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+ eeprom->use_eerd = true;
+ eeprom->use_eewr = true;
+ if (!e1000_is_onboard_nvm_eeprom(hw)) {
eeprom->type = e1000_eeprom_flash;
eeprom->word_size = 2048;
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = true;
+ eeprom->use_eewr = false;
break;
case e1000_ich8lan:
{
uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
eeprom->word_size = E1000_SHADOW_RAM_WORDS;
/* Zero the shadow RAM structure. But don't load it from NVM
* so as to save time for driver init */
if (hw->eeprom_shadow_ram != NULL) {
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = FALSE;
+ hw->eeprom_shadow_ram[i].modified = false;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
}
}
* directly. In this case, we need to acquire the EEPROM so that
* FW or other port software does not interrupt.
*/
- if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
- hw->eeprom.use_eerd == FALSE) {
+ if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
/* Prepare the EEPROM for bit-bang reading */
if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
return -E1000_ERR_EEPROM;
}
/* Eerd register EEPROM access requires no eeprom aquire/release */
- if (eeprom->use_eerd == TRUE)
+ if (eeprom->use_eerd)
return e1000_read_eeprom_eerd(hw, offset, words, data);
/* ICH EEPROM access is done via the ICH flash controller */
*
* hw - Struct containing variables accessed by shared code
****************************************************************************/
-static boolean_t
+static bool
e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
{
uint32_t eecd = 0;
DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
if (hw->mac_type == e1000_ich8lan)
- return FALSE;
+ return false;
if (hw->mac_type == e1000_82573) {
eecd = E1000_READ_REG(hw, EECD);
/* If both bits are set, device is Flash type */
if (eecd == 0x03) {
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
/******************************************************************************
DEBUGFUNC("e1000_validate_eeprom_checksum");
- if ((hw->mac_type == e1000_82573) &&
- (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
+ if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
/* Check bit 4 of word 10h. If it is 0, firmware is done updating
* 10h-12h. Checksum may need to be fixed. */
e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
}
/* 82573 writes only through eewr */
- if (eeprom->use_eewr == TRUE)
+ if (eeprom->use_eewr)
return e1000_write_eeprom_eewr(hw, offset, words, data);
if (eeprom->type == e1000_eeprom_ich8)
uint32_t new_bank_offset = 0;
uint8_t low_byte = 0;
uint8_t high_byte = 0;
- boolean_t sector_write_failed = FALSE;
+ bool sector_write_failed = false;
if (hw->mac_type == e1000_82573) {
/* The flop register will be used to determine if flash type is STM */
e1000_erase_ich8_4k_segment(hw, 0);
}
- sector_write_failed = FALSE;
+ sector_write_failed = false;
/* Loop for every byte in the shadow RAM,
* which is in units of words. */
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
/* Determine whether to write the value stored
* in the other NVM bank or a modified value stored
* in the shadow RAM */
- if (hw->eeprom_shadow_ram[i].modified == TRUE) {
+ if (hw->eeprom_shadow_ram[i].modified) {
low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
udelay(100);
error = e1000_verify_write_ich8_byte(hw,
(i << 1) + new_bank_offset, low_byte);
if (error != E1000_SUCCESS)
- sector_write_failed = TRUE;
+ sector_write_failed = true;
else {
high_byte =
(uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
(i << 1) + new_bank_offset, low_byte);
if (error != E1000_SUCCESS)
- sector_write_failed = TRUE;
+ sector_write_failed = true;
else {
e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
&high_byte);
}
}
- /* If the write of the low byte was successful, go ahread and
+ /* If the write of the low byte was successful, go ahead and
* write the high byte while checking to make sure that if it
* is the signature byte, then it is handled properly */
- if (sector_write_failed == FALSE) {
+ if (!sector_write_failed) {
/* If the word is 0x13, then make sure the signature bits
* (15:14) are 11b until the commit has completed.
* This will allow us to write 10b which indicates the
error = e1000_verify_write_ich8_byte(hw,
(i << 1) + new_bank_offset + 1, high_byte);
if (error != E1000_SUCCESS)
- sector_write_failed = TRUE;
+ sector_write_failed = true;
} else {
/* If the write failed then break from the loop and
/* Don't bother writing the segment valid bits if sector
* programming failed. */
- if (sector_write_failed == FALSE) {
+ if (!sector_write_failed) {
/* Finally validate the new segment by setting bit 15:14
* to 10b in word 0x13 , this can be done without an
* erase as well since these bits are 11 to start with
/* Clear the now not used entry in the cache */
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = FALSE;
+ hw->eeprom_shadow_ram[i].modified = false;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
}
}
/* Reserve a spot for the Locally Administered Address to work around
* an 82571 issue in which a reset on one port will reload the MAC on
* the other port. */
- if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
+ if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
rar_num -= 1;
if (hw->mac_type == e1000_ich8lan)
rar_num = E1000_RAR_ENTRIES_ICH8LAN;
case e1000_82571:
case e1000_82572:
case e1000_80003es2lan:
- if (hw->leave_av_bit_off == TRUE)
+ if (hw->leave_av_bit_off)
break;
default:
/* Indicate to hardware the Address is Valid. */
* hw - Struct containing variables accessed by shared code
*
* Call this after e1000_init_hw. You may override the IFS defaults by setting
- * hw->ifs_params_forced to TRUE. However, you must initialize hw->
+ * hw->ifs_params_forced to true. However, you must initialize hw->
* current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
* before calling this function.
*****************************************************************************/
hw->ifs_step_size = IFS_STEP;
hw->ifs_ratio = IFS_RATIO;
}
- hw->in_ifs_mode = FALSE;
+ hw->in_ifs_mode = false;
E1000_WRITE_REG(hw, AIT, 0);
} else {
DEBUGOUT("Not in Adaptive IFS mode!\n");
if (hw->adaptive_ifs) {
if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
if (hw->tx_packet_delta > MIN_NUM_XMITS) {
- hw->in_ifs_mode = TRUE;
+ hw->in_ifs_mode = true;
if (hw->current_ifs_val < hw->ifs_max_val) {
if (hw->current_ifs_val == 0)
hw->current_ifs_val = hw->ifs_min_val;
} else {
if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
hw->current_ifs_val = 0;
- hw->in_ifs_mode = FALSE;
+ hw->in_ifs_mode = false;
E1000_WRITE_REG(hw, AIT, 0);
}
}
M88E1000_PSSR_DOWNSHIFT_SHIFT;
} else if (hw->phy_type == e1000_phy_ife) {
/* e1000_phy_ife supports 10/100 speed only */
- hw->speed_downgraded = FALSE;
+ hw->speed_downgraded = false;
}
return E1000_SUCCESS;
static int32_t
e1000_config_dsp_after_link_change(struct e1000_hw *hw,
- boolean_t link_up)
+ bool link_up)
{
int32_t ret_val;
uint16_t phy_data, phy_saved_data, speed, duplex, i;
if (ret_val)
return ret_val;
- hw->phy_reset_disable = FALSE;
+ hw->phy_reset_disable = false;
}
}
static int32_t
e1000_set_d3_lplu_state(struct e1000_hw *hw,
- boolean_t active)
+ bool active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
static int32_t
e1000_set_d0_lplu_state(struct e1000_hw *hw,
- boolean_t active)
+ bool active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
/*****************************************************************************
* This function checks the mode of the firmware.
*
- * returns - TRUE when the mode is IAMT or FALSE.
+ * returns - true when the mode is IAMT or false.
****************************************************************************/
-boolean_t
+bool
e1000_check_mng_mode(struct e1000_hw *hw)
{
uint32_t fwsm;
if (hw->mac_type == e1000_ich8lan) {
if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
+ return true;
} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
/*****************************************************************************
* This function checks whether tx pkt filtering needs to be enabled or not.
*
- * returns - TRUE for packet filtering or FALSE.
+ * returns - true for packet filtering or false.
****************************************************************************/
-boolean_t
+bool
e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
{
/* called in init as well as watchdog timer functions */
int32_t ret_val, checksum;
- boolean_t tx_filter = FALSE;
+ bool tx_filter = false;
struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
E1000_MNG_DHCP_COOKIE_LENGTH)) {
if (hdr->status &
E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
- tx_filter = TRUE;
+ tx_filter = true;
} else
- tx_filter = TRUE;
+ tx_filter = true;
} else
- tx_filter = TRUE;
+ tx_filter = true;
}
}
*
* hw - Struct containing variables accessed by shared code
*
- * returns: - TRUE/FALSE
+ * returns: - true/false
*
*****************************************************************************/
uint32_t
if (!(manc & E1000_MANC_RCV_TCO_EN) ||
!(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
- return FALSE;
- if (e1000_arc_subsystem_valid(hw) == TRUE) {
+ return false;
+ if (e1000_arc_subsystem_valid(hw)) {
fwsm = E1000_READ_REG(hw, FWSM);
factps = E1000_READ_REG(hw, FACTPS);
if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
- return TRUE;
+ return true;
} else
if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
static int32_t
case e1000_80003es2lan:
fwsm = E1000_READ_REG(hw, FWSM);
if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
- return TRUE;
+ return true;
break;
case e1000_ich8lan:
- return TRUE;
+ return true;
default:
break;
}
- return FALSE;
+ return false;
}
for (i = 0; i < words; i++) {
if (hw->eeprom_shadow_ram != NULL &&
- hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
+ hw->eeprom_shadow_ram[offset+i].modified) {
data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
} else {
/* The NVM part needs a byte offset, hence * 2 */
if (hw->eeprom_shadow_ram != NULL) {
for (i = 0; i < words; i++) {
if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
- hw->eeprom_shadow_ram[offset+i].modified = TRUE;
+ hw->eeprom_shadow_ram[offset+i].modified = true;
hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
} else {
error = -E1000_ERR_EEPROM;
static int e1000_set_mac(struct net_device *netdev, void *p);
static irqreturn_t e1000_intr(int irq, void *data);
static irqreturn_t e1000_intr_msi(int irq, void *data);
-static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
- struct e1000_tx_ring *tx_ring);
+static bool e1000_clean_tx_irq(struct e1000_adapter *adapter,
+ struct e1000_tx_ring *tx_ring);
#ifdef CONFIG_E1000_NAPI
static int e1000_clean(struct napi_struct *napi, int budget);
-static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
- struct e1000_rx_ring *rx_ring,
- int *work_done, int work_to_do);
-static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
- struct e1000_rx_ring *rx_ring,
- int *work_done, int work_to_do);
+static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
+ struct e1000_rx_ring *rx_ring,
+ int *work_done, int work_to_do);
+static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
+ struct e1000_rx_ring *rx_ring,
+ int *work_done, int work_to_do);
#else
-static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
- struct e1000_rx_ring *rx_ring);
-static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
- struct e1000_rx_ring *rx_ring);
+static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
+ struct e1000_rx_ring *rx_ring);
+static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
+ struct e1000_rx_ring *rx_ring);
#endif
static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
struct e1000_rx_ring *rx_ring,
static void e1000_power_down_phy(struct e1000_adapter *adapter)
{
/* Power down the PHY so no link is implied when interface is down *
- * The PHY cannot be powered down if any of the following is TRUE *
+ * The PHY cannot be powered down if any of the following is true *
* (a) WoL is enabled
* (b) AMT is active
* (c) SoL/IDER session is active */
{
uint32_t pba = 0, tx_space, min_tx_space, min_rx_space;
uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
- boolean_t legacy_pba_adjust = FALSE;
+ bool legacy_pba_adjust = false;
/* Repartition Pba for greater than 9k mtu
* To take effect CTRL.RST is required.
case e1000_82540:
case e1000_82541:
case e1000_82541_rev_2:
- legacy_pba_adjust = TRUE;
+ legacy_pba_adjust = true;
pba = E1000_PBA_48K;
break;
case e1000_82545:
break;
case e1000_82547:
case e1000_82547_rev_2:
- legacy_pba_adjust = TRUE;
+ legacy_pba_adjust = true;
pba = E1000_PBA_30K;
break;
case e1000_82571:
break;
}
- if (legacy_pba_adjust == TRUE) {
+ if (legacy_pba_adjust) {
if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
pba -= 8; /* allocate more FIFO for Tx */
e1000_set_media_type(hw);
- hw->wait_autoneg_complete = FALSE;
- hw->tbi_compatibility_en = TRUE;
- hw->adaptive_ifs = TRUE;
+ hw->wait_autoneg_complete = false;
+ hw->tbi_compatibility_en = true;
+ hw->adaptive_ifs = true;
/* Copper options */
if (hw->media_type == e1000_media_type_copper) {
hw->mdix = AUTO_ALL_MODES;
- hw->disable_polarity_correction = FALSE;
+ hw->disable_polarity_correction = false;
hw->master_slave = E1000_MASTER_SLAVE;
}
* @start: address of beginning of memory
* @len: length of memory
**/
-static boolean_t
+static bool
e1000_check_64k_bound(struct e1000_adapter *adapter,
void *start, unsigned long len)
{
* write location to cross 64k boundary due to errata 23 */
if (adapter->hw.mac_type == e1000_82545 ||
adapter->hw.mac_type == e1000_82546) {
- return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
+ return ((begin ^ (end - 1)) >> 16) != 0 ? false : true;
}
- return TRUE;
+ return true;
}
/**
/* Enable 82543 Receive Checksum Offload for TCP and UDP */
if (hw->mac_type >= e1000_82543) {
rxcsum = E1000_READ_REG(hw, RXCSUM);
- if (adapter->rx_csum == TRUE) {
+ if (adapter->rx_csum) {
rxcsum |= E1000_RXCSUM_TUOFL;
/* Enable 82571 IPv4 payload checksum for UDP fragments
if (link) {
if (!netif_carrier_ok(netdev)) {
uint32_t ctrl;
- boolean_t txb2b = 1;
+ bool txb2b = true;
e1000_get_speed_and_duplex(&adapter->hw,
&adapter->link_speed,
&adapter->link_duplex);
adapter->tx_timeout_factor = 1;
switch (adapter->link_speed) {
case SPEED_10:
- txb2b = 0;
+ txb2b = false;
netdev->tx_queue_len = 10;
adapter->tx_timeout_factor = 8;
break;
case SPEED_100:
- txb2b = 0;
+ txb2b = false;
netdev->tx_queue_len = 100;
/* maybe add some timeout factor ? */
break;
if ((adapter->hw.mac_type == e1000_82571 ||
adapter->hw.mac_type == e1000_82572) &&
- txb2b == 0) {
+ !txb2b) {
uint32_t tarc0;
tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
tarc0 &= ~(1 << 21);
E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
/* Force detection of hung controller every watchdog period */
- adapter->detect_tx_hung = TRUE;
+ adapter->detect_tx_hung = true;
/* With 82571 controllers, LAA may be overwritten due to controller
* reset from the other port. Set the appropriate LAA in RAR[0] */
if (++i == tx_ring->count) i = 0;
tx_ring->next_to_use = i;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
-static boolean_t
+static bool
e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
struct sk_buff *skb)
{
if (unlikely(++i == tx_ring->count)) i = 0;
tx_ring->next_to_use = i;
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
#define E1000_MAX_TXD_PWR 12
* @adapter: board private structure
**/
-static boolean_t
+static bool
e1000_clean_tx_irq(struct e1000_adapter *adapter,
struct e1000_tx_ring *tx_ring)
{
#ifdef CONFIG_E1000_NAPI
unsigned int count = 0;
#endif
- boolean_t cleaned = FALSE;
+ bool cleaned = false;
unsigned int total_tx_bytes=0, total_tx_packets=0;
i = tx_ring->next_to_clean;
eop_desc = E1000_TX_DESC(*tx_ring, eop);
while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
- for (cleaned = FALSE; !cleaned; ) {
+ for (cleaned = false; !cleaned; ) {
tx_desc = E1000_TX_DESC(*tx_ring, i);
buffer_info = &tx_ring->buffer_info[i];
cleaned = (i == eop);
if (adapter->detect_tx_hung) {
/* Detect a transmit hang in hardware, this serializes the
* check with the clearing of time_stamp and movement of i */
- adapter->detect_tx_hung = FALSE;
+ adapter->detect_tx_hung = false;
if (tx_ring->buffer_info[eop].dma &&
time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
(adapter->tx_timeout_factor * HZ))
* @adapter: board private structure
**/
-static boolean_t
+static bool
#ifdef CONFIG_E1000_NAPI
e1000_clean_rx_irq(struct e1000_adapter *adapter,
struct e1000_rx_ring *rx_ring,
uint8_t last_byte;
unsigned int i;
int cleaned_count = 0;
- boolean_t cleaned = FALSE;
+ bool cleaned = false;
unsigned int total_rx_bytes=0, total_rx_packets=0;
i = rx_ring->next_to_clean;
next_buffer = &rx_ring->buffer_info[i];
- cleaned = TRUE;
+ cleaned = true;
cleaned_count++;
pci_unmap_single(pdev,
buffer_info->dma,
* @adapter: board private structure
**/
-static boolean_t
+static bool
#ifdef CONFIG_E1000_NAPI
e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
struct e1000_rx_ring *rx_ring,
unsigned int i, j;
uint32_t length, staterr;
int cleaned_count = 0;
- boolean_t cleaned = FALSE;
+ bool cleaned = false;
unsigned int total_rx_bytes=0, total_rx_packets=0;
i = rx_ring->next_to_clean;
next_buffer = &rx_ring->buffer_info[i];
- cleaned = TRUE;
+ cleaned = true;
cleaned_count++;
pci_unmap_single(pdev, buffer_info->dma,
buffer_info->length,
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