b43: use one shared function for setting MAC frequency
authorRafał Miłecki <zajec5@gmail.com>
Thu, 17 Jul 2014 17:31:05 +0000 (19:31 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 18 Jul 2014 17:45:26 +0000 (13:45 -0400)
By the way add few chipsets that were tracked with "wl" dumps.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/b43/main.c
drivers/net/wireless/b43/main.h
drivers/net/wireless/b43/phy_lcn.c
drivers/net/wireless/b43/phy_n.c
include/linux/bcma/bcma.h

index 3dcd3aa38608ff0daf41b084bfa2e6038ab449b2..3e127be06bfb988fe2d3a9eada52ccf21f4967fc 100644 (file)
@@ -2964,6 +2964,45 @@ void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
        }
 }
 
+/* brcms_b_switch_macfreq */
+void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode)
+{
+       u16 chip_id = dev->dev->chip_id;
+
+       if (chip_id == BCMA_CHIP_ID_BCM43217 ||
+           chip_id == BCMA_CHIP_ID_BCM43222 ||
+           chip_id == BCMA_CHIP_ID_BCM43224 ||
+           chip_id == BCMA_CHIP_ID_BCM43225 ||
+           chip_id == BCMA_CHIP_ID_BCM43227 ||
+           chip_id == BCMA_CHIP_ID_BCM43228) {
+               switch (spurmode) {
+               case 2: /* 126 Mhz */
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
+                       break;
+               case 1: /* 123 Mhz */
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
+                       break;
+               default: /* 120 Mhz */
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
+                       break;
+               }
+       } else if (dev->phy.type == B43_PHYTYPE_LCN) {
+               switch (spurmode) {
+               case 1: /* 82 Mhz */
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
+                       break;
+               default: /* 80 Mhz */
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
+                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
+                       break;
+               }
+       }
+}
+
 static void b43_adjust_opmode(struct b43_wldev *dev)
 {
        struct b43_wl *wl = dev->wl;
index f476fc337d64c8098ff7397bff7fedd2a9bcc4b0..9f22e4b4c13297207c309d7ea6a1fd884d061655 100644 (file)
@@ -99,6 +99,7 @@ void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags);
 void b43_mac_suspend(struct b43_wldev *dev);
 void b43_mac_enable(struct b43_wldev *dev);
 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on);
+void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode);
 
 
 struct b43_request_fw_context;
index 0bafa3b17035db8d5767da2632da343dd1ae70c7..e76bbdf3247e9b095af94bf907b2439f3f25f5f3 100644 (file)
@@ -54,39 +54,6 @@ enum lcn_sense_type {
        B43_SENSE_VBAT,
 };
 
-/* In theory it's PHY common function, move if needed */
-/* brcms_b_switch_macfreq */
-static void b43_phy_switch_macfreq(struct b43_wldev *dev, u8 spurmode)
-{
-       if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
-               switch (spurmode) {
-               case 2:         /* 126 Mhz */
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
-                       break;
-               case 1:         /* 123 Mhz */
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
-                       break;
-               default:        /* 120 Mhz */
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
-                       break;
-               }
-       } else if (dev->phy.type == B43_PHYTYPE_LCN) {
-               switch (spurmode) {
-               case 1:         /* 82 Mhz */
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
-                       break;
-               default:        /* 80 Mhz */
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC);
-                       break;
-               }
-       }
-}
-
 /**************************************************
  * Radio 2064.
  **************************************************/
@@ -609,7 +576,7 @@ static void b43_phy_lcn_txrx_spur_avoidance_mode(struct b43_wldev *dev,
                b43_phy_write(dev, 0x93b, ((0 << 13) + 23));
                b43_phy_write(dev, 0x93c, ((0 << 13) + 1989));
        }
-       b43_phy_switch_macfreq(dev, enable);
+       b43_mac_switch_freq(dev, enable);
 }
 
 /**************************************************
index ef1acaec7027c864e978e65487e8a53a40fa9dc3..0f0c1306b0adcfad46ec343b136bf4838cbb47bc 100644 (file)
@@ -6113,12 +6113,7 @@ static void b43_nphy_channel_setup(struct b43_wldev *dev,
 
                b43_nphy_pmu_spur_avoid(dev, avoid);
 
-               if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
-                   dev->dev->chip_id == 43225) {
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
-                                   avoid ? 0x5341 : 0x8889);
-                       b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
-               }
+               b43_mac_switch_freq(dev, avoid);
 
                if (dev->phy.rev == 3 || dev->phy.rev == 4)
                        ; /* TODO: reset PLL */
index 7cb2344741cf843d0ce372e528006744cebf3a29..969af0f2bdf92cdaf14d5e040a6b76f70dd32984 100644 (file)
@@ -159,6 +159,7 @@ struct bcma_host_ops {
 #define BCMA_CHIP_ID_BCM4313   0x4313
 #define BCMA_CHIP_ID_BCM43142  43142
 #define BCMA_CHIP_ID_BCM43217  43217
+#define BCMA_CHIP_ID_BCM43222  43222
 #define BCMA_CHIP_ID_BCM43224  43224
 #define  BCMA_PKG_ID_BCM43224_FAB_CSM  0x8
 #define  BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa