arm: omap5: tps659038: rename regulator defines
authorFelipe Balbi <balbi@ti.com>
Thu, 6 Nov 2014 14:28:43 +0000 (08:28 -0600)
committerTom Rini <trini@ti.com>
Thu, 4 Dec 2014 16:04:13 +0000 (11:04 -0500)
Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/include/asm/arch-omap5/clock.h

index 025738302a2878a6bdd59476d67338a532ee2b5c..8b4d53a7112565b56c47b2b7af65d9076631a476 100644 (file)
@@ -365,31 +365,31 @@ struct vcores_data dra752_volts = {
        .mpu.value      = VDD_MPU_DRA752,
        .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
        .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .mpu.addr       = TPS659038_REG_ADDR_SMPS12_MPU,
+       .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
        .mpu.pmic       = &tps659038,
 
        .eve.value      = VDD_EVE_DRA752,
        .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
        .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .eve.addr       = TPS659038_REG_ADDR_SMPS45_EVE,
+       .eve.addr       = TPS659038_REG_ADDR_SMPS45,
        .eve.pmic       = &tps659038,
 
        .gpu.value      = VDD_GPU_DRA752,
        .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
        .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .gpu.addr       = TPS659038_REG_ADDR_SMPS6_GPU,
+       .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
        .gpu.pmic       = &tps659038,
 
        .core.value     = VDD_CORE_DRA752,
        .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
        .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-       .core.addr      = TPS659038_REG_ADDR_SMPS7_CORE,
+       .core.addr      = TPS659038_REG_ADDR_SMPS7,
        .core.pmic      = &tps659038,
 
        .iva.value      = VDD_IVA_DRA752,
        .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
        .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
-       .iva.addr       = TPS659038_REG_ADDR_SMPS8_IVA,
+       .iva.addr       = TPS659038_REG_ADDR_SMPS8,
        .iva.pmic       = &tps659038,
 };
 
index 30d9de276492caf863b3d93429cb099bfdb9e0e4..7eacba2686286539b0405192b9502e88fa888a09 100644 (file)
 
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR               0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU          0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE          0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU           0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE          0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA           0x37
+#define TPS659038_REG_ADDR_SMPS12              0x23
+#define TPS659038_REG_ADDR_SMPS45              0x2B
+#define TPS659038_REG_ADDR_SMPS6               0x2F
+#define TPS659038_REG_ADDR_SMPS7               0x33
+#define TPS659038_REG_ADDR_SMPS8               0x37
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60