rcar_gen3: drivers: rpc: Modify PFC code

Modify PFC code and rename macro of MFIS according to Errata of
Hardware User's Manual

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac

diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c
index f7d8ec08a0c559f72e1ccd4e8d3864c0a9aa2a75..ece3462f450eaa0ddc09534ecd4c347bf7a6b767 100644 (file)
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/rcar/auth/auth_mod.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
  * reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -25,7 +25,7 @@ extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
 #define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
 #define        RST_BASE                (0xE6160000U)
 #define        RST_MODEMR              (RST_BASE + 0x0060U)
-#define        MFISSOFTMDR             (0xE6260600U)
+#define        MFISOFTMDR              (0xE6260600U)
 #define        MODEMR_MD5_MASK         (0x00000020U)
 #define        MODEMR_MD5_SHIFT        (5U)
 #define        SOFTMD_BOOTMODE_MASK    (0x00000001U)
@@ -139,7 +139,7 @@ static int32_t normal_boot_verify(uint32_t a, uint32_t b, void *c)
 void auth_mod_init(void)
 {
 #if RCAR_SECURE_BOOT
-       uint32_t soft_md = mmio_read_32(MFISSOFTMDR) & SOFTMD_BOOTMODE_MASK;
+       uint32_t soft_md = mmio_read_32(MFISOFTMDR) & SOFTMD_BOOTMODE_MASK;
        uint32_t md = mmio_read_32(RST_MODEMR) & MODEMR_MD5_MASK;
        uint32_t lcs, ret;
 

diff --git a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
index 7e9bde9d47aed14671e9ec2c95aa4565becd5290..aaa3b434a31e6461dcf3b55eedf034bb00c3883a 100644 (file)
--- a/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
+++ b/drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
@@ -610,7 +610,7 @@ void pfc_init_d3(void)
 
        /* initialize POC control register */
        pfc_reg_write(PFC_POCCTRL0,   0xC00FFFFFU);
-       pfc_reg_write(PFC_POCCTRL1,   0XFFFFFFFEU);
+       pfc_reg_write(PFC_POCCTRL2,   0XFFFFFFFEU);
        pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
 
        /* initialize LSI pin pull-up/down control */

diff --git a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
index 2946cbaaccdebee9b4ce263408fbff2a2005d07e..bd0048ebbfdc3b23928183cf565928f3259fef8e 100644 (file)
--- a/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
+++ b/drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -122,7 +122,7 @@
 #define GPSR5_SCK2_A           BIT(7)
 #define GPSR5_TX1              BIT(6)
 #define GPSR5_RX1              BIT(5)
-#define GPSR5_RTS0_TANS_A      BIT(4)
+#define GPSR5_RTS0_A           BIT(4)
 #define GPSR5_CTS0_A           BIT(3)
 #define GPSR5_TX0_A            BIT(2)
 #define GPSR5_RX0_A            BIT(1)
@@ -155,7 +155,7 @@
 #define IPSR_4_FUNC(x)         ((uint32_t)(x) << 4U)
 #define IPSR_0_FUNC(x)         ((uint32_t)(x) << 0U)
 
-#define IOCTRL30_MASK          (0x0007F000U)
+#define POCCTRL0_MASK          (0x0007F000U)
 #define POC_SD3_DS_33V         BIT(29)
 #define POC_SD3_DAT7_33V       BIT(28)
 #define POC_SD3_DAT6_33V       BIT(27)
@@ -180,7 +180,7 @@
 #define POC_SD0_CMD_33V                BIT(1)
 #define POC_SD0_CLK_33V                BIT(0)
 
-#define IOCTRL32_MASK          (0xFFFFFFFEU)
+#define POCCTRL2_MASK          (0xFFFFFFFEU)
 #define POC2_VREF_33V          BIT(0)
 
 #define MOD_SEL0_ADGB_A                ((uint32_t)0U << 29U)
@@ -561,7 +561,7 @@ void pfc_init_e3(void)
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
                      | GPSR5_SCK2_A
-                     | GPSR5_RTS0_TANS_A
+                     | GPSR5_RTS0_A
                      | GPSR5_CTS0_A);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
                      | GPSR6_SSI_SDATA6
@@ -581,7 +581,7 @@ void pfc_init_e3(void)
 
        /* initialize POC control */
        reg = mmio_read_32(PFC_POCCTRL0);
-       reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
+       reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
               | POC_SD1_DAT2_33V
               | POC_SD1_DAT1_33V
               | POC_SD1_DAT0_33V
@@ -594,9 +594,9 @@ void pfc_init_e3(void)
               | POC_SD0_CMD_33V
               | POC_SD0_CLK_33V);
        pfc_reg_write(PFC_POCCTRL0, reg);
-       reg = mmio_read_32(PFC_POCCTRL1);
-       reg = (reg & IOCTRL32_MASK);
-       pfc_reg_write(PFC_POCCTRL1, reg);
+       reg = mmio_read_32(PFC_POCCTRL2);
+       reg = (reg & POCCTRL2_MASK);
+       pfc_reg_write(PFC_POCCTRL2, reg);
 
        /* initialize LSI pin pull-up/down control */
        pfc_reg_write(PFC_PUD0, 0xFDF80000U);

diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
index 7287c833915a1c0d2f4ec78544b3ca5d09eb1c64..effdc767ec55e2372d383e9f6cf6098245c4a6fe 100644 (file)
--- a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -119,11 +119,11 @@
 #define GPSR5_RX2_A            BIT(11)
 #define GPSR5_TX2_A            BIT(10)
 #define GPSR5_SCK2             BIT(9)
-#define GPSR5_RTS1_TANS                BIT(8)
+#define GPSR5_RTS1             BIT(8)
 #define GPSR5_CTS1             BIT(7)
 #define GPSR5_TX1_A            BIT(6)
 #define GPSR5_RX1_A            BIT(5)
-#define GPSR5_RTS0_TANS                BIT(4)
+#define GPSR5_RTS0             BIT(4)
 #define GPSR5_CTS0             BIT(3)
 #define GPSR5_TX0              BIT(2)
 #define GPSR5_RX0              BIT(1)
@@ -160,8 +160,6 @@
 #define GPSR6_SSI_SDATA0       BIT(2)
 #define GPSR6_SSI_WS0129       BIT(1)
 #define GPSR6_SSI_SCK0129      BIT(0)
-#define GPSR7_HDMI1_CEC                BIT(3)
-#define GPSR7_HDMI0_CEC                BIT(2)
 #define GPSR7_AVS2             BIT(1)
 #define GPSR7_AVS1             BIT(0)
 
@@ -323,8 +321,8 @@
 #define DRVCTRL11_D15(x)       ((uint32_t)(x) << 24U)
 #define DRVCTRL11_AVS1(x)      ((uint32_t)(x) << 20U)
 #define DRVCTRL11_AVS2(x)      ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x)    ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)    ((uint32_t)(x) << 8U)
 #define DRVCTRL11_DU_DOTCLKIN0(x)      ((uint32_t)(x) << 4U)
 #define DRVCTRL11_DU_DOTCLKIN1(x)      ((uint32_t)(x) << 0U)
 #define DRVCTRL12_DU_DOTCLKIN2(x)      ((uint32_t)(x) << 28U)
@@ -673,7 +671,6 @@ void pfc_init_h3_v1(void)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
-                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(6)
                      | IPSR_4_FUNC(6)
                      | IPSR_0_FUNC(6));
@@ -829,11 +826,11 @@ void pfc_init_h3_v1(void)
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
                      | GPSR5_SCK2
-                     | GPSR5_RTS1_TANS
+                     | GPSR5_RTS1
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
                      | GPSR5_RX1_A
-                     | GPSR5_RTS0_TANS
+                     | GPSR5_RTS0
                      | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
@@ -856,9 +853,7 @@ void pfc_init_h3_v1(void)
                      | GPSR6_SSI_SDATA0
                      | GPSR6_SSI_WS0129
                      | GPSR6_SSI_SCK0129);
-       pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC
-                     | GPSR7_AVS2
+       pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
                      | GPSR7_AVS1);
 
        /* initialize POC control register */
@@ -996,8 +991,8 @@ void pfc_init_h3_v1(void)
               | DRVCTRL11_D15(3)
               | DRVCTRL11_AVS1(7)
               | DRVCTRL11_AVS2(7)
-              | DRVCTRL11_HDMI0_CEC(7)
-              | DRVCTRL11_HDMI1_CEC(7)
+              | DRVCTRL11_GP7_02(7)
+              | DRVCTRL11_GP7_03(7)
               | DRVCTRL11_DU_DOTCLKIN0(3)
               | DRVCTRL11_DU_DOTCLKIN1(3));
        pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1153,6 +1148,7 @@ void pfc_init_h3_v1(void)
        mmio_write_32(GPIO_POSNEG4, 0x00000000U);
        mmio_write_32(GPIO_POSNEG5, 0x00000000U);
        mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+       mmio_write_32(GPIO_POSNEG7, 0x00000000U);
 
        /* initialize general IO/interrupt switching */
        mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1162,6 +1158,7 @@ void pfc_init_h3_v1(void)
        mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+       mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
 
        /* initialize general output register */
        mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1182,4 +1179,5 @@ void pfc_init_h3_v1(void)
        mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
 #endif
        mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+       mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
 }

diff --git a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
index 8bba3c150687079b1812ab5785be13350e085847..a54b14b37f713964b1e455d05996751405008320 100644 (file)
--- a/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+++ b/drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -121,11 +121,11 @@
 #define GPSR5_RX2_A            BIT(11)
 #define GPSR5_TX2_A            BIT(10)
 #define GPSR5_SCK2             BIT(9)
-#define GPSR5_RTS1_TANS                BIT(8)
+#define GPSR5_RTS1             BIT(8)
 #define GPSR5_CTS1             BIT(7)
 #define GPSR5_TX1_A            BIT(6)
 #define GPSR5_RX1_A            BIT(5)
-#define GPSR5_RTS0_TANS                BIT(4)
+#define GPSR5_RTS0             BIT(4)
 #define GPSR5_CTS0             BIT(3)
 #define GPSR5_TX0              BIT(2)
 #define GPSR5_RX0              BIT(1)
@@ -162,8 +162,6 @@
 #define GPSR6_SSI_SDATA0       BIT(2)
 #define GPSR6_SSI_WS0129       BIT(1)
 #define GPSR6_SSI_SCK0129      BIT(0)
-#define GPSR7_HDMI1_CEC                BIT(3)
-#define GPSR7_HDMI0_CEC                BIT(2)
 #define GPSR7_AVS2             BIT(1)
 #define GPSR7_AVS1             BIT(0)
 
@@ -325,8 +323,8 @@
 #define DRVCTRL11_D15(x)       ((uint32_t)(x) << 24U)
 #define DRVCTRL11_AVS1(x)      ((uint32_t)(x) << 20U)
 #define DRVCTRL11_AVS2(x)      ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x)    ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)    ((uint32_t)(x) << 8U)
 #define DRVCTRL11_DU_DOTCLKIN0(x)      ((uint32_t)(x) << 4U)
 #define DRVCTRL11_DU_DOTCLKIN1(x)      ((uint32_t)(x) << 0U)
 #define DRVCTRL12_DU_DOTCLKIN2(x)      ((uint32_t)(x) << 28U)
@@ -697,7 +695,6 @@ void pfc_init_h3_v2(void)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
-                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(6)
                      | IPSR_4_FUNC(6)
                      | IPSR_0_FUNC(6));
@@ -862,11 +859,11 @@ void pfc_init_h3_v2(void)
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
                      | GPSR5_SCK2
-                     | GPSR5_RTS1_TANS
+                     | GPSR5_RTS1
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
                      | GPSR5_RX1_A
-                     | GPSR5_RTS0_TANS
+                     | GPSR5_RTS0
                      | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
@@ -889,9 +886,7 @@ void pfc_init_h3_v2(void)
                      | GPSR6_SSI_SDATA0
                      | GPSR6_SSI_WS0129
                      | GPSR6_SSI_SCK0129);
-       pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC
-                     | GPSR7_AVS2
+       pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
                      | GPSR7_AVS1);
 
        /* initialize POC control register */
@@ -1029,8 +1024,8 @@ void pfc_init_h3_v2(void)
               | DRVCTRL11_D15(3)
               | DRVCTRL11_AVS1(7)
               | DRVCTRL11_AVS2(7)
-              | DRVCTRL11_HDMI0_CEC(7)
-              | DRVCTRL11_HDMI1_CEC(7)
+              | DRVCTRL11_GP7_02(7)
+              | DRVCTRL11_GP7_03(7)
               | DRVCTRL11_DU_DOTCLKIN0(3)
               | DRVCTRL11_DU_DOTCLKIN1(3));
        pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1186,6 +1181,7 @@ void pfc_init_h3_v2(void)
        mmio_write_32(GPIO_POSNEG4, 0x00000000U);
        mmio_write_32(GPIO_POSNEG5, 0x00000000U);
        mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+       mmio_write_32(GPIO_POSNEG7, 0x00000000U);
 
        /* initialize general IO/interrupt switching */
        mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1195,6 +1191,7 @@ void pfc_init_h3_v2(void)
        mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+       mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
 
        /* initialize general output register */
        mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1215,4 +1212,5 @@ void pfc_init_h3_v2(void)
        mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
 #endif
        mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+       mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
 }

diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
index 380899d3aea53b905d9aeca04119f71a47a92a80..0aa3bffce0ad1d12f5716523c3bc43cbbdb84efc 100644 (file)
--- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -124,11 +124,11 @@
 #define GPSR5_RX2_A            BIT(11)
 #define GPSR5_TX2_A            BIT(10)
 #define GPSR5_SCK2             BIT(9)
-#define GPSR5_RTS1_TANS                BIT(8)
+#define GPSR5_RTS1             BIT(8)
 #define GPSR5_CTS1             BIT(7)
 #define GPSR5_TX1_A            BIT(6)
 #define GPSR5_RX1_A            BIT(5)
-#define GPSR5_RTS0_TANS                BIT(4)
+#define GPSR5_RTS0             BIT(4)
 #define GPSR5_CTS0             BIT(3)
 #define GPSR5_TX0              BIT(2)
 #define GPSR5_RX0              BIT(1)
@@ -165,8 +165,6 @@
 #define GPSR6_SSI_SDATA0       BIT(2)
 #define GPSR6_SSI_WS0129       BIT(1)
 #define GPSR6_SSI_SCK0129      BIT(0)
-#define GPSR7_HDMI1_CEC                BIT(3)
-#define GPSR7_HDMI0_CEC                BIT(2)
 #define GPSR7_AVS2             BIT(1)
 #define GPSR7_AVS1             BIT(0)
 
@@ -328,8 +326,8 @@
 #define DRVCTRL11_D15(x)       ((uint32_t)(x) << 24U)
 #define DRVCTRL11_AVS1(x)      ((uint32_t)(x) << 20U)
 #define DRVCTRL11_AVS2(x)      ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x)    ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)    ((uint32_t)(x) << 8U)
 #define DRVCTRL11_DU_DOTCLKIN0(x)      ((uint32_t)(x) << 4U)
 #define DRVCTRL11_DU_DOTCLKIN1(x)      ((uint32_t)(x) << 0U)
 #define DRVCTRL12_DU_DOTCLKIN2(x)      ((uint32_t)(x) << 28U)
@@ -792,7 +790,6 @@ void pfc_init_m3(void)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
-                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(6)
                      | IPSR_4_FUNC(6)
                      | IPSR_0_FUNC(6));
@@ -957,11 +954,11 @@ void pfc_init_m3(void)
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
                      | GPSR5_SCK2
-                     | GPSR5_RTS1_TANS
+                     | GPSR5_RTS1
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
                      | GPSR5_RX1_A
-                     | GPSR5_RTS0_TANS
+                     | GPSR5_RTS0
                      | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
@@ -984,9 +981,7 @@ void pfc_init_m3(void)
                      | GPSR6_SSI_SDATA0
                      | GPSR6_SSI_WS0129
                      | GPSR6_SSI_SCK0129);
-       pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC
-                     | GPSR7_AVS2
+       pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
                      | GPSR7_AVS1);
 
        /* initialize POC control register */
@@ -1124,8 +1119,8 @@ void pfc_init_m3(void)
               | DRVCTRL11_D15(3)
               | DRVCTRL11_AVS1(7)
               | DRVCTRL11_AVS2(7)
-              | DRVCTRL11_HDMI0_CEC(7)
-              | DRVCTRL11_HDMI1_CEC(7)
+              | DRVCTRL11_GP7_02(7)
+              | DRVCTRL11_GP7_03(7)
               | DRVCTRL11_DU_DOTCLKIN0(3)
               | DRVCTRL11_DU_DOTCLKIN1(3));
        pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1281,6 +1276,7 @@ void pfc_init_m3(void)
        mmio_write_32(GPIO_POSNEG4, 0x00000000U);
        mmio_write_32(GPIO_POSNEG5, 0x00000000U);
        mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+       mmio_write_32(GPIO_POSNEG7, 0x00000000U);
 
        /* initialize general IO/interrupt switching */
        mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1290,6 +1286,7 @@ void pfc_init_m3(void)
        mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+       mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
 
        /* initialize general output register */
        mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1310,4 +1307,5 @@ void pfc_init_m3(void)
        mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
 #endif
        mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+       mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
 }

diff --git a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
index 3fac3758e9feaf7458f4146496609e2bf63caa55..501455610d9890297b9dc8c3e334978de53a9ce8 100644 (file)
--- a/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+++ b/drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -123,11 +123,11 @@
 #define GPSR5_RX2_A            BIT(11)
 #define GPSR5_TX2_A            BIT(10)
 #define GPSR5_SCK2             BIT(9)
-#define GPSR5_RTS1_TANS                BIT(8)
+#define GPSR5_RTS1             BIT(8)
 #define GPSR5_CTS1             BIT(7)
 #define GPSR5_TX1_A            BIT(6)
 #define GPSR5_RX1_A            BIT(5)
-#define GPSR5_RTS0_TANS                BIT(4)
+#define GPSR5_RTS0             BIT(4)
 #define GPSR5_CTS0             BIT(3)
 #define GPSR5_TX0              BIT(2)
 #define GPSR5_RX0              BIT(1)
@@ -164,8 +164,6 @@
 #define GPSR6_SSI_SDATA0       BIT(2)
 #define GPSR6_SSI_WS0129       BIT(1)
 #define GPSR6_SSI_SCK0129      BIT(0)
-#define GPSR7_HDMI1_CEC                BIT(3)
-#define GPSR7_HDMI0_CEC                BIT(2)
 #define GPSR7_AVS2             BIT(1)
 #define GPSR7_AVS1             BIT(0)
 
@@ -327,8 +325,8 @@
 #define DRVCTRL11_D15(x)       ((uint32_t)(x) << 24U)
 #define DRVCTRL11_AVS1(x)      ((uint32_t)(x) << 20U)
 #define DRVCTRL11_AVS2(x)      ((uint32_t)(x) << 16U)
-#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
-#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_GP7_02(x)    ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x)    ((uint32_t)(x) << 8U)
 #define DRVCTRL11_DU_DOTCLKIN0(x)      ((uint32_t)(x) << 4U)
 #define DRVCTRL11_DU_DOTCLKIN1(x)      ((uint32_t)(x) << 0U)
 #define DRVCTRL12_DU_DOTCLKIN2(x)      ((uint32_t)(x) << 28U)
@@ -699,7 +697,6 @@ void pfc_init_m3n(void)
                      | IPSR_24_FUNC(0)
                      | IPSR_20_FUNC(0)
                      | IPSR_16_FUNC(0)
-                     | IPSR_12_FUNC(0)
                      | IPSR_8_FUNC(6)
                      | IPSR_4_FUNC(6)
                      | IPSR_0_FUNC(6));
@@ -864,11 +861,11 @@ void pfc_init_m3n(void)
                      | GPSR5_RX2_A
                      | GPSR5_TX2_A
                      | GPSR5_SCK2
-                     | GPSR5_RTS1_TANS
+                     | GPSR5_RTS1
                      | GPSR5_CTS1
                      | GPSR5_TX1_A
                      | GPSR5_RX1_A
-                     | GPSR5_RTS0_TANS
+                     | GPSR5_RTS0
                      | GPSR5_SCK0);
        pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
                      | GPSR6_USB30_PWEN
@@ -891,9 +888,7 @@ void pfc_init_m3n(void)
                      | GPSR6_SSI_SDATA0
                      | GPSR6_SSI_WS0129
                      | GPSR6_SSI_SCK0129);
-       pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
-                     | GPSR7_HDMI0_CEC
-                     | GPSR7_AVS2
+       pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
                      | GPSR7_AVS1);
 
        /* initialize POC control register */
@@ -1031,8 +1026,8 @@ void pfc_init_m3n(void)
               | DRVCTRL11_D15(3)
               | DRVCTRL11_AVS1(7)
               | DRVCTRL11_AVS2(7)
-              | DRVCTRL11_HDMI0_CEC(7)
-              | DRVCTRL11_HDMI1_CEC(7)
+              | DRVCTRL11_GP7_02(7)
+              | DRVCTRL11_GP7_03(7)
               | DRVCTRL11_DU_DOTCLKIN0(3)
               | DRVCTRL11_DU_DOTCLKIN1(3));
        pfc_reg_write(PFC_DRVCTRL11, reg);
@@ -1188,6 +1183,7 @@ void pfc_init_m3n(void)
        mmio_write_32(GPIO_POSNEG4, 0x00000000U);
        mmio_write_32(GPIO_POSNEG5, 0x00000000U);
        mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+       mmio_write_32(GPIO_POSNEG7, 0x00000000U);
 
        /* initialize general IO/interrupt switching */
        mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@@ -1197,6 +1193,7 @@ void pfc_init_m3n(void)
        mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
        mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+       mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
 
        /* initialize general output register */
        mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@@ -1217,4 +1214,5 @@ void pfc_init_m3n(void)
        mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
 #endif
        mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+       mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
 }

diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
index 51d6f427cc7687141d825150b660a9b7a9445fc5..60637580745547d1fa23f5d8034328d6693e720a 100644 (file)
--- a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -709,7 +709,7 @@ void pfc_init_v3m(void)
                                   | IOCTRL31_POC_VI0_DATA7
                                   | IOCTRL31_POC_VI0_DATA6);
 
-       pfc_reg_write(PFC_POCCTRL1, 0x00000000);
+       pfc_reg_write(PFC_POCCTRL2, 0x00000000);
 
        pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
 

diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
index b0b4e6fd99abf1482a2e8a3aeba09706c419ba21..e7dd54397f9645e7bff9e6785acee10cb01d980d 100644 (file)
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -206,7 +206,7 @@
 #define PFC_DRVCTRL24          (PFC_BASE + 0x0360U)
 #define PFC_POCCTRL0           (PFC_BASE + 0x0380U)
 #define PFC_IOCTRL31           (PFC_BASE + 0x0384U)
-#define PFC_POCCTRL1           (PFC_BASE + 0x0388U)
+#define PFC_POCCTRL2           (PFC_BASE + 0x0388U)
 #define PFC_TDSELCTRL0         (PFC_BASE + 0x03C0U)
 #define PFC_IOCTRL             (PFC_BASE + 0x03E0U)
 #define PFC_TSREG              (PFC_BASE + 0x03E4U)