imx: Add support for the SabreSD shipped with i.MX6DL
authorPierre Aubert <p.aubert@staubli.com>
Tue, 4 Jun 2013 07:00:15 +0000 (09:00 +0200)
committerStefano Babic <sbabic@denx.de>
Wed, 26 Jun 2013 15:34:11 +0000 (17:34 +0200)
The SabreSD platform is available with i.MX6Q or i.MX6DL. This patch adds the
support of the i.MX6DL. The config file and the board directory are renamed
to remove the reference to the MX6Q.

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
MAINTAINERS
board/freescale/mx6qsabresd/Makefile [deleted file]
board/freescale/mx6qsabresd/mx6qsabresd.c [deleted file]
board/freescale/mx6sabresd/Makefile [new file with mode: 0644]
board/freescale/mx6sabresd/mx6sabresd.c [new file with mode: 0644]
boards.cfg
include/configs/mx6qsabre_common.h [deleted file]
include/configs/mx6qsabreauto.h
include/configs/mx6qsabresd.h [deleted file]
include/configs/mx6sabre_common.h [new file with mode: 0644]
include/configs/mx6sabresd.h [new file with mode: 0644]

index d3b7e1a543dc538515f7e04890d3896782c077ea..e753e037e9c76638efac5f764b5590e47c594d8e 100644 (file)
@@ -662,7 +662,7 @@ Fabio Estevam <fabio.estevam@freescale.com>
        mx31pdk         i.MX31
        mx53ard         i.MX53
        mx53smd         i.MX53
-       mx6qsabresd     i.MX6Q
+       mx6sabresd      i.MX6Q/DL
        mx6qsabreauto   i.MX6Q
        wandboard       i.MX6DL/S
        mx6slevk        i.MX6SL
diff --git a/board/freescale/mx6qsabresd/Makefile b/board/freescale/mx6qsabresd/Makefile
deleted file mode 100644 (file)
index 5693772..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  := mx6qsabresd.o
-
-SRCS   := $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-
-$(LIB):        $(obj).depend $(OBJS)
-       $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
deleted file mode 100644 (file)
index 2529826..0000000
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
-#include <asm/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
-       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
-       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
-       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
-       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
-       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-int dram_init(void)
-{
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-       return 0;
-}
-
-iomux_v3_cfg_t const uart1_pads[] = {
-       MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
-       MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       /* AR8031 PHY Reset */
-       MX6_PAD_ENET_CRS_DV__GPIO_1_25          | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
-       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
-       /* Reset AR8031 PHY */
-       gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-       udelay(500);
-       gpio_set_value(IMX_GPIO_NR(1, 25), 1);
-}
-
-iomux_v3_cfg_t const usdhc2_pads[] = {
-       MX6_PAD_SD2_CLK__USDHC2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD2_CMD__USDHC2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD2_DAT0__USDHC2_DAT0   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD2_DAT1__USDHC2_DAT1   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD2_DAT2__USDHC2_DAT2   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD2_DAT3__USDHC2_DAT3   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D4__USDHC2_DAT4   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D5__USDHC2_DAT5   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D6__USDHC2_DAT6   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D7__USDHC2_DAT7   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
-       MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const usdhc4_pads[] = {
-       MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
-       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
-       {USDHC2_BASE_ADDR},
-       {USDHC3_BASE_ADDR},
-       {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-       int ret = 0;
-
-       switch (cfg->esdhc_base) {
-       case USDHC2_BASE_ADDR:
-               ret = !gpio_get_value(USDHC2_CD_GPIO);
-               break;
-       case USDHC3_BASE_ADDR:
-               ret = !gpio_get_value(USDHC3_CD_GPIO);
-               break;
-       case USDHC4_BASE_ADDR:
-               ret = 1; /* eMMC/uSDHC4 is always present */
-               break;
-       }
-
-       return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-       s32 status = 0;
-       int i;
-
-       /*
-        * According to the board_mmc_init() the following map is done:
-        * (U-boot device node)    (Physical Port)
-        * mmc0                    SD2
-        * mmc1                    SD3
-        * mmc2                    eMMC
-        */
-       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-               switch (i) {
-               case 0:
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-                       gpio_direction_input(USDHC2_CD_GPIO);
-                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-                       break;
-               case 1:
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-                       gpio_direction_input(USDHC3_CD_GPIO);
-                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-                       break;
-               case 2:
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-                       break;
-               default:
-                       printf("Warning: you configured more USDHC controllers"
-                              "(%d) then supported by the board (%d)\n",
-                              i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-                       return status;
-               }
-
-               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-       }
-
-       return status;
-}
-#endif
-
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-       unsigned short val;
-
-       /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-       val &= 0xffe3;
-       val |= 0x18;
-       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-       /* introduce tx clock delay */
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-       val |= 0x0100;
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-       return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-       mx6_rgmii_rework(phydev);
-
-       if (phydev->drv->config)
-               phydev->drv->config(phydev);
-
-       return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-       int ret;
-
-       setup_iomux_enet();
-
-       ret = cpu_eth_init(bis);
-       if (ret)
-               printf("FEC MXC: %s:failed\n", __func__);
-
-       return 0;
-}
-
-int board_early_init_f(void)
-{
-       setup_iomux_uart();
-
-       return 0;
-}
-
-int board_init(void)
-{
-       /* address of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-       return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-       /* 4 bit bus width */
-       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
-       {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-       /* 8 bit bus width */
-       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
-       {NULL,   0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
-       add_board_boot_modes(board_boot_modes);
-#endif
-
-       return 0;
-}
-
-int checkboard(void)
-{
-       puts("Board: MX6Q-SabreSD\n");
-
-       return 0;
-}
diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile
new file mode 100644 (file)
index 0000000..ff3c94b
--- /dev/null
@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := mx6sabresd.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
new file mode 100644 (file)
index 0000000..222ee98
--- /dev/null
@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+       return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+       MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+       MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TXC__ENET_RGMII_TXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD0__ENET_RGMII_TD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD1__ENET_RGMII_TD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD2__ENET_RGMII_TD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TD3__ENET_RGMII_TD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RXC__ENET_RGMII_RXC       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD0__ENET_RGMII_RD0       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD1__ENET_RGMII_RD1       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD2__ENET_RGMII_RD2       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RD3__ENET_RGMII_RD3       | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       /* AR8031 PHY Reset */
+       MX6_PAD_ENET_CRS_DV__GPIO_1_25          | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+       /* Reset AR8031 PHY */
+       gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+       udelay(500);
+       gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6_PAD_SD2_CLK__USDHC2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_CMD__USDHC2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT0__USDHC2_DAT0   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT1__USDHC2_DAT1   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT2__USDHC2_DAT2   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT3__USDHC2_DAT3   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D4__USDHC2_DAT4   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D5__USDHC2_DAT5   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D6__USDHC2_DAT6   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D7__USDHC2_DAT7   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D2__GPIO_2_2      | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+       MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR},
+       {USDHC3_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               ret = !gpio_get_value(USDHC2_CD_GPIO);
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = !gpio_get_value(USDHC3_CD_GPIO);
+               break;
+       case USDHC4_BASE_ADDR:
+               ret = 1; /* eMMC/uSDHC4 is always present */
+               break;
+       }
+
+       return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       s32 status = 0;
+       int i;
+
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * mmc0                    SD2
+        * mmc1                    SD3
+        * mmc2                    eMMC
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                              "(%d) then supported by the board (%d)\n",
+                              i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+                       return status;
+               }
+
+               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+       }
+
+       return status;
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+       unsigned short val;
+
+       /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+       val &= 0xffe3;
+       val |= 0x18;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+       /* introduce tx clock delay */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+       val |= 0x0100;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       mx6_rgmii_rework(phydev);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+
+       setup_iomux_enet();
+
+       ret = cpu_eth_init(bis);
+       if (ret)
+               printf("FEC MXC: %s:failed\n", __func__);
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       setup_iomux_uart();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+       /* 4 bit bus width */
+       {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+       {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+       /* 8 bit bus width */
+       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+       {NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+       add_board_boot_modes(board_boot_modes);
+#endif
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: MX6-SabreSD\n");
+       return 0;
+}
index 2635942e122319162f97b5f02a9b81d7f08891f1..db56488ddc1ba3513536138b5805500f1658294a 100644 (file)
@@ -258,9 +258,10 @@ ima3-mx53                    arm         armv7       ima3-mx53           esg
 vision2                      arm         armv7       vision2             ttcontrol      mx5            vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 cgtqmx6qeval                            arm             armv7           cgtqmx6eval             congatec               mx6             cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6            mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6            mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+mx6qsabreauto                arm         armv7       mx6qsabreauto       freescale      mx6            mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6            mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
-mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6            mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6dlsabresd                 arm         armv7       mx6sabresd          freescale      mx6            mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
+mx6qsabresd                  arm         armv7       mx6sabresd          freescale      mx6            mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
 mx6slevk                     arm         armv7       mx6slevk            freescale      mx6            mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 titanium                     arm         armv7       titanium            freescale      mx6            titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
 vf610twr                     arm         armv7       vf610twr            freescale      vf610          vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
deleted file mode 100644 (file)
index bfaa420..0000000
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale i.MX6Q SabreSD board.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MX6QSABRE_COMMON_CONFIG_H
-#define __MX6QSABRE_COMMON_CONFIG_H
-
-#define CONFIG_MX6
-#define CONFIG_MX6Q
-
-#include "mx6_common.h"
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_MXC_UART
-
-/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
-
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_MII
-#define IMX_FEC_BASE                   ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE            RGMII
-#define CONFIG_ETHPRIME                        "FEC"
-#define CONFIG_FEC_MXC_PHYADDR         1
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX              1
-#define CONFIG_BAUDRATE                        115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_SETEXPR
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY               1
-
-#define CONFIG_LOADADDR                        0x12000000
-#define CONFIG_SYS_TEXT_BASE           0x17800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-       "script=boot.scr\0" \
-       "uimage=uImage\0" \
-       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-       "fdt_addr=0x11000000\0" \
-       "boot_fdt=try\0" \
-       "ip_dyn=yes\0" \
-       "console=" CONFIG_CONSOLE_DEV "\0" \
-       "fdt_high=0xffffffff\0"   \
-       "initrd_high=0xffffffff\0" \
-       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-       "mmcpart=1\0" \
-       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-       "update_sd_firmware=" \
-               "if test ${ip_dyn} = yes; then " \
-                       "setenv get_cmd dhcp; " \
-               "else " \
-                       "setenv get_cmd tftp; " \
-               "fi; " \
-               "if mmc dev ${mmcdev}; then "   \
-                       "if ${get_cmd} ${update_sd_firmware_filename}; then " \
-                               "setexpr fw_sz ${filesize} / 0x200; " \
-                               "setexpr fw_sz ${fw_sz} + 1; "  \
-                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
-                       "fi; "  \
-               "fi\0" \
-       "mmcargs=setenv bootargs console=${console},${baudrate} " \
-               "root=${mmcroot}\0" \
-       "loadbootscript=" \
-               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-       "bootscript=echo Running bootscript from mmc ...; " \
-               "source\0" \
-       "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
-       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-       "mmcboot=echo Booting from mmc ...; " \
-               "run mmcargs; " \
-               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-                       "if run loadfdt; then " \
-                               "bootm ${loadaddr} - ${fdt_addr}; " \
-                       "else " \
-                               "if test ${boot_fdt} = try; then " \
-                                       "bootm; " \
-                               "else " \
-                                       "echo WARN: Cannot load the DT; " \
-                               "fi; " \
-                       "fi; " \
-               "else " \
-                       "bootm; " \
-               "fi;\0" \
-       "netargs=setenv bootargs console=${console},${baudrate} " \
-               "root=/dev/nfs " \
-               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-       "netboot=echo Booting from net ...; " \
-               "run netargs; " \
-               "if test ${ip_dyn} = yes; then " \
-                       "setenv get_cmd dhcp; " \
-               "else " \
-                       "setenv get_cmd tftp; " \
-               "fi; " \
-               "${get_cmd} ${uimage}; " \
-               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-                               "bootm ${loadaddr} - ${fdt_addr}; " \
-                       "else " \
-                               "if test ${boot_fdt} = try; then " \
-                                       "bootm; " \
-                               "else " \
-                                       "echo WARN: Cannot load the DT; " \
-                               "fi; " \
-                       "fi; " \
-               "else " \
-                       "bootm; " \
-               "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-       "mmc dev ${mmcdev};" \
-       "if mmc rescan; then " \
-               "if run loadbootscript; then " \
-               "run bootscript; " \
-               "else " \
-                       "if run loaduimage; then " \
-                               "run mmcboot; " \
-                       "else run netboot; " \
-                       "fi; " \
-               "fi; " \
-       "else run netboot; fi"
-
-#define CONFIG_ARP_TIMEOUT     200UL
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
-#define CONFIG_SYS_PROMPT              "U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE              256
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS             16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START       0x10000000
-#define CONFIG_SYS_MEMTEST_END         0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
-
-#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
-#define CONFIG_SYS_HZ                  1000
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE               (128 * 1024)
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
-#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_ENV_SIZE                        (8 * 1024)
-
-#define CONFIG_ENV_IS_IN_MMC
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
-#endif
-
-#define CONFIG_OF_LIBFDT
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
-#endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
index 76f7812069057b1daf69663d36f574ee9377b460..a396acf2e69172fe340a7c2cf2eb651ff9e87b52 100644 (file)
@@ -30,7 +30,7 @@
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
 
-#include "mx6qsabre_common.h"
+#include "mx6sabre_common.h"
 
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 #if defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h
deleted file mode 100644 (file)
index 44f07cb..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the Freescale i.MX6Q SabreSD board.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MX6QSABRESD_CONFIG_H
-#define __MX6QSABRESD_CONFIG_H
-
-#define CONFIG_MACH_TYPE       3980
-#define CONFIG_MXC_UART_BASE   UART1_BASE
-#define CONFIG_CONSOLE_DEV             "ttymxc0"
-#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
-#define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"
-#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
-
-#include "mx6qsabre_common.h"
-
-#define CONFIG_SYS_FSL_USDHC_NUM       3
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV         1       /* SDHC3 */
-#endif
-
-#endif                         /* __MX6QSABRESD_CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
new file mode 100644 (file)
index 0000000..53cc559
--- /dev/null
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRE_COMMON_CONFIG_H
+#define __MX6QSABRE_COMMON_CONFIG_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                   ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE            RGMII
+#define CONFIG_ETHPRIME                        "FEC"
+#define CONFIG_FEC_MXC_PHYADDR         1
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY               1
+
+#define CONFIG_LOADADDR                        0x12000000
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "script=boot.scr\0" \
+       "uimage=uImage\0" \
+       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       "fdt_addr=0x11000000\0" \
+       "boot_fdt=try\0" \
+       "ip_dyn=yes\0" \
+       "console=" CONFIG_CONSOLE_DEV "\0" \
+       "fdt_high=0xffffffff\0"   \
+       "initrd_high=0xffffffff\0" \
+       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+       "mmcpart=1\0" \
+       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+       "update_sd_firmware=" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "if mmc dev ${mmcdev}; then "   \
+                       "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+                               "setexpr fw_sz ${filesize} / 0x200; " \
+                               "setexpr fw_sz ${fw_sz} + 1; "  \
+                               "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+                       "fi; "  \
+               "fi\0" \
+       "mmcargs=setenv bootargs console=${console},${baudrate} " \
+               "root=${mmcroot}\0" \
+       "loadbootscript=" \
+               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootm ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootm; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootm; " \
+               "fi;\0" \
+       "netargs=setenv bootargs console=${console},${baudrate} " \
+               "root=/dev/nfs " \
+               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+       "netboot=echo Booting from net ...; " \
+               "run netargs; " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${uimage}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "bootm ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootm; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootm; " \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+       "mmc dev ${mmcdev};" \
+       "if mmc rescan; then " \
+               "if run loadbootscript; then " \
+               "run bootscript; " \
+               "else " \
+                       "if run loaduimage; then " \
+                               "run mmcboot; " \
+                       "else run netboot; " \
+                       "fi; " \
+               "fi; " \
+       "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE                        (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
new file mode 100644 (file)
index 0000000..76675f4
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRESD_CONFIG_H
+#define __MX6QSABRESD_CONFIG_H
+
+#define CONFIG_MACH_TYPE       3980
+#define CONFIG_MXC_UART_BASE   UART1_BASE
+#define CONFIG_CONSOLE_DEV             "ttymxc0"
+#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
+#define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"
+#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
+
+#include "mx6sabre_common.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV         1       /* SDHC3 */
+#endif
+
+#endif                         /* __MX6QSABRESD_CONFIG_H */